Z89C00 instruction set, consisting basic instructions, optimized high

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Z89C00 instruction set, consisting basic instructions, optimized high

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Z89C00 instruction set, consisting basic instructions, optimized high code density reduced execution time. Single-cycle instruction execution possible most instructions, including multiplications operations. format Codes addressing modes given generally required. assembler removes burden hand constructing instruction format. Mnemonics conveniently provided which assembler translates. system designer refer instruction format assistance debugging.
Instruction Summary
instruction broken down into following types instructions: Accumulator Modification Arithmetic Manipulation Load Logical Multiplication Program Control Rotate Shift
following tables list instructions pertinent each these groups.
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP following mnemonics used instruction format: Instruction Format Mnemonics Mnemonic const dest Description Address Accumulator Modification Bank Condition Code Constant Expression Destination Address Destination Value Flag Modification Code Register Pointer Source Address Source Value
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Accumulator Modification Instructions Mnemonic
Operands <cc>, <src> <cc>, <cc>, <cc>,
Instruction Absolute Value Comparison Decrement Increment Negate
Arithmetic Instructions Mnemonic Operands <cc>, <src> <src> Instruction Compare Subtract
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Manipulation Instructions Mnemonic CIEF COPF SIEF SOPF Operands None None None None None None Instruction Clear Carry Flag Clear Interrupt Enable Flag Clear Overflow Protection Flag Carry Flag Interrupt Enable Flag Overflow Protection Flag
Load Instructions Mnemonic PUSH Operands <dest>, <src> <dest> <src> Instruction Load Push
Logical Instructions Mnemonic Operands <src> <src> <src> Instruction Logical Logical Logical Exclusive
Multiplication Instructions Mnemonic MPYA MPYS Operands <src1>, <src2> <src1>, <src2> <src1>, <src2> Instruction Clear, Load, Multiply Add, Load, Multiply Subtract, Load, Multiply
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Program Control Instructions Mnemonic CALL Operands None Instruction Call Procedure Jump Return
Rotate Shift Instructions Mnemonic Operands <cc>, <cc>, <cc>, <cc>, Instruction Rotate Left Rotate Right Shift Left Logical Shift Right Arithmetic
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INSTRUCTION OPERANDS
Operands variety instructions offered obtained from Register Pointers, Data Pointers, Hardware Registers, Direct Addressing, Immediate Data Memory. There nine distinct types instruction operands. Instruction Operand Summary Symbolic Name Syntax <pregs> <dregs> <hwregs> <accind> <direct> <limm> <simm> <regind> Pn:b Dn:b EXTn, <const exp> #<const exp> #<const exp> @Pn:b @Pn:b+ @Pn:b+Loop @Pn:b-Loop @Dn:b @@Pn:b @@Pn:b+ @@Pn:b+Loop @@Pn:b-Loop Description Register Pointer Data Pointer Hardware Registers Accumulator Indirect Direct Address Expression Long (16-Bit) Immediate Short (8-Bit) Immediate Value Indirect Addressing
<memind> @Dn:b
Indirect Addressing
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP These instruction operands further described below with examples. Instruction Mnemonics/Operands Instruction MPYA PUSH P2:0, #%F2 @P2:0 #%3CF5 @@P2:0 @D2:0 D1:1 Mnemonic/Operand Representation MPYA PUSH <pregs>, <simm> <hwreg>, <regind> <hwreg>, <accind> <hwreg>, <limm> <memind> <memind> <direct> <dregs>
=L/2*
<pregs> register pointer mode used loading pointer with appropriate address. This address references location storing requested data. pointer also used store 8-bit data when used temporary register. pointers connected lower bits D-bus. Instruction loads Pointer Bank0 with value F2H. <regind> register indirect mode used indirect access RAM. noted instruction register indirect address method used obtaining operand multiply with accumulator. <dregs> data-pointer mode used indirect addressing method similar @P2:0. data pointers access lower bits each bank. Instruction uses this indirect addressing PUSH information onto stack. <memind> Pointer data registers used access program memory. Both commonly used reference program memory. Instructions display this addressing method. When either pointer automatically incremented. This assists transfer sequential data. <accind> Another method indirect addressing accumulator storing address. Instruction shows this method. <direct> absolute address given direct mode. range between (000H 1FFH) used. accumulator used conjunction with this method source destination operand. Instruction displays accumulator destination. <limm> This indicates long immediate load. 16-bit word copied directly from operand into specified register memory. Instruction uses this method. <simm> This only used immediate transfer 8-bit data operand specified pointer.
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INSTRUCTION FORMAT
following section discusses instruction format that specifies processor action taken. This information consists Code, destination, source, other special bits. assembler makes this operation transparent user providing mnemonics software developer use. Occasionally, developer refer instruction format development code assist debugging. Examples provided clarify various instruction formats explain specific patterns developed evaluated. Most instructions require 16-bit word containing necessary information processor execute instruction correctly. This process requires clock cycle execution. Immediate addressing, immediate operands, JUMP CALL instructions require 16-bit words (two clock cycles). Each instruction type unique Code format differentiate various instructions. Different operations also have unique formats. variables used instruction format depict bits that determined instruction used.
Formats
Code format each instruction different, allowing processor differentiate between instructions. example, (clear, load, multiply) instruction requires that operands (for example, P0:1 P2:0) defined instruction. @P0:1, @P2:0
Code
%DQN
P0:1
P2:0
(increment) instruction requires that condition modification code specified.
Code
Condition Code
Modification Code
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Formats
instructions have same Code with accumulator modification format. last four bits, modification code, determine type operation accumulator performs.
Code
Condition Code
Modification Code
Code
Condition Code
Modification Code
INSTRUCTION CODES
possible values series bits register forms patterns called codes. types codes include: Condition Codes Accumulator Modification Code Flag Modification Codes Source/Destination Field Designators Register Pointer/Data Pointer
following tables list options available their corresponding instructions.
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Condition Codes
Condition codes used accumulator modification, CALL, JUMP instructions. Condition Code Bits Code 00000 00001 00010 00011 00100 00101 00110 00111 01xxx 10000 10001 10010 10011 10100 10101 10110 10111 11xxx Mnemonic Code Value Condition Code Value Condition Code False Unused User Zero User Carry Zero (Not Equal) Overflow Plus (Not Negative) Unused True Unused User Zero User Carry Zero (Equal) Overflow Minus (Negative) Unused
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Accumulator Modification Codes
Accumulator modification codes determine type modification made value accumulator. Condition codes also used with CALL, JUMP instructions.
Accumulator Modification Bits Code 0000 0001 0010 0011 0100 0101 0110 0111 Mnemonic Operation Rotate Right Rotate Left Shift Right Shift Left Increment Decrement Negate Absolute
Flag Modification Codes
Flag modifications initialize set/reset bits accommodating interrupts, overflows, carrys.
Flag Modification Bits Code xx10 xx11 x1x0 x1x1 1xx0 1xx1 Mnemonic CIEF SIEF COPF SOPF Operation Clear Carry Carry Clear Interrupt Enable Interrupt Enable Clear Overflow Protection Overflow Protection Flag Value
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Source/Destination Field Designators
Register pointers data pointers provide convenient access data. pointers used source destination field instructions. specific codes listed below. register pointer offers optional incrementing decrementing. This option specified instruction: @P2:1+
Register Pointer/ Data Pointer Bits Code 00xx 01xx 10xx 11xx xx00 xx01 xx10 0011 0111 1011 1111 Mnemonic -1/loop +1/loop P0:0 P0:1 P1:0 P1:1 P2:0 P2:1 D0:0 D0:1 D1:0 D1:1 D2:0 D2:1 D3:0 D3:1
Data pointers automatically incremented when accessing program memory (for example, @D0:0) require incrementing option. Code xx11 format designated data pointer when source/destination format used. Additional source/destination designators other hardware registers provided processor. determine data pointer, register pointer register used source/destination explained next section.
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP Register Bits Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Mnemonic STACK EXT0 EXTI EXT2 EXT3 EXT4 EXT5 EXT6 EXT7
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INSTRUCTION FORMAT EXAMPLES
Some examples help clarify codes used instruction format. types instruction formats used. Instruction Format
Code
%DQN
Destination
Source
next page more format examples.
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=L/2* Accumulator Modification Format Code NOTES:
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Condition Code
Modification
Variables used instruction format depict bits that determined instruction used. General Instruction Format requires Code, bank bit, destination source addresses. example @P2:1+
Load Instruction Format Example
Code
%DQN
Destination
Source
Code (0000001) provides unique signature command. processor uses this signature determine format instruction. bank high (equal instruction definition (Pn:b). destination code 0011 which corresponds accumulator. source 0110 corresponds option P2:0 P2:1. bank clarifies that processor loads accumulator with referenced operand given Pointer Bank1 (P2:1). NOTE: source destination fields obtained from register pointers, data pointers, registers. Code specifies type source destination. Code 0000101 specifies that source indirect address program memory (@@P0:0 @D0:0) destination register.
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Instruction Format Listing
Below listing instruction formats instructions applicable each. NOTES: Several instructions provide variety addressing modes obtaining operands; therefore, same instruction have several different formats depending addressing mode used. variables used instruction format depict bits that determined instruction used.
General Instruction Format Example
Code
%DQN
Destination
Source
General Instruction Format Mnemonic MPYA MPYS PUSH A,@D1:1 A,P2:0 Operands @P0:0 @P0:1,@P0:0 @P1:1,@P2:0,0N @P1:1-loop,@P2:0+,0N D0:0 Code 1000001 0000 0000 1100110 0000 0111 0110000 0000 0001 0000000 0011 0111 1011011 0000 0000 1001011 0001 0010 0011011 1001 0110 0000000 0001 0101 0000001 0101 0011 0000000 0110 0101 0010101 0000 0111 1111001 0000 0010 Representation 8200 AB07 6001 0037 B700 9712 3796 0015 0253 0065 2B07 F202
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=L/2* Accumulator Modification Format
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Code
Condition Code
Modification
Accumulator Modification Format Mnemonic Operands NU0, Code 1001000 10101 0111 1001000 00000 0101 1001000 00101 0100 1001000 00000 0110 1001000 00010 0000 1001000 00111 0001 1001000 10100 0011 1001000 10011 0010 Representation 9157 9005 9054 9006 9020 9071 9143 9132
Flag Modification Format
Code
Condition Code
Flag Modification
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Flag Modification Format Mnemonic CIEF COPF SIEF SOPF Code 1001010 00000 0010 1001010 00000 0100 1001010 00000 1000 1001010 00000 0011 1001010 00000 0101 1001010 00000 1001 Representation 9402 9404 9408 9403 9405 9409
Direct Internal Addressing Format Example
Code
9-Bit Internal Address
Direct Internal Addressing Format Mnemonic Operands %12, Code 1000011 011111111 1010011 011111111 0110011 011111111 0000111 000010010 Representation 86FF A6FF 66FF 0E12
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=L/2* Short Immediate Addressing Format
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Code
Register Pointer
8-Bit Immediate Address/Data
Short Immediate Addressing Format Mnemonic Operands P1:1, #%FA Code 00011 11111010 Representation 1DFA
Long Immediate Addressing Format
Code
%DQN
Destination
Source
16-Bit Address/Data
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Long Immediate Addressing Format Mnemonic PUSH Operands #%1234 26A4 #%6FFC #%C32C #%2444 #%AFC2 Representation 8800 1234 A800 26A4 0810 6FFC 0850 C32C 2800 2444 E800 AFC2
JUMP, CALL Format Example
Code
Condition Code
Used
16-Bit Address
Jump, Call Format Mnemonic CALL Operands Representation 4800 0004 4D30 0004
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INSTRUCTION TIMING
provides single cycle instruction execution. This achieved through independent data memory program memory buses offered modified Harvard architecture pipeline instruction execution. This method provides overlapping instruction fetch execution cycles. Figure depicts this operation. first instruction takes clock cycles execute; subsequent executions occur single cycle. instruction fetch cycles have same machine timing regardless whether external internal memory used. Because contains twolevel pipeline, JUMP CALL instructions disrupt execution process these two-byte instructions, second byte being fetched while first byte executing. Because processor knows that instruction JUMP CALL, second byte transferred program counter correct address fetched into pipeline. disruption flushing pipeline needed, pipeline flow affected when program counter destination load. Because load (LD) instruction single word instruction, next instruction fetched while load execution taking place. compensate instruction pipeline, that instruction executed NOP.
Fetch Execute Fetch Execute
Figure Pipeline Execution
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INSTRUCTION CODES
table below summarizes essential information about instruction set. Instruction Codes Inst
Description
Absolute Value Addition
Code Synopsis
1001000 1001000 1001001 1000001 1000100 1000101 1000011 1000001 1000000 ADD<dest>, <src>
Operands
A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A<regind> A,<hwregs>
Words Cycles Examples
P0:0 D0:0 #%1234 @@P0:0 @P1:1 P2:0 D0:1 #%1234 @@P1:0 @1:2+LOOP EXT3 CALL sub1 CALL sub2 CIEF COPF
ABS[<cc>,] <src> <cc>,A
Bitwise
1011001 1010001 1010100 1010101 1010001 1010001 1010000
<dest>, <src>
A,<pregs> A,<dregs> A,<limm> A,<memind> A,<direct> A,<regind> A,<hwregs>
CALL CIEF
Subroutine Call
0010100 0010100
CALL <cc>,<address> CIEF COPF
<cc>,<direct> <direct> None None None
Clear Carry Flag 1001010 Clear Carry Flag 1001010 1001010
COPF Clear Flag
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=L/2* Instruction Codes (Continued) Inst
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Description
Comparison
Code Synopsis
CP<src1>,<src2> 0111001 0110001 0110101 0110011 0110001 0110000 0110100
Operands
<pregs> <dregs> <memind> <direct> <regind> <hwregs> <Iimm>
Words Cycles Examples
P0:0 D3:1 @@P0:0 @P2:1+ STACK #%FFCF NIE, Label Label
Decrement Increment Jump
1001000 1001000 1001000 1001000 0100110 0100110
[<cc>,] <dest> [<cc>,] <dest> [<cc>,] <address>
<cc>, <cc>, <cc>, <direct> <direct>
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP Instruction Codes (Continued) Inst
=L/2*
Description
Code Synopsis
Operands
<dregs> <pregs> regind> <memind>, <memind> <direct> <direct>, <dregs>, <hwregs> <pregs>, <simm> <pregs>, <hwregs> <regind>, <limm> <regind>, <hwregs> <hwregs>, <pregs> <hwregs>, <dregs> <hwregs>, <limm> <hwregs>, <accind> <hwregs>, <memind> <hwregs>, <regind> <hwregs>, <hwregs>
Words Cycles Examples
D0:0 P0:1 @P1:1 @D0:0 124, D0:0, EXT7 P1:1, #%FA P1:1, EXT1 @P1:1, #%1234 @PM+, P0:0 D0:0 #%1234 D0:0
Load 0000000 Destination with 0000001 Source 0001001 0000001 0000101 0000011 0000111 0000100 0001100 0001010 0000110 0000010 0001001 0000001 0000100 0100101 0000101 0000001 0000000
<dest>,<src> <hwregs>
@P0:0-LOOP
EXT6
Notes: When <dest> <hwregs>, <dest> cannot When<dest> <hwregs> <src> <hwregs>, <dest> cannot EXTn <src> EXTn, <dest> cannot <src> <dest> cannot <src> When <src> <accind> <dest> cannot
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=L/2* Instruction Codes (Continued) Inst
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Description
Multiply
Code Synopsis
1010010 1010010 MLD<src1>, <src1> [,<bank switch>]
Operands
<hwregs>, <regind> <hwregs>, <regInd>, <bank switch> <regind>, <reglnd> <regInd>, <regind>, <bank switch>
Words Cycles Examples
A,@P0:0+LOOP
A,@P1:0, @P1:1, @P2:0 @P0:1, @P1:0,
1011011 1011011
Notes: src1 <regind> must bank register. Src2's <regind> must bank register. <hwregs> src1 cannot operands <hwregs>, <regind> <band switch> defaults OFF. operands <regind>, <bank switch> defaults MPYA Multiply 1010010 1010010 MPYA <src1>, <src2> [,<bank switch>] <hwregs>, <regind> <hwregs>, <regind>, <bank switch> <regind>, <reglnd> <regInd>, <regind>, <bank switch> MPYA @P0:0 MPYA @P1:0, MPYA @P1:1, @P2:0 MPYA@P0:1, @P1:0,
1011011 1011011
Notes: src1 <regind>, register must bank register. Src2's <regind> must bank register. <hwregs> src1 cannot operands <hwregs>, <regind> <bank switch> defaults OFF. operands <regind>, <bank switch> defaults
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP Instruction Codes (Continued) Inst Description Code Synopsis
MPYS <src1>, <src2> 0010010 0010010 [bank switch>]
=L/2*
Operands
Words Cycles Examples
MPYS Multiply Subtract
<hwregs>, <regind> <hwregs>, <regind>, <bank switch> <regind>, <regind> <regind>, <regind>, <bank switch>
MPYS @P0:0 MPYS @P1:0,OFF MPYS @P1:1, @P2:0 MPYS @P0:1, @P1:0,ON
0011011 0011011
Notes: src1 <regind> must bank register. Src2's <regind> must bank register. <hwregs> src1 cannot operands <hwregs>, <regind> <bank switch> defaults OFF. operands <regind>, <regind> <bank switch> defaults Negate Operation Bitwise 1101001 1100001 1100100 1100101 1100011 1100001 1100000 1001000 1001000 0000000 <dest>, <src> <cc>, <cc>, None NZ,A
<pregs> <dregs> <limm> <memind> <direct> <regind> <hwregs>
P0:1 D0:1 A,#%202 @@P2:1+
@P1:0-LOOP
EXT6
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=L/2* Instruction Codes (Continued) Inst
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Description
Value from Stack
Code Synopsis
0001010 0000100 0000010 0000000 <dest>
Operands
<pregs> <regs> <regind> <hwregs>
Words Cycles Examples
P0:0 D0:1 @P0:0 PUSH P0:0 PUSH D0:1 PUSH @P0:0 PUSH BU.S PUSH #%2345 PUSH PUSH @@P0:0 SIEF SOPF P1:1 D0:1 #%2C2C @D0:1 @P2:0-LOOP STACK
PUSH
Push Value onto Stack
0001001 0000001 0000001 0000000 0000100 0100101 0000101
PUSH <src>, <pregs>
<dregs> <regind> <hwregs> <limm> <accind> <memind>
SIEF SOPF
Return from Subroutine Rotate Left Rotate Right Flag Flag
0000000 1001000 1001000 1001000 1001000 1001010 1001010 1001000
<cc>, <cc>, SIEF SOPF <cc>, <dest>, <src>
None <cc>, <cc>, None None [<cc>,] None <cc>, <pregs> <dregs> <limm> <memind> <direct> <regind> <hwregs>
Shift Left Logical 1001000 Flag Shift Right Arithmetic Subtract 1001010 1001000 1001000 0011001 0010011 0010100 0010101 0010011 0010001 0010000
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=L/2*
Description
Bitwise Exclusive
Code Synopsis
1111001 1110001 1110100 1110001 1110011 1110001 1110000 <dest>, <src>
Operands
<pregs> <dregs> <limm> <memind> <direct> <regind> <hwregs>
Words Cycles Examples
P2:0 D0:1 #%3933 @P2:1+ @P2:0
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instruction set, consisting basic instructions, optimized high-code density reduced execution time. Single-cycle instruction execution possible pipeline other architectural features. This chapter discusses instruction provides examples assist explaining their function. table below contains description each instruction: Instruction Description Mnemonic Instruction Operands Instruction Format Operation Affected Flags Description Examples Mnemonic Expansion Lists possible types addressing methods specific instruction (ABS <cc>, Displays instruction format register indirect addressing. Displays operation sequence. Lists flags that affected operation. description operation instruction. simple example given display operation instruction registers affected. example includes initialization, instruction result. Cycles instruction length also given.
NOTE:
Each Assembly Instruction provided with example each addressing mode available specific instruction.
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#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP following mnemonics used instruction format: Instruction Format Mnemonics Mnemonic const dest Description Address Accumulator Modification Bank Condition Code Constant Expression Destination Address Destination Value Flag Modification Code Register Pointer Source Address Source Value
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Syntax: <cc>,
ABSOLUTE VALUE
Accumulator Modification Format: Code Operation: Affected Flags:
Condition Code
Modification
then -(ACC) accumulator 800000H (see below).
contents accumulator determined less then (negative number), absolute value accumulator calculated (accumulator replaced two's complement value). condition code provides additional method status flag evaluation before absolute value accumulator calculated. NOTE: accumulator contains 800000H, instruction stores value two's complement address 800000H sets Overflow Negative status bits. overflow protection provided. Accumulator Accumulator FFEB00H 0000H 001500H 1000H Cycles: Words:
Example: Initialization: Instruction: Result:
Because value accumulator less then zero, two's complement performed result placed accumulator. ABS(FFEBH)=001500H. carry this operation. Example: Initialization: Instruction: Result: <cc>, Accumulator Accumulator 456400H 456400H Cycles: Words:
condition code (negative bit) because accumulator value positive; therefore, instruction executed. 16&52
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Syntax: <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs>
ADDITION
Addition Format: Code %DQN
Destination
Source
Operation: Affected Flags:
<source> carry from most significant found. result accumulator negative. result addition exceeds upper (FFFFFH) lower (800000H) limit accumulator.
addressed data memory operand added accumulator. result loaded into accumulator. NOTE: lower eight bits accumulator unchanged during execution instruction.
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Example: Initialization: <regind> Cycles: Words:
123456H Accumulator P0:0 8746H Bank1: @P0:0 Instruction: 997A56H Result: 746H @P0:0 pointer P0:0 contains register location (4DH). contents register added accumulator obtain (874600H 123456H 997A56H). contained accumulator pointer left unchanged. direct addressing equivalent would (4DH decimal).
Example: Initialization:
<memind>
Cycles: Words:
123400H Accumulator P0:0 247AH Bank0: 0C12H Address: 247AH @@P0:0 Instruction: lE4600H Result: P0:0 247BH Bank0: pointer P0:0 contains register location (21H). contents this register have address. This address refers data that placed specified accumulator instruction. 123400H 0C1200H 1E4600H. When memory indirect addressing used, address automatically incremented. This provides convenient method accessing sequential data. @@P0:0+ would perform same operation also increment P0:0 content 22H.
Example:
<limm>
Cycles: Words:
123400H Initialization: Accumulator Instruction: #%0C12 Result: lE4600H immediate operand 0C12H added accumulator obtain sum. 123400H 0C1200H 1E4600H.
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Example: Initialization: A,<hwregs> Cycles: Words:
123400H Accumulator 0C12H Register Instruction: 1E4600H Result: contents register added accumulator obtain sum. 123400H 0C1200H 1E4600H. Transfer from <hwregs> possible from hardware registers.
Example: Initialization:
A,<direct>
Cycles: Words:
123400H Accumulator 0C12H Bank0: A,%F3 Instruction: 1E4600H Result: Register added accumulator obtain sum. 123400H 0C1200H 1E4600H. equivalent instruction (F3H decimal).
Example: Initialization:
<pregs>
Cycles: Words:
123400H Accumulator P0:0 P0:0 Instruction: 128A00H Result: Accumulator contents pointer register P0:0 added accumulator. 123400H 005600H 128A00H. Pointer Register connected lower bits D-bus. D-bus connected upper 16-bits P-bus. This causes pointer register operand become 005600H before being added accumulator.
Example: Initialization:
A,<dregs>
Cycles: Words:
123400H Accumulator 8746H Instruction: D0:1 Result: 997A00H 8746H contents data pointer D0:1 added accumulator. contained accumulator pointer left unchanged. data pointer contains 8746H. 16&52
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Syntax: <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm>
BITWISE
General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
<accumulator>. AND.<source> <accumulator> accumulator result less than accumulator result
Data stored specified accumulator instruction. lower eight bits accumulator cleared when execution this instruction occurs.
Example: Initialization:
<regind> Accumulator Bank1: @P0:1 Accumulator 123456H 8746H 020400H
Cycles: Words:
Instruction: Result:
data Bank1, referenced pointer stored specified accumulator using instruction. 123456H.AND.874600H 020400H.
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Example: Initialization: <memind> Cycles: Words:
123400H Accumulator P0:0 047AH Bank0: 8746H Address: 047AH @@P0:0 Instruction: 020400H Result: P0:0 247BH Bank0: pointer P0:0 contains register location (45H). contents this register address. This address refers data that placed specified accumulator instruction. 123400H.AND.874600H 020400H. When memory-indirect addressing utilized, address automatically incremented. This provides convenient method accessing sequential data. @@P0:0+ would perform same operation also increment P0:0 content 46H.
Example: Initialization: Instruction: Result:
<limm> Accumulator #%1234 Accumulator 362400H 122400H
Cycles: Words:
immediate operand 1234H accumulator address processed with instruction produce result, 362400H.AND.123400H 122400H.
Example: Initialization: Instruction: Result:
<simm> Accumulator #%1F Accumulator 123456H 001400H
Cycles: Words:
data immediate field contents accumulator processed with instruction. 123456H.AND.001F00H 001400H.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <hwregs> Accumulator Register 123400H OC12H 001000H Cycles: Words:
instruction send contents Register accumulator obtain result. 123400H.AND.0C1200H 001000H. Transfer from <hwregs> possible from hardware registers.
Example: Initialization: Instruction: Result:
<direct> Accumulator Bank0: 123400H 0C12H 001000H
Cycles: Words:
instruction send Register accumulator obtain result. 123400H OC1200H 001000H. equivalent instruction (F3H decimal).
Example: Initialization: Instruction: Result:
<pregs> Accumulator P0:0 P0:0 Accumulator 123400H 001400H
Cycles: Words:
instruction send contents pointer register P0:0 accumulator. 123400H.AND.005600H 001400H. Pointer Register connected lower bits D-bus. D-bus connected upper bits P-bus. This action causes pointer register operand become 005600H before being added accumulator.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: Instruction: Result: <dregs> Accumulator D0:1 00:0 Accumulator 123400H 2645H 020400H Cycles: Words:
data register, D0:0, used reference operand 2645H. instruction send this data register accumulator produce result. 123400H.AND.2645H 020400H.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
CALL
Syntax: Call Format: Code
SUBROUTINE CALL
CALL <cc>,<direct> CALL <direct>
Condition Code
Used
16-Bit Address Operation: Affected Flags: STACK 16-Bit Address None
current Program Counter (PC) register content incremented placed stack. address specified label CALL instruction then placed register. jump made appropriate subroutine condition code option used control execution CALL should occur.
Example: Initialization:
CALL <direct> FFT2 subroutine addr. Stack Level CALL FFT2 Stack Level Stack Level 1FFBH F234H 0025H F234H 1FFDH 0025H
Cycles: Words:
Instruction: Result:
call subroutine FFT2 places PC+2 FFDH) stack. information currently stack pushed stack. subroutine address then placed register. processor executes next instruction addressed FFT2 subroutine.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
CALL
Example: Initialization: CALL <cc>, <direct> FFT2 subroutine addr. Stack Level (User Zero Bit) CALL FFT2 Stack Level Stack Level 1FFBH F234H 0025H F234H 1FFDH 0025H Cycles: Words:
Instruction: Result:
condition code first tested processor before execution CALL instruction executed. Because enabled, CALL routine executed exactly previous example. condition code input processor that determines subroutine FFT2 should used. Another CALL instruction determine another subroutine, FFT1, should used.
Example: Initialization:
CALL <direct> FFT2 subroutine addr. Stack Level CALL FFT2 Stack Level Stack Level 1FFBH F234H 0025H F234H 1FFDH 0025H
Cycles: Words:
Instruction: Result:
call subroutine FFT2 places PC+2 FFDH) stack. information currently stack pushed stack. subroutine address then placed register. processor executes next instruction addressed FFT2 subroutine.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax: Flag Modification Format: Code Operation: Affected Flags:
CLEAR CARRY FLAG
Condition Code
Flag Modification
Zero Carry
Clear Carry Flag instruction resets carry flag with
Example: Initialization: Instruction: Result:
3000H 2000H
Cycles: Words:
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
CIEF
CIEF Syntax: Clear Flag Format
CLEAR INTERRUPT ENABLE FLAG
Code Operation: Affected Flags: Zero
Condition Code
Flag Modification
Clear Interrupt Enable Flag instruction sets flag
Example: Initialization: Instruction: Result:
CIEF CIEF 3080H 3000H
Cycles: Words:
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
COPF
CLEAR OVERFLOW PROTECTION FLAG
COPF Syntax: Flag Modification Format: Code Operation: Affected Flags: Zero
Condition Code
Flag Modification
Clear Overflow Protection Flag instruction resets flag
Example: Initialization: Instruction: Result:
COPF COPF 0100H 0000H
Cycles: Words:
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm> General Instruction Format: Code
COMPARISON
%DQN
Destination
Source
Operation: Affected Flags:
<source> appropriate status bits carry required operation. operands equal. operation exceeds (800000H) high limit (7FFFFFH) accumulator. result negative.
contents specified register instruction compared accumulator 16-bit mode. specified register subtracted from accumulator appropriate flags set. Because registers 16-bit, comparison with 24-bit accumulator requires that lower eight bits accumulator filled with zeros ensure accurate comparisons. instruction does affect contents accumulator except when overflow protection overflow occurs after execution compare. accumulator updates with appropriate (800000H) high (7FFFFFH) limit.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <regind> P2:1 Bank1: @P2:1 7A2500H 5463H 7A2500H 1000H Cycles: Words:
Instruction: Result:
operand referenced P2:1 subtracted from accumulator. 7A2500H 546300H 25C200H. Because comparison does yield set. content P2:1 register appended with eight additional bits. ensure consistent comparisons, accumulator must contain zeros lower eight bits. Also note that accumulator unaffected operation.
Example: Initialization:
<memind> P2:1 Bank1: Address: 5463H @@P2:1 P2:1 Bank1: 7A2500H 5463H OC12H 7A2500H 5464H 1000H
Cycles: Words:
Instruction: Result:
pointer P2:1 contains register location (A4H). contents this register have address. This address refers data that compared accumulator. 7A2500H OC1200H 6E1300H. Because comparison does yield set. When memory indirect addressing used, address automatically incremented. This action provides convenient method accessing sequential data. A,@@P2:1 performs same operation also increments P2:1 content A5H.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: Instruction: Result: <limm> #%7A25 7A2500H 7A2500H 3000H Cycles: Words:
immediate operand compared accumulator. Because they equal, Zero Flag set.
Example: Initialization:
<hwregs> 7A2500H 0000H 7A25H 7A2500H 3000H
Cycles: Words:
Instruction: Result:
<hwreg> operand subtracted from accumulator. Because operands equal, zero-status High. Comparison <hwregs> possible from hardware registers.
Example: Initialization: Instruction: Result:
<direct> Accumulator Bank0 7A2500H 5463H 7A2500H 1000H
Cycles: Words:
Register compared accumulator. 7A2500H 546300H 25C200H. equivalent instruction A,243 (173H decimal).
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <pregs> Accumulator P0:0 P0:0 Accumulator 123400H 123400H 1000H Cycles: Words:
contents pointer register P0:0 compared accumulator. 123400H 005600H 11DE00H Pointer Register connected lower bits D-bus. D-bus connected upper bits P-bus. This action causes pointer register operand become 005600H before being compared accumulator.
Example: Initialization: Instruction: Result
<dregs> D2:1 D2:1 7A2500H 5463H 7A2500H 1000H
Cycles: Words:
contents data pointer D2:1 compared accumulator. 7A2500H 546300H 25C200H.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: <cc>, Decrement Format: Code Operation: Affected Flags:
DECREMENT
Condition Code
Modification
carry required operation result decrement results value less then upper (7FFFFFH) lower (800000H) limits exceeded.
accumulator decrements condition code used test specific condition decrement occur.
Example: Initialization: Instruction: Result:
7A2500H 7A24FFH
Cycles: Words:
value accumulator decrements
Example: Initialization: Instruction: Result:
<cc>, 7A2500H 7A2500H
Cycles: Words:
Because accumulator negative, decrement instruction executed.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax: <cc>, Increment Format: Code Operation: Affected Flags:
INCREMENT
Condition Code
Modification
carry required operation. result results value less then upper (7FFFFFH) lower (800000H) limits exceeded.
Increment instruction adds accumulator. condition code used test specific condition increment occur.
Example: Initialization: Instruction: Result:
<cc>, 7A2500H 7A2500H
Cycles: Words:
Because accumulator negative, increment instruction executed.
Example: Initialization: Instruction: Result:
7A2500H 7A2501H
Cycles: Words:
value accumulator incremented
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: Jump Format: Code <cc>, <direct> <direct>
JUMP
Condition Code
Used
16-Bit Address Operation: Affected Flags: 16-Bit address None
instruction places address referenced location Program Counter (PC). Because processor obtains next instruction address from processor jumps appropriate location. condition code used test specific condition JUMP occur.
Example: Initialization:
<cc>, <direct> Routine address User input NUO, Routine 1455H 1343H 1343H
Cycles: Words:
Instruction: Result:
Because User input High, condition code met. Therefore, JUMP instruction does occur. User input used this example control flow software.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <direct> Routine address Routine 1455H 1343H 1455H Cycles: Words:
value program counter replaced Routine address (1455H).
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax:
LOAD
<pregs> <direct>, <hwregs>, <dregs> A,<dregs> <dregs>, <hwregs> <hwregs>,<limm> <memind> <pregs>, <simm> <hwregs>, <accind> A,<direct> <pregs>, <hwreg> <hwregs>, <memind> A,<regind> <regind>, <limm> <hwregs>, <regind> <hwregs> <hwregs>,< pregs> <hwregs>, <hwregs> General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
<source> <destination> None
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
LOAD command provides ability transfer data many different locations processor. Access hardware registers, accumulator, stack, pointers memory provides flexibility. transfers across various internal buses transparent user. NOTES: load using register provides automatic multiply operation. This provides ability obtain operand from register location. register read-only register, therefore destination load cannot register. EXTN, EXTN allowed. LOAD accumulator clears lower eight bits 24-bit accumulator.
Example: Initialization:
<regind> P2:1 Bank1: @P2:1 7A2500H 5463H 546300H
Cycles: Words:
Instruction: Result:
Indirect addressing through pointer registers provides access data. data Bank register transferred accumulator. contents P2:1 register appended with eight additional bits. This added ensure correct arithmetic comparison.
Example: Initialization:
<memind> Accumulator P0:0 Bank0: Address: 247AH @@P0:0 P0:0 Bank0: 123400H 247AH 200H 247BH
Cycles: Words:
Instruction: Result:
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
pointer P0:0 contains register location (21H). contents this register have address. This address refers data that loads accumulator. When memory indirect addressing used address automatically incremented. This provides convenient method accessing sequential data. @@P0:0+ performs same operation also increments P0:0 content 22H.
Example: Initialization: Instruction: Result:
<limm> Accumulator #%2474 123400H 247400H
Cycles: Words:
immediate operand 2474H loads accumulator.
Example: Initialization: Instruction: Result:
<hwregs> Accumulator Register 123400H OC12H OC1200H
Cycles: Words:
contents Register loaded accumulator. Transfer from <hwregs> possible from hardware registers.
Example: Initialization: Instruction: Result:
<direct> Accumulator Bank0 123400H OC12H OC1200H
Cycles: Words:
Register loaded accumulator. equivalent instruction A,243 (F3H decimal).
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <dregs> Accumulator D0:1 123400H 8746H 874600H 8746H Cycles: Words:
contents data pointer D0:1 load accumulator.
Example: Initialization: Instruction: Result:
<pregs> Accumulator P0:0 P0:0 Accumulator 123400H 005600H
Cycles: Words:
contents pointer register P0:0 loaded accumulator. Pointer Register connected lower bits D-bus. D-bus connected upper bits P-bus. This operation causes pointer register operand become 005600H before being loaded into accumulator.
Example: Initialization: Instruction: Result:
<direct>, Accumulator Bank0: %3C, Accumulator Bank0: 123400H 5678H 123400H 1234H
Cycles: Words:
current value accumulator loaded register addressed instruction (3CH). equivalent instruction (3CH decimal).
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: Instruction: Result: <pregs>, <simm> P2:0 Bank0: P2:0, #%3F P2:0 Bank0: 254645H 254645H Cycles: Words:
immediate data (3FH) loaded into pointer register P2:0. This action provides convenient method initializing pointer registers.
Example: Initialization: Instruction: Result:
<pregs>, <hwregs> P0:1, 2376H 2376H
Cycles: Words:
lower 8-bits register transferred pointer register P0:1. Transfer from <hwregs> possible from hardware registers.
Example: Initialization: Instruction: Result:
<regind>, <limm> P0:1 Bank0: @P0:1, #%35B8 P0:1 Bank1: 2376H 35B8H
Cycles: Words:
immediate operand 35B8H transferred Register Bank1.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <hwregs>, <pregs> P2:0 Register X,P2:0 P2:0 Register 8B87H 002FH Cycles:1 Words:
contents P2:0 pointer (2FH) loaded into register. Transfer <hwreg> possible hardware registers except read-only register.
Example: Initialization: Instruction: Result:
<hwregs>, <dregs> D2:0 Accumulator A,D2:0 D2:0 Accumulator 3C87H 8BB722H 3C87H 3C8700H
Cycles: Words:
contents D2:0 pointer (3C87H) loaded into accumulator. Transfer <hwregs> possible hardware registers except read-only register.
Example: Initialization: Instruction: Result:
<hwregs>, <limm> Stack0 Stack1 Stack, #%35B8 Stack0 Stack1 8B2FH 0000H 35B8H 8B2FH
Cycles: Words:
immediate data pushed onto stack. Previous stack data pushed stack. Transfer <hwregs> possible hardware registers except read-only register.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: <hwregs>, <accind> EXT7 Register Accumulator 77B6H EXT7, EXT7 Register Accumulator 8B87H 77B6H 387DH 387DH 77B6H Cycles: Words:
Instruction: Result:
contents Register 77B6H (387DH) loaded into External Register Transfer <hwregs> possible hardware registers except read-only register accumulator register.
Example: Initialization:
<hwregs>, <memind> Register P0:0 Bank0: Address: 247AH @@P0:0 Register P0:0 Bank0: 1234H 247AH 0C12H 0C12H 247BH
Cycles: Words:
Instruction: Result:
pointer P0:0 contains register location (21H). contents this register have address. This address refers data that loads register. Transfer <hwregs> possible hardware registers except read-only register. When memory indirect addressing used address automatically incremented. This provides convenient method accessing sequential data. A,@@P0:0+ performs same operation also increments P0:0 content 22H.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <hwregs>, <regind> Register Bank1: @P2:1 Register 7A25H 5463H 5463H Cycles: Words:
Instruction: Result:
Indirect addressing through pointer registers provides access data. data bank register transferred register. Transfer <hwreg> possible hardware registers except read-only register.
Example: Initialization: Instruction: Result:
<hwregs>, <hwregs> Register EXT5 Register EXT5 Register EXT5 Register 7A25H 789AH 789AH 789AH
Cycles: Words:
EXT5 Register contents transferred register. Transfer <hwregs> possible hardware registers except read-only register.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
<hwregs>, <hwregs>, <regind>, <regind>,
MULTIPLY
<regind> <regind>,<bank switch> <regind> <regind>,<bank switch>
Syntax:
Multiply Format: Code %DQN 6ZLWFK
Pn:1
Pn:0
Operation:
Affected Flags:
<regind> <regind> Multiplier: When bank switch <regind>, <regind> :(@Pn:1) (@Pn:0) <hwregs>, <regind> :<hwregs> (@Pn:0) When bank switch OFF, <regind>, <regind> :(@Pn:0) (@Pn:0) <hwregs>, <regind> :<hwregs> <hwregs> Note: <dst> <regind>, bank switch default <dst> <hwregs>, bank switch default OFF. Accumulator:
This instruction provides capability multiply operands from each bank single cycle. first operand referenced Pn:1 placed register second Pn:0 placed register (MLD @Pn:1, @Pn:0). After multiplication performed, result placed Product Register register accumulator cleared. hardware register used instead operand.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <regind>, <regind> P0:0 Bank0: Bank1: @P0:1, @P0:0 365400H 4561H 1123H 0949DAH 000000H Cycles: Words:
Instruction: Result:
instruction multiplies operands referenced P0:1 P0:0. operand consists 4561H 1123H. multiplication results 0949DA86H. Because most significant bits saved, register contains 0949DAH.
Example: Initialization:
Instruction: Result:
<regind>, <regind>, <bank switch>Cycles: Words: 365400H P0:0 P0:1 4561H Bank0: 1123H Bank1: @P0:1, @P0:0, 259ADDH 000000H
bank switch option provides ability multiply @P0:0 @P0:0. default switch shown previous example. switch then @P0:0 placed registers multiplied together. result 259ADD82H. Because most significant bits saved, register contains 259ADDH.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: <hwregs>, <regind> Accumulator P0:0 Bank0: EXT3 Register EXT3, @P0:0 Accumulator 365400H 124670H 4561H 768BH 6DC8DEH 000000H Cycles: Words:
Instruction: Result:
instruction places EXT3 Register contents into both registers. multiplication results 6DC8DEF2H. Because most significant bits saved, register contains 6DC8DEH. next example illustrates multiplication <hwregs> <regind> operands. Transfer <hwregs> possible hardware registers except read-only register, register, accumulator.
Example: Initialization:
Instruction: Result:
<hwregs>, <regind>, <bank switch>Cycles: Words: 365400H Accumulator 124670H P0:0 4561H Bank0: 768BH EXT3 Register EXT3, @P0:0, 4040C3H 000000H Accumulator
bank switch option provides ability multiply EXT3 @P0:0 EXT3 EXT3. default switch OFF, shown first example. switch then EXT3 placed register GP0:0 register. multiplication results 4040C356H. Because most significant bits saved, register contains 4040C3H. Transfer <hwregs> possible hardware registers except read-only register, register, accumulator.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
MPYA
Syntax: MPYA MPYA MPYA MPYA Multiply/Add Format: Code
MULTIPLY
<hwregs>, <hwregs>, <regind>, <regind>, <regind> <regind>, <bank switch> <regind> <regind>, <bank switch>
%DQN 6ZLWFK
Pn:1
Pn:0
Operation:
*(@Pn:0) Multiplier: When bank switch MPYA <regind>, <regind>: (@Pn:1) (@Pn:0) MPYA <hwregs>, <regind>: <hwregs>* (@Pn:0) When bank switch OFF, MPYA <regind>, <regind> (@Pn:0) (@Pn:0) MPYA <hwreg>, <regind> <hwregs> <hwregs> Note: <dst> <regind>, bank switch default <dst> <hwregs>, bank switch default OFF. carry from most significant performed. result accumulator negative. result addition exceeds upper (7FFFFFH) lower (800000H) limit accumulator.
Accumulator: Affected Flags:
This instruction provides capability multiply operands register with accumulator. operations occur simultaneously. register contents moved accumulator while multiplication occurring. After cycle complete, contained accumulator product register.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
MPYA
Example: Initialization: MPYA <regind>, <regind> P0:0 P0:1 Bank0: Bank1: MPYA @P0:1, @P0:0 365400H 4040C3H 4561H 1123H Cycles: Words:
Instruction: Result:
0949DAH 7694C3H
register accumulator added together produce 7694C3H. multiplication results 0949DA86H. Because most significant bits saved, register contains 0949DAH.
Example: Initialization:
Instruction: Result:
MPYA <regind>, <regind>, <bank switch>Cycles: Words: 365400H 4040C3H P0:0 4561H Bank0: 1123H Bank1: MPYA @P0:1, @P0:0, 259ADDH 7694C3H
register accumulator added together produce 769403H. bank switch option provides ability multiply @P0:0 @P0:0. default switch shown previous example. switch OFF, then @P0:0 placed registers multiplied together. result 259ADD82H. Because most significant bits saved, register contains 259ADDH.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
MPYA
Example: Initialization: MPYA <hwregs>, <regind> P0:0 Bank0: EXT3 Register MPYA EXT3, @P0:0 365400H 4040C3H 4561H 768BH 6DC8DEH 7694C3H Cycles: Words:
Instruction: Result:
register accumulator added together produce 7694C3H. instruction places EXT3 Register content into both register. multiplication results 6DC8DEF2H. Because most significant bits saved, register contains 6DC8DEH. next example illustrates multiplication <hwregs> <regind> operands. Transfers <hwregs> possible hardware registers except read-only register, register accumulator.
Example: Initialization:
Instruction: Result:
MPYA <hwregs>, <regind>, <bank switch>Cycles: Words: 365400H 4040C3H P0:0 4561H Bank0: 768BH EXT3 Register MPYA EXT3, @P0:0, 4040C3H 7694C3H
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
MPYA
register accumulator added together produce 7694C3H. bank switch option provides ability multiply EXT3 @P0:0 EXT3 EXT3. default switch evaluated previous example. switch then EXT3 placed register @P0:0 register. multiplication results 4040C356H. Because most significant bits saved, register contains 4040C3H. Transfers <hwregs> possible hardware registers except read-only register, register accumulator
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
MPYS
Syntax: MPYS MPYS MPYS MPYS Multiply Subtract: Code
MULTIPLY SUBTRACT
<hwregs>, <hwregs>, <regind>, <regind>, <regind> <regind>, <bank switch> <regind> <regind>, <bank switch>
%DQN 6ZLWFK
Pn:1
Pn:0
Operation:
P->ACC Pn:1) (@Pn:0) Multiplier: When bank switch MPYS <regind>, <regind>: (@Pn:1)(@Pn:0)-> MPYS hwregs>, <regind>: <hwregs>(@Pn:0)-> When bank switch OFF, MPYS <regind>, <regind> (@Pn:0)(*Pn:0) MPYS <hwregs>, <regind> <hwregs> <hwregs>
NOTE:
<dst> <regind>, bank switch default <dst> <hwregs>, bank switch default OFF. carry from most significant performed. result accumulator negative. result addition exceeds upper (7FFFFFH) lower (800000H) limit accumulator.
Accumulator: Affected Flags:
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
MPYS
This instruction provides capability multiply operands subtract register from Accumulator. operations occur simultaneously. register contents moved accumulator while multiplication occurring. After cycle complete, difference contained accumulator product register. Example: Initialization: MPYS <regind>, <regind> P0:0 Bank0: Bank1: MPYS @P0:1, @P0:0 365400H 4040C3H 4561H 1123H 0949DAH 4040C3H Cycles: Words:
Instruction: Result:
register subtracted from accumulator produce difference 240D90H. multiplication results 0949DA86H. Because most significant bits saved, register contains 0949DAH.
Example: Initialization:
Instruction: Result:
MPYS <regind>,<regind>,<bank switch>Cycles: Words: 365400H 4040C3H P0:0 P0:1 4561H Bank0: 1123H Bank1: MPYS @P0:1, @P0:0, 259ADDH 4040C3H
register subtracted from accumulator produce difference 4040C3H. bank switch option provides ability multiply @P0:0 @P0:0. default switch shown first example. switch OFF, then @P0:0 placed registers multiplied together. result 259ADD82H. Because most significant bits saved, register contains 259ADDH.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
MPYS
Example: Initialization: MPYS <hwregs>, <regind> P0:0 Bank0: EXT3 Register MPYS EXT3, @P0:0 365400H 4040C3H 4561H 768BH 6DC8DEH F6133DH Cycles: Words:
Instruction: Result
register subtracted from accumulator produce difference F6133DH. instruction places EXT3 Register contents into both register. multiplication results 6DC8DEF2H. Because most significant bits saved, register contains 6DC8DEH. next example illustrates multiplication <hwregs> <regind> operands. Transfer <hwregs> possible hardware registers except read-only register, register accumulator.
Example: Initialization:
Instruction: Result:
MPYS <hwregs> <regind>, <bank switch>Cycles: Words: 365400H 4040C3H P0:0 4561H Bank0: 768BH EXT3 Register MPYS EXT3, @P0:0, 4040C3H 489A70H
register subtracted from accumulator produce difference F6133DH. bank switch option provides ability multiply EXT3 @P0:0 EXT3 EXT3. default switch OFF, shown previous example. switch then EXT3 placed register @P0:0 register. multiplication results 4040C356H. Because most significant bits saved, register contains 4040C3H. Transfer <hwregs> possible hardware registers except read-only register, register accumulator.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: Negate Format: Code Operation: Affected Flags: <cc>,
NEGATE
Condition Code
Modification
-ACC result negative number. special cases are: contains 000000 after execution, then cleared, contains 800000 after execution, then set; cleared.
accumulator replaced with negative current value. achieve this state, two's complement performed.
Example: Initialization: Instruction: Result: Example: Initialization: Instruction: Result:
<cc>, Carry 000111H FFFEEFH 003654H FFC9ACH
Cycles: Words:
Cycles: Words:
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax:
OPERATION
Instruction Format:
Operation: Affected Flags:
None
instruction causes processor continue operation cycle without affecting previous registers I/0.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm> General Instruction Format: Code
BITWISE
%DQN
Destination
Source
Operation: Affected Flags:
.OR. source result accumulator negative. result
accumulator performs instruction contents specified register. upper bits accumulator used this operation. result placed accumulator. instruction frequently used compare specific bits assist program control. NOTE: lower eight bits accumulator unchanged after execution instruction.
Example: Initialization:
<regind> Accumulator P0:0 Bank0: @P0:0 3264A0H 1126H 336600H
Cycles: Words:
Instruction: Result:
instruction reference operand P0:0 with upper bits accumulator. result stored accumulator. 3264A0H 1126A0H 3366A0H.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: A,<memind> P2:11 Bank Address: 5463H @@P2:1 P2:1 Bank0: 3264A0H 5463H 1126H 3366A0H 5464H 0000H Cycles: Words:
Instruction: Result
pointer P2:1 contains register location (A4H). contents this register have address. This address refers data that compared accumulator. 3264A0H.OR.112600H 3366A0H. When memory indirect addressing used, address automatically incremented. This provides convenient method accessing sequential data. ORA,@@P0:0+ performs same operation also increments P0:0 content A5H.
Example: Initialization: Instruction: Result:
<limm> #%1126 3264A0H 3366A0H 0000H
Cycles: Words:
accumulator performs instruction immediate data.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax:
VALUE FROM STACK
<pregs> <dregs> <regind> <hwregs> General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
STACK <destination> Stack Stack None
current value stack copied register specified. Because stack last-in, firstout (LIFO) hard-wired architecture, copy shift remaining data stack performed single cycle. instruction provides ability control information sent stack, making possible expand stack software.
Example: Initialization:
<pregs> Stack Stack P0:0 P0:0 Stack P0:0 0426H 0C06H 0426H
Cycles: Words:
Instruction: Result
destination Stack (item stack) P0:0. 8-LSBs data stack loaded into P0:0. transfer, Stack automatically moved Stack
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <dregs> Stack Stack D0:0 D0:0 Stack D0:0 0426H 0C06H 7676H 0426H 0C06H Cycles: Words:
Instruction: Result:
destination Stack (item stack) given D0:0. Upon transfer, Stack automatically moved Stack
Example: Initialization:
<regind> Stack Stack P0:0 Bank0: @P0:0 Stack Bank0: 0426H 0C06H 42A4H 0426H 0C06H
Cycles: Words:
Instruction: Result
destination Stack (item stack) given P0:0. register location Bank0 which stack item transferred. transfer, Stack automatically moved Stack
Example: Initialization:
<hwregs> Stack Stack Register Stack Register 0426H 0C06H 089CH 0426H 0C06H
Cycles: Words:
Instruction: Result:
destination Stack (item stack) given Register. transfer, Stack automatically moved Stack Transfer <hwregs> possible hardware registers except read-only register.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
PUSH
Syntax:
PUSH VALUE ONTO STACK
PUSH <pregs> PUSH <dregs> PUSH <memind> PUSH <accind> PUSH <regind> PUSH <hwregs> PUSH <direct> PUSH <limm> General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
<source> Stack Stack Stack None
contents specified register placed stack. Because stack last-in, firstout (LIFO) hard-wired architecture, placement shifting current stack data performed single cycle. PUSH instruction provides ability control information sent stack, making possible expand stack software.
Example: Initialization: Instruction: Result
PUSH <pregs> Stack P1:1 PUSH P1:1 Stack Stack 0C06H 0C06H 00A4H
Cycles: Words:
pointer P1:1 contains 8-bit value A4H. 16-bit value, 00A4H, pushed onto stack. transfer, Stack automatically moved Stack
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
PUSH
Example: Initialization: PUSH <dregs> Stack Stack D1:1 PUSH D1:1 Stack Stack 0426H 0C06H 42A4H 0C06H 42A4H Cycles: Words:
Instruction: Result
pointer D1:1 pushed onto stack. transfer, Stack automatically moved Stack
Example: Initialization:
PUSH <memind> Stack Stack Bank0: P1:1 Bank1: Address 5463H PUSH @@P1:1 Stack Stack Bank1: 0426H 0C06H 42A4H 5463H 1126H 0C06H 1126H 5464H
Cycles: Words:
Instruction: Result:
When memory indirect addressing used, address automatically incremented. This provides convenient method accessing sequential data. A,@@P0:0+ performs same operation also increments P0:0 content A5H.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
PUSH
Example: Initialization: PUSH <accind> Stack Stack Accumulator address 42A4H PUSH Stack Stack 0426H 0C06H 42A4H 4C45H 0C06H 4C45H Cycles: Words:
Instruction: Result
Indirect addressing with accumulator points memory (42A4H) data this location pushed onto stack. transfer, Stack automatically moved Stack
Example: Initialization:
PUSH <regind> Stack Stack P1:1 Bank1: PUSH @P1:1 Stack Stack Bank1: 0426H 0C06H 42A4H 0C06H 42A4H 42A4H
Cycles: Words:
Instruction: Result:
pointer P1:1 contains register location (A4H). data this location pushed onto stack. transfer, Stack automatically moved Stack
Example: Initialization:
PUSH <hwregs> Stack Stack Register PUSH Stack Stack 0426H 0C06H 42A4H 0C06H 42A4H
Cycles: Words:
Instruction: Result:
data register pushed onto stack. transfer, Stack automatically moved Stack Transfer from <hwregs> possible from hardware registers.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
PUSH
Example: Initialization: PUSH <direct> Stack Stack Bank0: PUSH Stack Stack 0426H 0C06H 42A4H 0C06H 42A4H Cycles: Words:
Instruction: Result:
direct register address given instruction (24H). value contained this register pushed onto stack (42A4H). transfer, Stack automatically moved Stack
Example: Initialization: Instruction: Result:
PUSH <limm> Stack Stack PUSH #%5757 Stack Stack 0426H 0C06H 0C06H 5757H
Cycles: Words:
immediate operand 5757H pushed onto stack. transfer, Stack automatically moved Stack
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
RETURN FROM SUBROUTINE
Syntax: General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
Stack Stack Stack None
current stack information popped from stack placed Program Counter (PC) register. jump made from subroutine
Example: Initialization:
Stack Stack Stack 0624 0401 06DF 0624 0401H
Cycles: Words:
Instruction: Result:
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax: <cc>,A Accumulator Modification Format: Code Operation: Affected Flags:
ROTATE LEFT
Condition Code
Modification
result accumulator negative result zero. before rotate.
upper bits accumulator rotated left through carry bit. lower bits remain unchanged while resultant LSB, placed with value (see accumulator section).
Example: Initialization: Instruction: Result:
Carry Carry 226A84H 44D584H
Cycles: Words:
upper bits (226AH) shifted left through carry produce 44D5H. lower bits (84H) remain unchanged.
Example: Initialization: Instruction: Result:
<cc>, Carry 226A84H 226A84H
Cycles: Words:
condition code set; therefore, instruction executed.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: <cc>, Accumulator Modification Format: Code Operation: Affected Flags:
ROTATE RIGHT
Condition Code
Modification
=>23 discarded result accumulator negative. result before rotate.
upper bits rotated right through carry bit. lower bits also obtains data shifted from upper bits. lower bits shifted right with being discarded.
Example Initialization: Instruction: Result:
Carry 226A84H 113542H
Cycles: Words:
upper bits (226AH) shifted right through carry produce 1135H. lower bits (84H) shifted right provide 42H.
Example: Initialization: Instruction: Result:
<cc>, Carry 226A84H 226A84H
Cycles: Words:
condition code set; therefore, instruction executed.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax: Flag Modification Format: Code Operation: Affected Flags: Carry
CARRY FLAG
Condition Code
Flag Modification
Carry Flag instruction places carry (bit Status Register).
Example: Initialization: Instruction: Result:
2000H 3000H
Cycles: Words:
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
SIEF
Syntax: SIEF Format: Code Operation: Affected Flags: SIEF
INTERRUPT ENABLE FLAG
Condition Code
Flag Modification
None
instruction places status register used enable interrupts.
Example: Initialization: Instruction: Result:
SIEF SIEF 3000H 3080H
Cycles: Words:
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
SHIFT LEFT LOGICAL
Syntax:
<cc>, Accumulator Modification Format: Code Operation: Affected Flags:
Condition Code
Modification
discarded result accumulator negative (bit to1). result before shift.
bits accumulator shifted left through carry bit. MSB, passes through carry before being discarded. LSB, filled with zero. Subsequent shifts result additional zeroes shifted
Example: Initialization: Instruction: Result:
Carry 226A84H 226A84H
Cycles: Words:
bits accumulator shifted left through carry bit, producing result 44D508H.
Example: Initialization: Instruction: Result:
<cc>, Carry 226A84H 226A84H
Cycles: Words:
condition code set, instruction executed.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
SOPF
OVERFLOW PROTECTION FLAG
SOPF Syntax: Flag Modification Format: Code Operation: Affected Flags: None
Condition Code
Flag Modification
Overflow Protection Flag instruction places status register. operation exceeds limits processor, overflow protection sets overflow flag (OV) hold limit value accumulator.
Example: Initialization: Instruction: Result:
SOPF SOPF 0000H 0100H
Cycles: Words:
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Syntax:
SHIFT RIGHT ARITHMETIC
<cc>, Accumulator Modification Format: Code Operation: Affected Flags:
Condition Code
Modification
discarded result accumulator negative. result before shift.
bits accumulator shifted right with sign extension through carry bit. MSB, replicated into vacated bits. LSB, passed through carry before being discarded.
Example: Initialization: Instruction: Result:
Carry Carry 226A84H 113542H
Cycles: Words:
bits accumulator shifted right. MSB, copied into LSB, discarded.
Example: Initialization: Instruction: Result:
<cc>, 226A84H 113542H
Cycles: Words:
Carry Carry
condition code set; therefore, instruction executed. initialization accumulator sets (NN) condition code. 16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax: <regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm> General Instruction Format: Code
SUBTRACT
%DQN
Destination
Source
Operation: Affected Flags:
(Source) carry from most significant performed. result accumulator negative. result addition exceeds upper (7FFFFFH) lower (800000H) limit accumulator.
addressed data memory operand subtracted from accumulator. result loaded into accumulator. NOTE: lower eight bits accumulator cleared execution subtract instruction.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <regind> Accumulator Bank1: @P0:1 @P0:1 874600H 1234H 751200H 1234H Cycles: Words:
Instruction: Result:
contents register pointed P0:1 subtracted from accumulator. difference contained accumulator pointer left unchanged. register pointer contains 45H. Because pointer references Bank1, absolute register 145H (325). Therefore, contents register 145H subtracted from accumulator. 874600H 123400H 751200H. direct addressing equivalent would A,%145 A,325.
Example: Initialization:
<memind> Accumulator P0:0 Bank0: Address: 247AH @@P0:0+ P0:0 Bank0: 874600H 247AH 1234H 751200H 247BH
Cycles: Words:
Instruction: Result:
pointer used memory indirect addressing. pointer contains address (address 247AH). contains address requested data (data 247AH). This operand subtracted from accumulator. 874600H 123400H 751200H.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: Instruction: Result: <limm> Accumulator #%1234 Accumulator 874600H 751200H Cycles: Words:
immediate operand 8746H subtracted from accumulator. 874600H 123400H 751200H.
Example: Initialization: Instruction: Result:
<hwregs> Accumulator Register 874600H 1234H 751200H
Cycles: Words:
contents Register subtracted from accumulator. 874600H 123400H 751200H. Transfer from <hwregs> possible from hardware registers,
Example: Initialization: Instruction: Result:
<direct> Accumulator Bank0: 874600H 1234H 751200H
Cycles: Words:
contents register subtracted from accumulator. 874600H 123400H 751200H. equivalent instruction (F3H decimal).
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: Instruction: Result: <dregs> Accumulator D0:1 D0:1 874600H 1234H 751200H 1234H Cycles: Words:
contents data pointer D0:1 subtracted from accumulator. difference contained accumulator pointer left unchanged.
Example: Initialization: Instruction: Result:
<pregs> Accumulator P0:0 P0:0 Accumulator 874600H 86F000H
Cycles: Words:
contents pointer register P0:0 subtracted from accumulator. 874600H 005600H 86F000H. Pointer Register connected lower bits D-bus. D-bus connected upper bits P-bus. This causes pointer register operand become 005600H before being subtracted from accumulator.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Syntax:
BITWISE EXCLUSIVE
<regind> <memind> <limm> <hwregs> <direct> <pregs> <dregs> <simm> General Instruction Format: Code %DQN
Destination
Source
Operation: Affected Flags:
A.XOR.<operand> carry from most significant performed. result accumulator negative. result operation exceeds upper (7FFFFFH) lower (800000H) limit accumulator.
With accumulator, perform instruction addressed data memory operand. result loads into accumulator. NOTE: lower eight bits accumulator cleared execution instruction.
16&52
=L/2*
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
Example: Initialization: <regind> Accumulator P0:0 Bank0: @P0:0 005600H 1234H 126200H Cycles: Words:
Instruction: Result:
pointer used memory indirect addressing. pointer contains address (address 00H). Location operand 1234H. With accumulator, 005600H, perform instruction obtain result 126200H.
Example: Initialization:
<memind> Bank1: Address: 5463H @@P2:1 P2:1 Bank1: 3264A0H 5463H 1126H 2342A0H A41H 5464H 0000H
Cycles: Words:
Instruction: Result
pointer P2:1 contains register location(A4H). contents this register have address. This address refers data that compared accumulator. 3264A0H.XOR.112600H 2342A0H. When indirect memory addressing used, address automatically incremented. This provides convenient method accessing sequential data. @@P2:1+ performs same operation also increments content A5H.
16&52
#RRNKECVKQP +PUVTWEVKQPU +PUVTWEVKQP
=L/2*
Example: Initialization: Instruction: Result: <limm> Cycles: Words:
3264A0H #%1126 2342A0H 0000H Perform instruction immediate data. <hwreg> 3264A0H 0000H 1126H 2342A0H 0000H Cycles: Words:
Example: Initialization:
Instruction: Result:
With accumulator, perform instruction <hwreg> operand.
Example: Initialization: Instruction: Result:
<direct> Accumulator Bank0: 3264A0H 1126H 2342A0H 0000H
Cycles: Words:
Register compared accumulator. 3264A0H.XOR.112600H 2342A0H. equivalent instruction (F3H decimal).
16&52

Z89C00 instruction set, consisting basic instructions, optimized high

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