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©2000 ZiLOG, Inc. rights reserved. Information this publication concerning devices, applications, technology described intended suggest possible uses superseded. ZiLOG, INC. DOES ASSUME LIABILITY PROVIDE REPRESENTATION ACCURACY INFORMATION, DEVICES, TECHNOLOGY DESCRIBED THIS DOCUMENT. ZiLOG ALSO DOES ASSUME LIABILITY INTELLECTUAL PROPERTY INFRINGEMENT RELATED MANNER INFORMATION, DEVICES, TECHNOLOGY DESCRIBED HEREIN OTHERWISE. Except with express written approval ZiLOG, information, devices, technology critical components life support systems authorized. licenses conveyed, implicitly otherwise, this document under intellectual property rights.
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Z86D99 low-voltage general-purpose one-time programmable (OTP) microcontroller with integrated four-channel 8-bit sigma delta analog-todigital converter. Z86L99 read-only memory (ROM) version this controller. Z86D99 designed used wide variety embedded control applications including battery chargers, home appliances, infrared (IR) remote controls, security systems, wireless keyboards. three counter/timers, general-purpose 8-bit counter/timer with 6-bit prescaler 8-bit/16-bit counter/timer pair that used individually general-purpose timing pair automate generation reception complex pulses signals. Unique features Z86D99 family products include bytes general-purpose random-access memory (RAM), bytes which mapped into program memory space used store data variables executable RAM, low-battery detection flag, controlled current output pin, which regulated current source that sinks predefined current (I77I). Figure highlights basic product features Z86D99 family.
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microcontroller core offers more flexibility performance than accumulator-based microcontrollers. general-purpose registers, including dedicated input/output (I/O) port registers, used accumulators. This unique register-to-register architecture avoids accumulator bottlenecks high code efficiency. registers used address pointers indirect addressing, index registers, implementing on-chip stack. sophisticated interrupt structure automatically saves program counter status flags stack fast context-switching. Speed execution smooth programming also supported "working register area" with short 4-bit register addresses.
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instruction set, consisting basic instructions, optimized highcode density reduced execution time. similar form ZiLOG instruction set. eight instruction types addressing modes together with ability operate bits, 4-bit nibbles binary coded decimal (BCD) digits, 8-bit bytes, 16-bit words, make code-efficient, flexible microcontroller. Operating with 8-MHz clock source (internal 4-MHz clock rate*), executes most instructions microseconds machine cycles). longest instruction takes microseconds machine cycles). *Most microcontrollers automatically divide external clock determine internal clock rate. Z86D99 allows user select divideby-one option that internal system clock equals external clock frequency.
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Four-channel, 8-bit sigma delta analog-to-digital (A/D) converter with external voltage references (not available 28-pin configuration) independent analog comparators Controlled current output (100 bytes bytes general-purpose register-based bytes mapped into program memory space that used data executable Kbytes memory (Z86D99x) Kbytes (Z86L99x)
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Special architecture automate generation reception complex pulses signals: Programmable 8-bit counter/timer (T8) with 8-bit capture registers 8-bit load registers Programmable 16-bit counter/timer (T16) with 16-bit capture register pair 16-bit load register pair Programmable input glitch filter pulse reception general-purpose 8-bit counter/timer (T1) with 6-bit prescaler
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Thirty-two I/Os, twenty-nine which bidirectional I/Os with programmable resistive pull-up transistors I/Os available 28-pin configuration) Sixteen I/Os selectable stop-mode recovery sources interrupt vectors with nine interrupt sources Three external sources comparator interrupts Three timer interrupts low-battery detector flag
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8-MHz operation operating voltage power consumption typical) with three standby modes: Stop maximum) Halt (0.8 typical)
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Voltage Standby
Low-battery detection flag Low-voltage protection circuit (also known V6I, voltage brown-out, circuit) Watch-dog timer power-on reset circuits
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Clock source-RC/other (LC, resonator, crystal) Watch-dog timer permanently enable 32-kHz crystal Port 20-27 pull-up resistive transistor Port 40-42 pull-up resistive transistor Port 44-47 pull-up resistive transistor Port 50-51 pull-up resistive transistor Port 54-57 pull-up resistive transistor Port 60-63 pull-up resistive transistor Port 64-67 pull-up resistive transistor
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Register File 8-bit Expanded Register File
Port Program Memory Bytes CIN2 CREF2 COUT2 Analog Comparators CIN1 CREF1 COUT1 Port 8-Bit (Carrier) 16-Bit (Modulation) 8-Bit (General) ADC0/P44 ADC1/P45 ADC2/P46 ADC3/P47 Controlled Current Output Power VDD, AVDD VSS, AVSS
Core
Port
Machine Timing Instruction Control
XTAL XTAL
Port *Controlled Current Output (100
8-Bit VRef VRef
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architecture characterized flexible scheme, efficient register address space structure number ancillary features cost-sensitive, high-volume embedded control applications. ROM-based products geared high-volume production (where software stable) one-time programmable equivalents prototyping well volume production where time market code flexibility critical.
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register-oriented architecture centers around internal register file composed consecutive bytes, known standard register file. standard register file consists port registers (R2, R6), control status registers, general-purpose registers, registers reserved future expansion. addition standard register file, Z86D99 uses control status registers located expanded register file. general-purpose register used accumulator address pointer index, data, stack register. active registers referenced modified instruction that accesses 8-bit register, without requirement special instructions. Registers accessed bits treated even-odd register pairs. this case, data's most significant byte (MSB) stored even-numbered register, while least significant byte (LSB) goes into next higher odd-numbered register. instruction designed large register file. instruction provides full compliment 8-bit arithmetic logical operations. operations supported using decimal adjustment binary values, 16-bit quantities addresses counters incremented decremented. manipulation Rotate Shift instructions complete data-manipulation capabilities CPU. special instructions necessary because mapped into register file.
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standard control registers govern operation CPU. instruction which references register file access these control registers. following available control registers: Register Pointer (RP) Stack Pointer (SP) Program Control Flags (FLAGS) Interrupt Control (IPR, IMR, IRQ) Stop Mode Recovery (SMR, P2SMR, P5SMR) Low-Battery Detect (LB) Flag
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uses 16-bit Program Counter (PC) determine sequence current program instructions. addressable register. Peripheral registers used transfer data, configure operating mode, control operation on-chip peripherals. instruction that references register file access peripheral registers. following peripheral control registers: Analog/Digital Converter (ADCCTRL ADCDATA) Timer/Counter (TMR, PRE1) Timer/Counter (CTR0, HI8, LO8, TC8H, TC8L) Timer/Counter (CTR2, HI16, LO16, TC16H, TC16L) T8/T16 Control Registers (CTR1and CTR3) addition, four port registers considered peripheral registers. following port control registers: Port Configuration Registers (P456CON P3M) Port Control Mode Registers P2M) Port Control Mode Registers P4M) Port Control Mode Registers P5M) Port Control Mode Registers P6M) functions applications control peripheral registers explained "Control Status Registers" page
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There four basic address spaces available support wide range configurations: Program memory (on-chip) Standard register file Expanded register file Executable standard register file totals consecutive bytes organized groups eight-bit registers. These registers consist port registers, general-purpose registers, control status registers. Every register acts like accumulator, speeding instruction execution maximizing coding efficiency. Working register groups allow fast context switching. standard register file (known Bank been expanded form expanded register file (ERF) banks. expanded register file allows additional system control registers mapping additional peripheral devices into register area. Each bank potentially consist registers (the same amount standard register file) that then divided
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into working register groups. Currently, only Group Banks (0FH 0DH) been implemented. addition standard program memory register files, Z86D99 also bytes executable that been mapped into upper bytes program memory address space (FF00H-FFFFH). Data written executable using instruction.
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first bytes program memory reserved interrupt vectors. These locations contain 16-bit vectors that correspond available interrupts (IRQ0 through IRQ5.) Address (0CH) 32,767 (7FFFH) consists onchip one-time programmable memory. After reset operation (power-on reset, watch-dog timer time out, stop mode recovery), program execution resumes with initial instruction fetch from location 000CH. After reset, first routine executed must that initializes control registers required system configuration. unique feature Z86D99 family presence bytes on-chip executable RAM. This random-access memory addition standard register file memory available microcontrollers. illustrated Figure executable mapped into upper bytes program memory address space (FF00H-FFFFH). Data written executable using instruction. Memory locations between 8000H FEFFH have been implemented this microcontroller. Z86D99 family does have capability accessing external memory.
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Bank expanded register file architecture known standard register file shown Figure standard register file consists groups sixteen 8-bit registers known Working Register (WR) groups. Working Register Group contains various control status registers. lower half Working Register Group consists port registers R7), upper eight registers available general-purpose registers. Working Register Group through Group standard register file available used general-purpose registers. user bytes general-purpose registers standard register file (Bank
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addition Standard Register File (Bank Expanded Register File Banks Working Register Group have been implemented Z86D99. Figure illustrates Expanded Register File architecture. These expanded register file banks Working Register Group provide total additional control status registers. Z86D99 implemented available registers.
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derives timing from on-board clock circuitry connected pins XTAL1 XTAL2. clock circuitry consists oscillator, divide-by-two shaping circuit, clock buffer. oscillator's input XTAL1, oscillator's output XTAL2. clock driven crystal, ceramic resonator, clock, external clock source.
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offers software control internal system clock using programming register bits register. This register selects clock divide value determines mode STOP Mode Recovery. default setting external clock divide-by-two. When bits register System Clock (SCLK) Timer Clock (TCLK) equal external clock frequency divided two. When register then SCLK TCLK equal external clock frequency. Refer Table page maximum clock frequency. divide-by-16 prescaler SCLK TCLK allows user selectively reduce device power consumption during normal processor execution (under SCLK control) and/or HALT mode, where TCLK sources counter/timers interrupt logic. Combining divide-by-2 circuitry with divide-by-16 prescaler allows external clock divided
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Z6D99 allows different interrupts, three external three internal, from nine possible sources. interrupts assigned follows: Three edge triggered external interrupts (P51, P52, P53), which shared with analog comparators internal interrupt assigned Timer internal interrupt assigned Timer internal interrupt shared between Low-Battery Detect flag Timer Table presents interrupt types, interrupt sources, location specific interrupt vectors.
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'ZVGTPCN KPVGTTWRV
VTKIIGTGF GKVJGT TKUKPI HCNNKPI GFIG KPVGTPCN KPVGTTWRV IGPGTCVGF %QORCTCVQT OCRRGF KPVQ
'ZVGTPCN KPVGTTWRV
VTKIIGTGF HCNNKPI GFIG
%QORCTCVQT 'ZVGTPCN KPVGTTWRV
VTKIIGTGF GKVJGT TKUKPI HCNNKPI GFIG KPVGTPCN KPVGTTWRV IGPGTCVGF %QORCTCVQT OCRRGF KPVQ +43! 6KOGT +PVGTPCN KPVGTTWRV +43" 6KOGT +PVGTPCN KPVGTTWRV +43# 6KOGT +PVGTPCN KPVGTTWRV HNCI OWNVKRNGZGF YKVJ 6KOGT 'PFQH %QWPV KPVGTTWRV 016' (CNNKPIGFIG VTKIIGTGF 4KUKPIGFIG VTKIIGTGF
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These interrupts masked their priorities using Interrupt Mask Register (IMR) Interrupt Priority Register (IPR) (see Figure 12.) When more than interrupt pending, priorities resolved priority encoder, controlled IPR.
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+06'447265
Instruction Power-On Reset (POR)
(+)74' +06'44726 $.1%- &+#)4#/
Interrupt Request Register (IRQ, FAH) Reset
Interrupt requests stored Interrupt Request Register (IRQ), which also used polling. When interrupt request granted, enters "interrupt machine cycle" that globally disables other interrupts, saves program counter (the address next instruction executed) status flags, finally branches vector location interrupt granted. only this point that control passes interrupt service routine specific interrupt. interrupts globally disabled resetting master Interrupt Enable (bit IMR) with Disable Interrupts (DI) instruction. Interrupts globally enabled setting same with Enable Interrupts (EI) instruction. Descriptions three interrupt control registers-the Interrupt Request Register, Interrupt Mask Register, Interrupt Priority Register-are provided "Register Summary" page family supports both vectored polled interrupt handling.
'ZVGTPCN +PVGTTWRV 5QWTEGU
External sources involve interrupt request lines P51, P52, (IRQ2, IRQ0, IRQ1, respectively.) IRQ0, IRQ1, IRQ2 generated transition corresponding port pin. shown Figure when appropriate port (P51, P52, P53) transitions, first flip-flop set. next flip-flops synchronize request internal clock delay internal clock periods. output most recent flip-flop (IRQ0, IRQ1, IRQ2) sets corresponding Interrupt Request Register bit.
n=2,3,1
Multiple Input Signal Conditioning Circuitry
m=0,1,2
System Clock (Internal)
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programming bits Interrupt Edge Select function located register, bits configuration these bits resulting interrupt edge shown Table
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(CNNKPI (CNNKPI 4KUKPI 4KUKPI(CNNKPI
(CNNKPI 4KUKPI (CNNKPI 4KUKPI(CNNKPI
016' Although interrupts edge triggered, minimum interrupt request High times must observed proper operation. "Electrical Characteristics" page exact timing requirements (TWIL, TWIH) external interrupt requests.
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Internal sources ORed with external sources, that either internal external source trigger interrupt.
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Figure shows logic diagram Interrupt Request Register. leading edge interrupt request sets first flip-flop. remains until interrupt requests sampled.
IRQ0 Sample Clock From Priority Logic
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Mask Priority Logic
Internal interrupt requests sampled during most recent clock cycle before Code fetch (see Figure 15.) External interrupt requests sampled internal clocks earlier than internal interrupt requests because synchronizing flip-flops shown Figure
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Interrupt Request Sampled Internally External Interrupt Request Sampled
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sample time, interrupt request transferred second flip-flop shown Figure which drives interrupt mask priority logic. When interrupt cycle occurs, this flip-flop reset only highest priority level that enabled. user direct access second flip-flop reading writing IRQ. read specifying source register instruction, written specifying destination register.
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After RESET, interrupts disabled must re-initialized before vectored polled interrupt processing begin. Interrupt Priority Register, Interrupt Mask Register, Interrupt Request Register must initialized, that order, start interrupt process. However, does have initialized polled processing. Interrupts must globally enabled using instruction. Setting sufficient. Subsequent this instruction, interrupts enabled either manipulation instruction, with equivalent effects. Additionally, interrupts must disabled executing instruction before IPRs IMRs modified. Interrupts then enabled executing instruction.
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used generate software interrupts specifying destination instruction referencing Standard Register File. These Software Interrupts (SWIs) controlled same manner hardware-generated requests other words, control priority enabling each level). generate SWI, request follows: ORIRQ, #NUMBER where immediate data, NUMBER, position corresponding appropriate level SWI.
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example, IRQ5, NUMBER would have With this instruction, interrupt system globally enabled, IRQ5 enabled, there higher priority pending requests, control transferred service routine pointed IRQ5 vector.
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system reset overrides other operating conditions puts into known state. control status registers reset their default conditions after power-on reset (POR) Watch-Dog Timer (WDT) time-out while mode. control status registers reset their default conditions after Stop Mode Recovery (SMR) while HALT STOP mode. General-purpose registers undefined after device powered Resetting does affect contents general-purpose registers. registers keep their most recent value after reset, long reset occurs specified operating range. Registers keep their most recent state from reset, drops below Table page 73). Following reset, first routine executed must that initializes control registers required system configuration.
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(cold start) always resets control status registers their default conditions. sets Stop Mode Recovery register indicate that cold start occurred. timer circuit clocked dedicated on-board oscillator used Power-On Reset Timer (TPOR) function. time specified TPOR. TPOR time allows oscillator circuit stabilize before instruction execution begins. delay timer circuit one-shot timer triggered three conditions: Power Fail Power status including recovery from Voltage (VLV) Standby mode STOP-Mode Recovery (when register time-out Under normal operating conditions, stop mode recovery event always triggers delay timer. This delay necessary allow external oscillator time
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stabilize. When using oscillator (with factor), shorter wake-up time means delay eliminated. register selects whether timer delay used after StopMode Recovery bypassed. then timer delay used. then timer delay bypassed. this case, source must held recovery state pass Reset signal internally.
9CVEJ&QI 6KOGT
retriggerable one-shot timer that resets reaches terminal count. When operating modes, reset functionally equivalent hardware reset. mask option permanently enabled watch-dog timer selected, runs when power option selected, initially enabled executing instruction refreshed subsequent executions instruction. instruction does affect Zero (Z), Sign (S), Overflow flags. Permanently enabled WDTs always enabled, instruction used refresh cannot disabled after been initially enabled. during both HALT STOP modes. circuit driven on-board oscillator. time-out period fixed typical value (see Table page 75).
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addition standard mode, supports three power-down modes minimize device current consumption. following three modes supported: HALT STOP Low-Voltage Standby Table shows status internal clock (SCLK), internal Timer clock (TCLK), external oscillator, Watch-Dog Timer during mode three low-power modes.
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order enter HALT STOP mode, necessary first flush instruction pipeline avoid suspending execution mid-instruction. user flush instruction pipeline executing Code FFH) immediately before appropriate sleep instruction. example:
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HALT mode suspends instruction execution turns internal clock (SCLK). on-chip oscillator circuit remains active, internal Timer clock (TCLK) continues applied counter/timers interrupt logic. interrupt request, either internally externally generated, must executed (enabled) exit HALT mode. After interrupt service routine, program continues from instruction immediately following HALT. HALT mode also exited POR. this case, program execution restarts reset address 000CH.
5612
STOP mode provides lowest possible device standby current. This instruction turns both internal clock (SCLK) internal Timer clock (TCLK) reduces standby current less. STOP mode terminated source. Terminating STOP mode causes processor restart application program address 000CH.
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Exiting STOP mode using source greatly simplified Z86D99 family. Z86D99 family products allows individual pins (Ports used stop-mode recovery sources. STOP mode exited when these sources toggled. transition from either high high Port Port identified source will effect SMR.
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There three registers that control STOP mode recovery: Stop Mode Recovery Port Stop Mode Recovery (P2SMR) Port Stop Mode Recovery (P5SMR) functions applications these registers explained "Stop-Mode Recovery Control Registers" page
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on-chip voltage comparator checks that level required level correct operation When falls below low-voltage trip voltage (VLV), reset globally driven, then device low-current standby mode with external oscillator stopped. remains above VRAM, content preserved. When power level rises above level, device performs functions normally. minimum operating voltage varies with temperature operating frequency, while varies with temperature only.
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Z86D99x family lines dedicated input output 40-pin configuration. These lines grouped into four 8-bit ports known Port Port Port Port four ports programmable either inputs outputs with exception P52, P53, P43. input only they used programming. controlled current output therefore output only. ports have push-pull CMOS outputs. addition, push-pull outputs turned open-drain operation using P456CON register. Internal resistive pull-up transistors available user-defined OTP/mask option ports. Ports pull-ups nibble selectable. Port pull-up option applies eight lines.
016' Internal pull-ups disabled given group port pins when those pins programmed outputs.
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Each port associated Mode Register that determines port's functions allows dynamic change port functions during program execution. Port Mode Registers mapped into Standard Register File. Because their close association, Port Mode Registers treated like other general-purpose register. There special instructions port manipulation. instruction that addresses register address ports. Data directly accessed Port Register, with extra moves.
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Each four ports (Ports input register, output register, associated buffer control logic. Because there separate input output registers associated with each port, writing bits defined inputs store data output register. This data cannot read long bits defined inputs. However, bits reconfigured output, data stored output register reflected output pins then read. This mechanism allows user initialize outputs before driving their loads. Because port inputs asynchronous internal clock, READ operation could occur during input transition. this case, logic level might uncertain (somewhere between logic
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eight lines each port configured under software control either input output, independently. Bits programmed outputs globally programmed either push-pull open-drain.
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ports accessed general-purpose registers. Port registers written specifying port register instruction's destination register. Writing port causes data stored output register port, reflected externally configured output. Ports read specifying port register source register instruction. When output read, data external returned. Under normal loading conditions, returning data external equivalent reading output register. However, defined open-drain output, data returned value forced output external system. This value might same data output register. Reading input bits also returns data external pins.
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Special functions Ports defined Table
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Z86D99 includes independent on-chip analog comparators. User's Manual description comparators work.
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Z86D99 family incorporates 8-bit that uses sigma delta architecture (see Figure comprised modulator digital filter. input selected (bit from ADCCTRL) with analog from (P47-P44) pins that configured analog inputs (bit from ADCCTRL).
016' Whenever input analog value, digital input buffer disabled order reduce current through device.
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VRef+ AVDD Analog modulator digital
VRef-
AVSS
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low-pass filter transfer function presented Figure with -3dB frequency given formula:
0.0021
where f587 sampling frequency modulator.
Filter response
Out/In[db]
log10(f)
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sampling frequency modulator f587 selected between fS7FE fS7FE/2 (bit1 from ADCCTRL). Reducing clock frequency lowers power dissipated block. enabled disabled. When enabled, converter tracks input voltage. When switching between channels (step response), required time reach final value given time constant low-pass filter:
delay
When available, reference externally with Vrefp Vqry pins. output code represents following ratio:
Ref+ RefThough functions smaller input voltage range (VRqr-VRqr), noise offsets remain constant over specified electrical range. errors converter increase small input signals. fast access output ADC, current data available result register (r8, bank00). reduce interference between digital part analog part, separate AVSS AV88 pins available packages where used.
016' smaller packages, which support ADC, user must keep converter active order have power dissipated block.
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24'.+/+0#4; <&## Description Signal/noise Power Value <-47
#EVKXG )NKVEJ (KNVGT Z86x99 family incorporates active power/glitch filter
that used improve quality power supply when device operating noisy environments. chips three separate power buses: ring power (all output drivers plus crystal/RC oscillator) called core power (all digital circuitry) called V88e7IR9 analog power (all analog circuitry) called AV88 Depending availability, more power busses connected together. active power filter used packages that have separate. internal schematic presented Figure
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VDD_CORE
power supply
External
chip switch ring core
comp
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When internal power/glitch filter used, both V88e7IR9 must connected together externally power supply. When internal circuitry used, connected power supply connected external energy storage capacitor (1-10 range). core connected only this capacitor during power supply glitches.
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24'.+/+0#4; <&## Parameter Diff. stage gain Diff. stage bandwidth Rise time Fall time pulse pulse Condition
wafer level, three power buses available. Depending number pins package, more power buses connected together. active glitch/power filter effectively increases noise immunity batteryoperated designs where controller driving high current loads LED, keyboard scanning).
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current output controlled current source that controlled output value (see Table 10). cannot configured input, read, always returns state output value sink sink).
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6#$.' %744'06 5+0- 52'%5 24'.+/+0#4; <&## Parameter Rise time Fall time Comparator response Regulated current Internal resistance 0.02 0.54 Conditions load load @27C
driver function modes: controlled current output, when voltage over minimum value
Voutmin
resistive pull down when driver cannot regulate current; this mode, gate NMOS pull down raised power rail. characteristics presented Figure
0.18
0.16
0.14
0.12
0.08
0.06
0.04
0.02
Vpad[V]
(+)74' %*#4#%6'4+56+%5 %744'06 5+0-
reads mode driver reading number from register. This output Set-Reset flip-flop that sets whenever volt-
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lower than reset write respective register.
6KOGT
timer general-purpose 8-bit counter/timer driven 6-bit prescaler PRE1. counter/timer independent processor instruction sequence, which relieves software time-critical operations such interval timing event counting. counter/timer operates either single-pass continuous mode. count, counting either stops, initial value reloaded counting continues. Under software control, values loaded immediately when endof-count reached. Software also controls counting mode, counter/ timer started stopped, uses lines. Both counter prescaler registers altered while counter/timer running. Counter/timer driven timer clock generated dividing internal clock four. During divide-by-four stage, 6-bit prescaler 8-bit counter/ timer form synchronous 16-bit divide chain. Counter/timer also driven external input (TCH) using P51. Port line serve timer output (TIUT) through which internal clock out. timer output toggles count. counter/timer register (F2H) consists 8-bit down-counter, writeonly register that holds initial count value, read-only register that holds current count value. initial value range from decimal (01H, 02H, 00H). Under software control, counter/timer started stopped using Timer Mode Register (TMR,F1H) bits D-D!. counter/timer associated with Load Enable Count bit. After hardware reset, counter/timer disabled, contents counter/timer prescaler register undefined. However, counting modes configured single-pass mode, clock source external.
24'.+/+0#4;
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HI16
LO16
16-Bit Input Glitch Filter SCLK TC16L 8-Bit TC8H TC8L
Timer
Clock Divider Clocked And/Or Logic Timer 8/16
TC16H
Edge Detect Circuit
Timer
SCLK
Clock Divider Clock Divider
(+)74' %1706'46+/'4 #4%*+6'%674' 6KOGT 1RGTCVKQP
timer programmable 8-bit counter/timer with 8-bit capture registers 8-bit load registers. timer programmable 16-bit counter/ timer with 16-bit capture register pair 16-bit load register pair. counters/timers have modes operation: transmit mode used generate complex waveforms. There submodes: normal mode used single-pass modulo-N (repeating) mode. ping-pong mode used when timer counts down, enables timer that counts down, enabling until mode disabled. demodulation mode used capture demodulate complex waveforms.
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6TCPUOKV /QFG Before enabled, output depends CTR1, CTR1, T8_OUT CTR1, T8_OUT
When enabled, output T8_OUT switches initial value (CTR1 D1). initial value (CTR1 TC8L loaded; otherwise, TC8H loaded into counter. single-pass mode (CTR0 D6), counts down stops, T8_OUT toggles, time-out status (CTR0 set, time-out interrupt generated enabled (CTR0 D1). modulo-N mode, upon reaching terminal count, T8_OUT toggled, interrupt generated. Then loads count T8_OUT level TC8L loaded; T8_OUT TC8H loaded. counts down toggles T8_OUT, sets time-out status (CTR0 D5), generates interrupt enabled (CTR0 D1). This completes cycle. then loads from TC8H TC8L, according T8_OUT level, repeats cycle. user modify values TC8H TC8L time.The values take effect when they loaded. write these registers time values loaded into counter/timer. initial count allowed. initial count causes count from used hexadecimal values). Transition from time-out condition (see Figure 21).
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016' same instructions stopping counter/timers setting status bits. successive commands necessary-the first command stopping counter/timers second command resetting status bits-because counter/timer clock interval must complete initiated event actually occur.
&GOQFWNCVKQP /QFG Program TC8L TC8H %FF. After enabled, when first edge (rising, falling, both, depending CTR1 detected, starts count down. When subsequent edge (rising, falling, both, depending CTR1 detected during counting, current value one's complemented into capture registers. positive edge, data placed LO8. negative edge, data placed H18. edge-detect status bits (CTR1 set, interrupt generated enabled (CTR0 D2). Meanwhile, loaded with TC8H starts counting again. reaches time-out status (CTR0 set, interrupt generated enabled (CTR0 D1), continues counting from (see Figure 22).
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(+)74' &'/1&7.#6+10 /1&' (.19%*#46 6TCPUKV /QFG normal ping-pong mode, output T16, when
enabled, dependent CTR1, CTR1, T16_OUT CTR1, T16_OUT user force output either whether enabled not, programming CTR1
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When enabled, TC16H TC16L loaded, T16_OUT switched initial value (CTR1 d0). When counts down T16_OUT toggled normal ping-pong mode), interrupt generated enabled (CTR2 D1), status (CTR2 set. modulo-N mode, loaded with TC16H TC16L, counting continues. user modify values TC16H TC16L time. values take effect when they loaded. load these registers time values loaded into counter/timer. initial count allowed. initial count causes count from %FFFF %FFFE. Transition from %FFFF time-out condition.
&GOQFWNCVKQP /QFG Program TC16L TC16H %FF. After enabled, when first edge (rising, falling, both, depending CTR1 detected, captures HI16 LO16, reloads, begins counting. 2KPI2QPI /QFG This operation mode only valid transmit mode. must programmed single-pass mode (CTR0 CTR2 D6), pingpong mode must programmed CTR1 user begin operation enabling either (CTR0 CTR2 D7). example, enabled, T8_OUT this initial value (CTR1 D1). According T8_OUT's level, TC8H TC8L loaded into After terminal count reached, disabled, enabled. T16_OUT switches initial value (CTR1 D0), data from TC16H TC16L loaded, starts count. After reaches terminal count, stops. enabled again, whole cycle repeats. Interrupts allowed when reaches terminal control (CTR0 CTR2 D1). stop ping-pong operation, write bits CTR1.
016' Enabling ping-pong operation while counters/timers running cause intermittent counter/timer function. Disable counters/timers, then reset status flags before starting ping-pong mode.
24'.+/+0#4;
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Z86D99 family port registers, status control registers, general-purpose registers. port control registers included general-purpose register memory allow instruction process control information directly, thus eliminating requirement special control instructions. instruction permits direct access these registers. addition, each general-purpose registers also function accumulator, address pointer, index register. Registers identified "Reserved" exist have been implemented this design.
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Table through Table summarize name location registers. register-by-register descriptions follow this section.
6#$.' 2146 4')+56'45
)4172 $#0- 4')+56'45 )TR$PM
4GIKUVGT (WPEVKQP )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT )GPGTCN2WTRQUG 4GIKUVGT #PCNQI&KIKVCN %QPXGTVGF &CVC 2QTV %QPVTQN 4GIKUVGT 2QTV %QPVTQN 4GIKUVGT 2QTV %QPVTQN 4GIKUVGT 4GUGTXGF 2QTV %QPVTQN 4GIKUVGT 4GUGTXGF 4GUGTXGF +FGPVKHKGT #&%#
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'4 57//#4;
6#$.' %10641. 56#675 4')+56'45
)4172 $#0- 4')+56'45 )TR$PM
4GIKUVGT (WPEVKQP 5VCEM 2QKPVGT )GPGTCNRWTRQUG 4GIKUVGT 4GIKUVGT 2QKPVGT 2TQITCO %QPVTQN (NCI 4GIKUVGT +PVGTTWRV /CUM 4GIKUVGT +PVGTTWRV 4GSWGUV 4GIKUVGT +PVGTTWRV 2TKQTKV[ 4GIKUVGT 4GUGTXGF 2QTV /QFG 4GIKUVGT 2QTV /QFG 4GIKUVGT 4GUGTXGF 4GUGTXGF 2TGUECNG 4GIKUVGT &CVC 4GIKUVGT /QFG 4GIKUVGT 4GUGTXGF +FGPVKHKGT (NCIU
6#$.' 6+/'4 %10641. 4')+56'45
)4172 $#0- 4')+56'45 )TR$PM
4GIKUVGT (WPEVKQP 4GUGTXGF 4GUGTXGF 4GUGTXGF .QY$CVVGT[ &GVGEV (NCI /5$[VG %CRVWTG 4GIKUVGT .5$[VG %CRVWTG 4GIKUVGT *KIJ %CRVWTG 4GIKUVGT %CRVWTG 4GIKUVGT /5$[VG *QNF 4GIKUVGT .5$[VG *QNF 4GIKUVGT *KIJ *QNF 4GIKUVGT *QNF 4GIKUVGT %QPVTQN 4GIKUVGT %QPVTQN 4GIKUVGT %QPVTQN 4GIKUVGT %QPVTQN 4GIKUVGT +FGPVKHKGT
24'.+/+0#4;
25+44
4')+56'4 '4414 %10&+6+105
%10641. 56#675 4')+56'45
6#$.' 2146 /1&' 4')+56'45
)4172 $#0- 4')+56'45 )TR$PM
4GIKUVGT (WPEVKQP 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 5VQR /QFG 4GEQXGT[ 4GIKUVGT 4GUGTXGF 4GUGTXGF %QPVTQN 4GIKUVGT 4GUGTXGF 2QTV /QFG 2QTV 5VQR /QFG 4GEQXGT[ 2QTV /QFG 4GIKUVGT 4GUGTXGF 2QTV /QFG 4GIKUVGT 2QTV 5VQR /QFG 4GEQXGT[ 2QTV %QPHKIWTCVKQP 4GIKUVGT +FGPVKHKGT
#&%%64. 25/4 25/4 2%10
4')+56'4 '4414 %10&+6+105
Registers Standard Register File must used correctly because certain conditions produce inconsistent results must avoided. Registers F5H-F9H write-only registers. attempt made read these registers, returned. Reading write-only register returns FFH. When Register Pointer (register FDH) read, least significant four bits (lower nibble) indicate current Expanded Register File Bank. (For example, 0000 indicates Standard Register File, while 1010 indicates Expanded Register File Bank Writing bits that selected timer outputs changes register effect signal. instruction DJNZ uses general-purpose working register counter. Logical instructions such require that current contents operand read. They therefore function properly write-only registers.
4')+56'45
)4172'& (70%6+10
following summary special-purpose registers Z86D99 family grouped function. following functional groups: Flags Pointers Analog-to-Digital Converter Control Interrupt Control
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
Port Control Timer Control -General-Purpose Timer (T1) Timer Control Timers Stop-Mode Recovery Control registers described this section, bits identified "Reserved" either exist (meaning they have been implemented this design) have special purpose ZiLOG engineering test environment. attempt these bits results unpredictable meaningless.
6#$.' 4')+56'4 &'5%4+26+10 .1%#6+105 #FFTGUU )TR$PM 4GIKUVGT 4GIKUVGT (WPEVKQP 2QTV &CVC 2QTV &CVC 2QTV &CVC 2QTV &CVC &CVC 6KOGT %QPVTQN %QPVTQN
6KOGT %QPVTQN %QPVTQN
.QCF *KIJ .QCF .QCF *KIJ .QCF %CRVWTG *KIJ %CRVWTG %CRVWTG *KIJ %CRVWTG $CVVGT[ &GVGEV 2QTV 5QWTEG 2QTV /QFG 2QTV /QFG 2QTV 5QWTEG 2QTV /QFG %QPVTQN 5VQR /QFG 4GEQXGT[ 6KOGT /QFG 6KOGT &CVC 6KOGT 2TGUECNG 5[ODQN #&%# 25/4 25/4 #&%%64. .QECVKQP RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG
2QTV %QPHKIWTCVKQP
2%10
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4 &'5%4+26+10 .1%#6+105
%106+07'& #FFTGUU )TR$PM 4GIKUVGT 4GIKUVGT (WPEVKQP 2QTV /QFG 2QTV %QPHKIWTCVKQP
+PVGTTWRV 2TKQTKV[ +PVGTTWRV 4GSWGUV +PVGTTWRV /CUM 4GIKUVGT 2QKPVGT 5VCEM 2QKPVGT 5[ODQN .QECVKQP RCIG RCIG RCIG RCIG RCIG RCIG RCIG RCIG
2TQITCO %QPVTQN (NCIU (NCIU
016' 6JKU TGIKUVGT 4'5'6 HQNNQYKPI 5VQR /QFG 4GEQXGT[
6JKU 4'5'6 CHVGT
(NCIU 2QKPVGT 4GIKUVGTU
addition three standard flag pointer registers (Program Control Register Pointer, Stack Pointer), Z86D99 family includes Low-Battery Detect Flag register.
2TQITCO %QPVTQN (NCI 4GIKUVGT
(NCIU Program Control Flag register reflects current status shown Table FLAGS register contains bits status information that cleared operations. Four bits tested with conditional jump instructions. flags cannot tested used arithmetic. remaining flags register available user, they must cleared instructions usable with conditional jumps.
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' (.#)5 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA
)4172$#0- 4')+56'4
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF %CTT[ (NCI
8CNWG &GUETKRVKQP +PFKECVGU ECTT[ RQUKVKQP TGIKUVGT DGKPI WUGF CEEWOWNCVQT 4QVCVG 5JKHV KPUVTWEVKQPU VJKU EQPVCKPU OQUV TGEGPV XCNWG UJKHVGF URGEKHKGF TGIKUVGT +PFKECVGU VJCV EQPVGPVU CEEWOWNCVQT TGIKUVGT \GTQ HQNNQYKPI CTKVJOGVKE NQIKECN QRGTCVKQP 5VQTGU XCNWG OQUV UKIPKHKECPV TGUWNV HQNNQYKPI CTKVJOGVKE NQIKECN 4QVCVG 5JKHV QRGTCVKQP CTKVJOGVKE QRGTCVKQPU UKIPGF PWODGTU RQUKVKXG PWODGT KFGPVKHKGF PGICVKXG PWODGT KFGPVKHKGF UKIPGF CTKVJOGVKE 4QVCVG 5JKHV QRGTCVKQPU HNCI YJGP TGUWNV ITGCVGT VJCP OCZKOWO RQUUKDNG PWODGT
NGUU VJCP OKPKOWO RQUUKDNG PWODGT
VJCV TGRTGUGPVGF EQORNGOGPV HQTO HQNNQYKPI NQIKECN QRGTCVKQPU VJKU HNCI 7UGF CTKVJOGVKE CHVGT UWDVTCEVKQP HNCI HQNNQYKPI CFFKVKQP ENGCTGF YJGPGXGT CFFKVKQP IGPGTCVGU ECTT[ RQUKVKQP
QXGTHNQY CEEWOWNCVQT UWDVTCEVKQP IGPGTCVGU DQTTQY KPVQ 7UGT FGHKPCDNG
AAAAAAA
<GTQ (NCI
AAAAAAA
5KIP (NCI
AAAAAAA
1XGTHNQY (NCI
AAAAAAA
&GEKOCN #FLWUV (NCI
AAAAAAA
*CNH %CTT[ (NCI
AAAAAAA
7UGT (NCI
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' (.#)5 4')+56'4 AAAAAAA 7UGT (NCI
)4172$#0- 4')+56'4
7UGT FGHKPCDNG
4GIKUVGT 2QKPVGT
instructions access registers directly indirectly
using either 4-bit 8-bit address field. upper nibble Register Pointer, Table contains base address active Working Register GROUP. lower nibble contains base address Expanded Register File BANK. When using 4-bit addressing, 4-bit address working register combined with upper nibble Register Pointer (identifying GROUP), thus forming 8-bit actual address.
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAA )4172$#0- 4')+56'4
9QTMKPI 4GIKUVGT )TQWR
'ZRCPFGF 4GIKUVGT (KNG $CPM
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 9QTMKPI 4GIKUVGT )TQWR 2QKPVGT 'ZRCPFGF 4GIKUVGT (KNG $CPM 2QKPVGT 8CNWG &GUETKRVKQP +FGPVKHKGU RQUUKDNG )TQWRU GCEJ EQPVCKPKPI 9QTMKPI 4GIKUVGTU +FGPVKHKGU RQUUKDNG $CPMU QPN[ $CPMU XCNKF HCOKN[
AAAAA
5VCEM 2QKPVGT
Z86D99 family products configured internal stack. size stack limited only available memory space general-purpose registers dedicated this task. 8-bit stack pointer, Table used stack operations.
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
5VCEM 2QKPVGT
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 5VCEM 2QKPVGT 8CNWG &GUETKRVKQP 2QKPVU FCVC UVQTGF UVCEM QXGTHNQY WPFGTHNQY QEEWT UVCEM CFFTGUU KPETGOGPVGF FGETGOGPVGF FWTKPI PQTOCN UVCEM QRGTCVKQPU
.QY$CVVGT[ &GVGEV (NCI
When Z86D99 used battery-operated
application, on-chip comparators used check that required level correct operation device. When voltage begins approach point, on-chip low-battery detection circuit tripped, which turn sets user-readable flag. low-voltage detection level (VLB) 0.4V. register, Table used reset flag.
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA 4GUGTXGF )4172$#0- 4')+56'4 .8&A (NCI .8&A 'PCDNG
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 4GUGTXGF 8CNWG &GUETKRVKQP #NYC[U TGCFU 11111 'HHGEV XQNVCIG FWTKPI 6TCPUOKV /QFG TGIWNCVKPI EWTTGPV 4GUGV HNCI (NCI (NCI 4GUGV 'HHGEV 'PCDNG &KUCDNG
AAAAAAA
.8&A(NCI
AAAAAAA
.8&A'PCDNG
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
#PCNQIVQ&KIKVCN %QPXGTVGT %QPVTQN 4GIKUVGTU
Z86D99 family features 8-bit analog-to-digital converter with external voltage references. output stored Data Register, shown Table configured using Control Register, shown Table
6#$.' #&%%64. 4')+56'4 )4172$#0- 4')+56'4 %JCPPGN 5GNGEVKQP
$KV(KGNF 4GUGV 2QUKVKQP AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAA
%NQEM 5GNGEV
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2A#& 2A#& 2A#& 2A#& %JCPPGN 5GNGEVKQP 8CNWG &GUETKRVKQP EQPHKIWTGF +PRWV EQPHKIWTGF FKIKVCN KPRWV EQPHKIWTGF +PRWV EQPHKIWTGF FKIKVCN KPRWV EQPHKIWTGF +PRWV EQPHKIWTGF FKIKVCN KPRWV EQPHKIWTGF +PRWV EQPHKIWTGF FKIKVCN KPRWV %JCPPGN %JCPPGN %JCPPGN %JCPPGN 5%.-
AAAAAAA AAAAAAA
#&A2QYGT10 %NQEM 5GNGEV
%QPVTQN 4GIKUVGT
#&%%64. ADCCTRL register controls operation analog-to-digital converter. Bits ADCCTRL register determine which four analog input channels feeds into given time. Bits through enable disable digital input buffer. When configured input channel, port configured Input Mode with digital input buffer disabled. &CVC 4GIKUVGT
#&%# ADCDATA register read-only register
that contains digital output analog-to-digital converter. Table
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' #&%# 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4 &CVC
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF &CVC 8CNWG &CVC &GUETKRVKQP 1WVRWV 'HHGEV
+PVGTTWRV %QPVTQN 4GIKUVGTU
allows different interrupts from variety sources. These interrupts masked their priorities using Interrupt Mask Register Interrupt Priority Register. Interrupt Request Register stores interrupt requests both vectored polled interrupts.
+PVGTTWRV /CUM 4GIKUVGT IMR, Table individually globally enables interrupt requests. master enable must before individual interrupt requests recognized. must reset enable interrupts disable interrupts instructions only. automatically reset during interrupt service routine following execution Interrupt Return (IRET) instruction.
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
)4172$#0- 4')+56'4
/CUVGT UGTXGF
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF /CUVGT 4GUGTXGF +43# +43" +43! 8CNWG &GUETKRVKQP 'PCDNG /CUVGT +PVGTTWRV &KUCDNG /CUVGT +PVGTTWRV #NYC[U TGCFU 'HHGEV 'PCDNG +43# &KUCDNG +43# 'PCDNG +43" &KUCDNG +43" 'PCDNG +43! &KUCDNG +43! 'PCDNG &KUCDNG 'PCDNG &KUCDNG 'PCDNG &KUCDNG
016' must reset instruction before contents Interrupt Mask Register Interrupt Priority Register changed except following situations:
Immediately after hardware reset Immediately after executing interrupt service routine before been instruction
+PVGTTWRV 2TKQTKV[ 4GIKUVGT
IPR, Table write-only register that
sets priorities vectored interrupts order resolve simultaneous interrupt requests. There sequence possibilities interrupts. interrupts, IRQ0 IRQ5, divided into three groups interrupt requests each, follows: Group consists IRQ3 IRQ5 Group consists IRQ0 IRQ2 Group consists IRQ1 IRQ4
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' $KV(KGNF 4GUGV 2QUKVKQP AAAAAA AAAAAAA AAAAA 4GUGTXGF +43A
)4172$#0- 4')+56'4 +PVA)TQWR +PVA )TQWR
+43A +43A
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 4GUGTXGF 2TKQTKV[ +43! +43# +PVGTTWRV )TQWR 2TKQTKV[ 8CNWG &GUETKRVKQP 'HHGEV +43! +43# +43#
)TQWR +43!
4GUGTXGF 4GUGTXGF +43"
)TQWR
)TQWR +43"
AAAAAAA AAAAAAA
2TKQTKV[ 2TKQTKV[ +43"
Priorities both within between groups using IPR. Bits define priority individual members within groups. Bits encoded define priority orders between three groups. Bits reserved.
+PVGTTWRV 4GSWGUV 4GIKUVGT IRQ, Table read/write register that stores interrupt requests both vectored polled interrupts. When interrupt request made interrupts, corresponding
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' $KV(KGNF 4GUGV 2QUKVKQP AAAAAA
)4172$#0- 4')+56'4
+PVGTTWRV 'FIG
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF +PVGTTWRV 'FIG 6TKIIGT 8CNWG &GUETKRVKQP 4KUG(CNNKPI 4KUKPI (CNNKPI (CNNKPI 4KUG(CNNKPI (CNNKPI 4KUKPI (CNNKPI
AAAAAAA
+43#
+43# +PCEVKXG +43# #EVKXG +43# 4GUGV +43# +43" +PCEVKXG +43" #EVKXG +43" 4GUGV +43" +43! +PCEVKXG +43! #EVKXG +43! 4GUGV +43! +PCEVKXG #EVKXG 4GUGV +PCEVKXG #EVKXG 4GUGV +PCEVKXG #EVKXG 4GUGV
AAAAAAA
+43"
AAAAAAA
+43!
AAAAAAA
AAAAAAA
AAAAAAA
Whenever power-on reset executed, reset disabled. Before accepts requests, must enabled executing enable interrupts instruction.
016' always cleared read-only mode until first instruction that enables read/write. Setting Global Interrupt Enable Interrupt Mask Register (IMR does enable IRQ. Execution instruction required.
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
polled processing, must initialized instruction. properly initialize IRQ, following code provided: make sure vectored interrupts disabled enable IRQ, otherwise read only necessary, interrupts were previously enabled disable interrupt handling
cleared before enabling sequence ensure unexpected interrupts occur when executed. This code sequence must executed before programming application required values IMR.
2QTV %QPVTQN 4GIKUVGTU
Each four ports (Ports input register, output register, associated buffer control logic. $GECWUG there separate input output registers associated with each port, writing bits defined inputs stores data output register. This data cannot read long bits defined inputs. However, bits reconfigured output, data stored output register reflected output pins then read. This mechanism allows user initialize outputs before driving their loads.
2QTV %QPHKIWTCVKQP 4GIKUVGTU
2%10 port configuration register (described Table switches comparator inputs from digital analog allows Ports and/or switched from push/pull active outputs open drain outputs. ZiLOG Test Mode, this register used enable Address Strobe/Data Strobe. available User Mode.
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 2%10 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAA 7UGF /QFG
)4172$#0- 4')+56'4 4GUGTX 1WVRWV 1WVRWV 1WVRWV
/QFG
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 7UGF 8CNWG &GUETKRVKQP 6JGUG DKVU GZKUV JCXG HWPEVKQP CUUKIPGF VJGO VJG[ TGUGTXGF HWVWTG GZVGPUKQPU OWUV WUGF #PCNQI
+PRWVU &KIKVCN KPRWVU #PCNQI EQORCTCVQT KPRWVU
EQPHKIWTGF +PRWVU &KIKVCN KPRWVU 2WUJ2WNN #EVKXG 1RGP &TCKP 1WVRWVU 2WUJ2WNN #EVKXG 1RGP &TCKP 1WVRWVU 2WUJ2WNN #EVKXG 1RGP &TCKP 1WVRWVU
AAAAAAA AAAAAAA
%QORCTCVQT /QFG %QORCTCVQT /QFG 4GUGTXGF 2QTV 1WVRWV %QPHKIWTCVKQP 2QTV 1WVRWV %QPHKIWTCVKQP 2QTV 1WVRWV %QPHKIWTCVKQP
AAAAAAA AAAAAAA AAAAAAA AAAAAAA
Port outputs configured using Register, shown Table Register switches Port from push/pull active open drain outputs. other bits this register implemented.
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAAAA
)4172$#0- 4')+56'4
1WVRWV
4GUGTXGF
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 4GUGTXGF 2QTV 1WVRWV %QPHKIWTCVKQP 8CNWG &GUETKRVKQP #NYC[U TGCFU 1111111 'HHGEV 2WUJ2WNN #EVKXG 1RGP &TCKP 1WVRWVU
2QTV %QPVTQN /QFG 4GIKUVGTU
Port general-purpose 8-bit, bidirectional port, shown Table Each eight Port lines independently programmed either input output using Port Mode Register (see Table 28.) 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4
2QTV &CVC
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV &CVC 8CNWG &CVC &GUETKRVKQP 2QTV +PRWV1WVRWV 4GIKUVGT )4172$#0- 4')+56'4
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV /QFG 5GNGEV 8CNWG &GUETKRVKQP #NYC[U TGCFU 11111111 +PRWV 1WVRWV
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
Register configures corresponding Port input, while configures output line.
2QTV %QPVTQN /QFG 4GIKUVGTU
Port general-purpose 8-bit, bidirectional port, shown Table Each eight Port lines independently programmed either input output using Port Mode Register (see Table 30.) 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
2QTV &CVC
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV &CVC 8CNWG &CVC &GUETKRVKQP 2QTV +PRWV1WVRWV 4GIKUVGT )4172$#0- 4')+56'4
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
AAAAAAA
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV /QFG 5GNGEV /QFG 5GNGEV 8CNWG &GUETKRVKQP +PRWV 1WVRWV 1WVRWV 4GICTFNGUU YJCV YTKVVGP VJKU CNYC[U EQPHKIWTGF QWVRWV
Register configures corresponding Port input, while configures output line.
016' P43, controlled current output pad, cannot configured input. (P43 read out)
2QTV %QPVTQN /QFG 4GIKUVGTU
Port general-purpose 8-bit, bidirectional port, shown Table Each eight Port lines independently programmed either input output using Port Mode Register (see Table 32.)
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
2QTV &CVC
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV &CVC 8CNWG &CVC &GUETKRVKQP 2QTV +PRWV1WVRWV 4GIKUVGT )4172$#0- 4')+56'4
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
AAAAAA
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV /QFG 5GNGEV /QFG 5GNGEV 8CNWG &GUETKRVKQP +PRWV 1WVRWV +PRWV 4GICTFNGUU YJCV YTKVVGP VJKU CNYC[U KPRWV OQFG
Register configures corresponding Port input, while configures output line.
016' Regardless bits set, always input mode.
2QTV %QPVTQN /QFG 4GIKUVGTU
Port general-purpose 8-bit, bidirectional port, shown Table Each eight Port lines independently programmed either input output using Port Mode Register (see Table 34.)
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
2QTV &CVC
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV &CVC 8CNWG &CVC &GUETKRVKQP 2QTV +PRWV1WVRWV 4GIKUVGT )4172$#0- 4')+56'4
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV /QFG 5GNGEV 8CNWG &GUETKRVKQP +PRWV 1WVRWV
Register configures corresponding Port input, while configures output line.
6KOGT %QPVTQN 4GIKUVGTU )GPGTCN2WTRQUG 6KOGT
Z86D99 provides standard 8-bit counter/timer, driven 6-bit prescaler, PRE1. independent processor instruction sequence, relieving software from time-critical operations such interval timing event counting. There three registers that control operation Data Register (T1), Mode Register (TMR), Prescale Register (PRE1). Because timer, prescaler, mode register mapped into standard register file, software treat counter/timer general-purpose register, thus eliminating requirement special instructions.
&CVC 4GIKUVGT
counter/timer register (T1) consists 8-bit down counter, write-only register that holds initial count value, read-only register that holds current count value. initial value range from represents 256) (see Table 35.)
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 $KV(KGNF 4GUGV
)4172$#0- 4')+56'4
6A8CNWG
4GCF 9TKVG +PFGVGTOKPCVG 2QUKVKQP
$KV(KGNF 8CNWG
8CNWG &CVC &CVC
&GUETKRVKQP %WTTGPV 8CNWG +PKVKCN 8CNWG
4CPIG &GEKOCN
/QFG 4GIKUVGT
Under software control, counter/timer started stopped using Mode Register shown Table 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAA 6176A/QFG 6+0A/QFG )4172$#0- 4')+56'4
%QWPV .QCF 4GUGTXGF
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 6IUT /QFG 8CNWG &GUETKRVKQP +PVGTPCN %NQEM 6176 4GUGTXGF WUGF
EQPHKIWTGF 6TKIIGT +PRWV
4GVTKIIGTCDNG 6TKIIGT +PRWV
0QVTGVTKIIGTCDNG )CVG +PRWV 'ZVGTPCN %NQEM +PRWV
'PCDNG &KUCDNG .QCF GHHGEV #NYC[U TGCFU GHHGEV
AAAAAA
/QFG
AAAAAAA AAAAAAA AAAAAA
.QCF 4GUGTXGF
2TGUECNG 4GIKUVGT
prescaler consists 8-bit register 6-bit down-counter. most significant bits (D2-D7) PRE1 hold prescaler's count modulo, value from decimal, shown Table
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
prescale register also contains control bits that specify counting mode clock source
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAAA AAAAAAAA )4172$#0- 4')+56'4
2TGUECNGTA/QFWNQ
%NQEMA %QWPVA 5QWTEG /QFG
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2TGUECNGT /QFWNQ %NQEM 5QWTEG %QWPV /QFG 8CNWG &CVC &GUETKRVKQP 4CPIG &GEKOCN +PVGTPCN 'ZVGTPCN
/QFWNQP 5KPING 2CUU
6KOGT %QPVTQN 4GIKUVGTU 6KOGTU
unique features Z86D99 family special timer architecture automate generation reception complex pulses signals. This timer architecture consists programmable 8-bit counter timer with capture registers load registers programmable 16-bit counter/timer with 16-bit capture register pair 16-bit load register pair their associated control registers. These counter/timers work independently combined together using number user-selectable modes governed T8/T16 control registers.
%QPVTQN 4GIKUVGT
T8/T16 Control Register controls functions common with both counter/timers. counter/timers have primary modes operation: Transmit Mode Demodulation Mode. Transmit Mode used generating complex waveforms. Transmit Mode submodes: Normal Mode Ping-Pong Mode. settings CTR1 Transmit Mode given Table
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4
64#05/+6 /1&')4172$#0- 4')+56'4 6TCPUOKVA 5WDOQFG
$KV(KGNF 4GUGV 2QUKVKQP AAAAAAA AAAAAAA AAAAAA
/QFG
66A.QIKE
+PKVKCNA +PKVKCNA 6A1WV
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF /QFG 2A1WV 6&6$ .QIKE 8CNWG &GUETKRVKQP &GOQFWNCVKQP 6TCPUOKV EQPHKIWTGF 1WVRWV EQPHKIWTGF 0#0& 6A1WV 6A1WV 2KPI2QPI /QFG 0QTOCN 1RGTCVKQP 6A1WV KPKVKCNN[ 6A1WV KPKVKCNN[ 6A1WV KPKVKCNN[ 6A1WV KPKVKCNN[
AAAAAA
6TCPUOKVA 5WDOQFG
AAAAAAA AAAAAAA
+PKVKCNA6A1WV +PKVKCNA6A1WV
Demodulation Mode, counter/timers used capture demodulate complex waveforms. settings CTR1 Demodulation Mode given Table
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4
&'/1&7.#6+10 /1&')4172$#0- $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA AAAAAAA AAAAAA /QFG &GOQF A+PRWV 'FIGA&GVGEV )NKVEJA(KNVGT 4KUKPI 'FIG (CNNKPI 'FIG
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF /QFG &GOQFWNCVQTA +PRWV 'FIGA&GVGEV 8CNWG &GUETKRVKQP &GOQFWNCVKQP 6TCPUOKV &GOQFWNCVQT +PRWV &GOQFWNCVQT +PRWV 4GUGTXGF $QVJ 'FIGU 4KUKPI 'FIG (CNNKPI 'FIG 5%.- %[ENGU 5%.- %[ENGU 5%.- %[ENGU (KNVGT 4KUKPI 'FIG &GVGEVGF 4KUKPI 'FIG 4GUGV (NCI 'HHGEV (CNNKPI 'FIG &GVGEVGF (CNNKPI 'FIG 4GUGV (NCI 'HHGEV
AAAAAA
)NKVEJA(KNVGT
AAAAAAA
4KUKPIA'FIG
AAAAAAA
(CNNKPIA'FIG
%QPVTQN 4GIKUVGT
T8/T16 Control Register known CTR3, register Z86D99 family. This register allows counters synchronized. settings CTR3 described Table
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA 'PCDNG 'PCDNG 5[PE /QFG
)4172$#0- 4')+56'4 4GUGTXGF
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 'PCDNG 8CNWG &GUETKRVKQP %QWPVGT 'PCDNGF %QWPVGT &KUCDNGF 'PCDNG %QWPVGT 5VQR %QWPVGT %QWPVGT 'PCDNGF %QWPVGT &KUCDNGF 'PCDNG %QWPVGT 5VQR %QWPVGT 'PCDNG 5[PE /QFG &KCDNG 5[PE /QFG #NYC[U TGCFU 11111 'HHGEV
AAAAAAA
'PCDNG
AAAAAAA
5[PE /QFG 4GUGTXGF
%QPVTQN 4GIKUVGT
shown Table Control Register,
known CTR0, controls operation 8-bit timer.
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4 'PCDNG 5KPING WNQP 6KOGA
)4172$#0- 4')+56'4
$KV(KGNF 4GUGV 2QUKVKQP AAAAAAA
6A%NQEM
%CRVWTG %QWPVGT +06A +06A /CUM /CUM
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 'PCDNG 8CNWG &GUETKRVKQP %QWPVGT 'PCDNGF %QWPVGT &KUCDNGF 'PCDNG %QWPVGT 5VQR %QWPVGT 5KPING 2CUU /QFWNQP %QWPVGT 6KOGQWV 1EEWTTGF %QWPVGT 6KOGQWV 4GUGV (NCI 'HHGEV 5%.- 5%.- 5%.- 5%.'PCDNG &CVC %CRVWTG +PVGTTWRV &KUCDNG &CVC %CRVWTG +PVGTTWRV 'PCDNG 6KOGA1WV +PVGTTWRV &KUCDNG 6KOGA1WV +PVGTTWRV EQPHKIWTGF 1WVRWV EQPHKIWTGF
AAAAAAA AAAAAAA
5KPING /QFWNQP 6KOGA1WV
AAAAAA
%NQEM
AAAAAAA AAAAAAA AAAAAAA
%CRVWTG +PVGTTWRV /CUM %QWPVGT +PVGTTWRV /CUM 2A1WV
*KIJ %CRVWTG 4GIKUVGT
High Capture Register, Table holds
captured data from output counter/timer. This register typically used hold number counts when input signal high
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4)4172$#0- 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
6A%CRVWTGA*+
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF %CRVWTG *KIJ 8CNWG 8CNWG &CVC &GUETKRVKQP %CRVWTGF &CVC 'HHGEV
%CRVWTG 4GIKUVGT
Capture Register, Table holds
captured data from output counter/timer. This register typically used hold number counts when input signal
6#$.' 4')+56'4)4172$#0- 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
6A%CRVWTGA.1
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF %CRVWTG 8CNWG 8CNWG &CVC &GUETKRVKQP %CRVWTGF &CVC 'HHGEV
*KIJ .QCF 4GIKUVGT
High Load Register, Table loaded with counter value necessary keep T8_Out signal high state required time. 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4 6A.GXGNA*+
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF .GXGN *KIJ 8CNWG 8CNWG &CVC &GUETKRVKQP &WTCVKQP VJCV 6A1WV TGOCKPU *KIJ
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
.QCF 4GIKUVGT
Load Register, Table loaded with counter value necessary keep T8_Out signal state required time. 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4 6A.GXGNA.1
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF .GXGN 8CNWG 8CNWG &CVC &GUETKRVKQP &WTCVKQP VJCV 6A1WV TGOCKPU
%QPVTQN 4GIKUVGT
Control Register, know CTR2, con-
trols operation 16-bit timer (see Table 46).
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
6#$.' 4')+56'4 'PCDNG 5KPING WNQP 6KOGA
)4172$#0- 4')+56'4
$KV(KGNF 4GUGV 2QUKVKQP AAAAAAA
6A%NQEM
%CRVWTG %QWPVGT +06A +06A /CUM /CUM
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 'PCDNG 8CNWG AAAAAAA 6KOGA1WV &GUETKRVKQP %QWPVGT 'PCDNGF %QWPVGT &KUCDNGF 'PCDNG %QWPVGT 5VQR %QWPVGT 6TCPUOKV /QFG 5KPING 2CUU /QFWNQP &GOQFWNCVKQP /QFG &QGU 4GEQIPK\G 'FIG 4GEQIPK\GU 'FIG %QWPVGT 6KOGQWV 1EEWTTGF %QWPVGT 6KOGQWV 4GUGV (NCI 'HHGEV 5%.- 5%.- 5%.- 5%.'PCDNG &CVC %CRVWTG +PVGTTWRV &KUCDNG &CVC %CRVWTG +PVGTTWRV 'PCDNG 6KOGA1WV +PVGTTWRV &KUCDNG 6KOGA1WV +PVGTTWRV EQPHKIWTGF 1WVRWV EQPHKIWTGF
AAAAAAA
5KPING /QFWNQP
AAAAAA
%NQEM
AAAAAAA AAAAAAA AAAAAAA
%CRVWTG +PVGTTWRV /CUM %QWPVGT +PVGTTWRV /CUM 2A1WV
/5$[VG %CRVWTG 4GIKUVGT
MS-Byte Capture Register, Table holds captured data from output counter/timer. This register holds most significant byte data.
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
6A%CRVWTGA*+
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF %CRVWTG 8CNWG &CVC &GUETKRVKQP /5$[VG %CRVWTGF &CVC 'HHGEV
.5$[VG %CRVWTG 4GIKUVGT
LS-Byte Capture Register, Table holds captured data from output counter/timer. This register holds least significant byte data. 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4
6A%CRVWTGA.1
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF %CRVWTG 8CNWG &CVC &GUETKRVKQP .5$[VG %CRVWTGF &CVC 'HHGEV
/5$[VG .QCF 4GIKUVGT
MS-Byte Load Register, Table loaded with most significant byte counter value. 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4 6A&CVCA*+
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF &CVC 8CNWG &CVC &GUETKRVKQP /5$[VG %QWPVGT
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
.5$[VG .QCF 4GIKUVGT
LS-Byte Load Register, Table loaded with least significant byte counter value. 6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP )4172$#0- 4')+56'4 6A&CVCA.1
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF &CVC 8CNWG &CVC &GUETKRVKQP .5$[VG %QWPVGT
5VQR/QFG 4GEQXGT[ %QPVTQN 4GIKUVGTU
Z86D99 family products allows individual pins (Ports used stop-mode recovery sources. STOP mode exited when these sources toggled.
5VQR/QFG 4GEQXGT[ 4GIKUVGT register serves functions.
register, shown Table Stop Mode Flag that upon entering stop mode. this indicates that device been reset Reset. Reset sometimes referred "cold" start. indicates that device awakened source. Waking device with source sometimes referred "warm" start.
24'.+/+0#4;
25+44
4')+56'45
)4172'& (70%6+10
%10641. 56#675 4')+56'45
6#$.' 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP AAAAAAA 5VQR (NCI UGTXGF 5VQR &GNC[
)4172$#0- 4')+56'4 4GUGTXGF 5%.- 5GNGEV
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 5VQR /QFG (NCI 8CNWG &GUETKRVKQP 5VQR 4GEQXGT[
YCTO UVCTV 2149&6 4GUGV
EQNF UVCTV 'HHGEV #NYC[U TGCFU 'HHGEV #NYC[U TGCFU 'PCDNG 4GUGV FGNC[ &KUCDNG 4GUGV FGNC[ CHVGT #NYC[U TGCFU 'HHGEV #NYC[U TGCFU 5%.- 6%.- :6#. 5%.- 6%.- :6#. 5%.- 6%.- :6#. 5%.- 6%.- :6#.
AAAAAAA AAAAAAA
4GUGTXGF 5VQR &GNC[
AAAAA AAAAAAA
4GUGTXGF 5[UVGO %NQEM 5GNGEV
second function register selection external clock divide value. purpose this control selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources counter/timers interrupt logic).
2QTV 5VQR /QFG 4GEQXGT[
25/4 P2SMR register, Table defines
which lines Port used stop mode recovery sources.
6#$.' 25/4 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV 5VQR /QFG 4GEQXGT[ 8CNWG &GUETKRVKQP 4GEQXGT[ 5QWTEG
25+44
24'.+/+0#4;
%10641. 56#675 4')+56'45
4')+56'45
)4172'& (70%6+10
2QTV 5VQR/QFG 4GEQXGT[
25/4 P5SMR register, Table defines which lines Port used stop-mode recovery sources. 6#$.' 25/4 4')+56'4 $KV(KGNF 4GUGV 2QUKVKQP
)4172$#0- 4')+56'4
4GCF 9TKVG +PFGVGTOKPCVG $KV(KGNF 2QTV 5VQR /QFG 4GEQXGT[ 8CNWG &GUETKRVKQP 4GEQXGT[ 5QWTEG
24'.+/+0#4;
25+44
#$51.76' /#:+/7/ 4#6+0)5
'.'%64+%#. %*#4#%6'4+56+%5
'.'%64+%#. %*#4#%6'4+56+%5
#$51.76' /#:+/7/ 4#6+0)5
6#$.' #$51.76' /#:+/7/ 4#6+0)5 5[ODQN 8G5X 6STA 8R5G
016'
&GUETKRVKQP 5WRRN[ 8QNVCIG
5VQTCIG 6GOR 1RGT #ODKGPV 6GOR /KPKOWO 8QNVCIG
7PKVU
8QNVCIG RKPU YKVJ TGURGEV 1TFGTKPI +PHQTOCVKQP RCIG 'UVKOCVGF XCNWG VGUVGF
Stresses greater than those listed preceding table cause permanent damage device. This rating stress rating only. Functional operation device condition above those indicated operational sections these specifications implied. Exposure absolute maximum rating conditions extended period affect device reliability.
56#0& 6'56 %10&+6+105
characteristics listed below apply standard test conditions noted. voltages referenced GND. Positive current flows into referenced (see Figure 23).
)URP 2XWSXW 8QGHU 7HVW
(+)74' 6'56 .1#& &+#)4#/
%*#4#%6'4+56+%5
6#$.' %*#4#%6'4+56+%5 5[ODQN 2CTCOGVGT 2QYGT 5WRRN[ 8QNVCIG 7PKVU %QOOGPVU
25+44
24'.+/+0#4;
'.'%64+%#. %*#4#%6'4+56+%5
%*#4#%6'4+56+%5
6#$.' %*#4#%6'4+56+%5
%106+07'& 5[ODQN +77I 2CTCOGVGT %NQEM +PRWV *KIJ 8QNVCIG %NQEM +PRWV 8QNVCIG +PRWV *KIJ 8QNVCIG +PRWV 8QNVCIG 1WVRWV *KIJ 8QNVCIG 4GIWNCT *KIJ &TKXG 2KPU
4GIWNCT 1WVRWV XQNVCIG *KIJ &TKXG 2KPU
%QPVTQNNGF %WTTGPV 1WVRWV
+PRWV .GCMCIG 5WRRN[ %WTTGPV 7PKVU %QOOGPVU &TKXGP ENQEM IGPGTCVQT &TKXGP ENQEM IGPGTCVQT
8QWV
(KIWTG 8KPX 8KPX 8KP8 %NQEM FKXKFGF :6#. TWPPKPI 8KPX 8888FV
5VCPFD[ %WTTGPV
*CNV /QFG
+587
5VCPFD[ %WTTGPV
5612 /QFG 5VCPFD[ %WTTGPV
8QNVCIG %WTTGPV YKVJ 4WPPKPI .QY8QNVCIG 2TQVGEVKQP .QY$CVVGT[ &GVGEVKQP
XQNVCIG UQOGVKOGU MPQY DTQYPQWV
24'.+/+0#4;
25+44
%*#4#%6'4+56+%5
'.'%64+%#. %*#4#%6'4+56+%5
%*#4#%6'4+56+%5
6#$.' %*#4#%6'4+56+%5 5[ODQN 6Y6KP. 6Y6KP* 6R6KP 6T6KP 6H6KP 6Y+. 6Y+* 6YUO 6YFV 2CTCOGVGT +PRWV %NQEM 2GTKQF %NQEM +PRWV 4KUG (CNN 6KOGU +PRWV %NQEM 9KFVJ 6KOGT +PRWV 9KFVJ 6KOGT +PRWV *KIJ 9KFVJ 6KOGT +PRWV 2GTKQF 6KOGT +PRWV 4KUG (CNN 6KOG +PVGTTWRV 4GSWGUV 6KOG +PVGTTWRV 4GSWGUV +PRWV *KIJ 6KOG 5VQR/QFG 4GEQXGT[ 9KFVJ 5RGE 9CVEJ&QI 6KOGT 6KOG 7PKVU
25+44
24'.+/+0#4;
10'6+/' 241)4#//+0)
&'6#+.'& &'5%4+26+105 241)4#//+0) /1&'
10'6+/' 241)4#//+0)
Z86D99 features 256K bits that arranged 32kx8. features internal address generator that automatically increments while programming reading externally. inputs used similarly Z86E08 when mode.
&'6#+.'& &'5%4+26+105
241)4#//+0) /1&'
following description pinouts functions pins when part placed either test modes. pins have High-Voltage Detector (HVD), which circuit detect input voltages higher than V88. This high voltage referred output logic depending input above below respectively. pins that have EPM.
Input that supplies programming voltage current program OTP. This also used latch modes described Table page When goes above four address bits latched become mode (3:0) inputs OTP. enter normal program/verify mode, raised address cleared zero with pin, then raised Vpp. enter other mode, address must incremented with input appropriate address before raised Vpp.
Input pin. When this raised above used place external modes. This enables mode latch switches address muxes external mode. must raised before raised Vpp. clear mode, both must reduced below
Input pin; active output enable. When low, output data pins contain data from OTP. When high (V88), data outputs tristated. this control output pins, part must external mode having above
Input that enables operation when low. When high (VCB), disabled. When this high, disabled regardless what mode currently
24'.+/+0#4;
25+44
/1&' &'5%4+26+105
10'6+/' 241)4#//+0)
Input pin. active programming pulse that applies during programming.
Input pin. This increments address counter. used sequence through address during programming reading external mode.
Input pin. This clears address counter. used beginning programming reading initialize counter zero.
pins that contain data program mode from read mode. most significant used program/read shadow column when that mode.
1&1$
No-connection pins. These pins should have valid logic state when mode minimize current through input buffers.
/1&' &'5%4+26+105
modes incrementing address counter until correct mode number least significant bits address raising above After setup time, raised above latch mode. left high lowered below depending mode. However, each time raised above mode latched (except margin read mode). only change margin read mode reduce both below start over. program/read cycles same mode, eliminating required long programming pulses option bits. Address (3:0) mode (3:0) one. example, user sets page-4 mode, above address incremented (1101h), then raised Vpp. This action latches mode, subsequent program cycles page-4 mode. Clear address back zero after latching mode before beginning first program/read address zero. address reset back zero, first addresses might missed.
6#$.' 241)4#//+0) /1&'5 5VCPFCTF /QFG /QFG *CNV /QFG &KTGEVKQP
/QFG 0WODGT #FFTGUU
25+44
24'.+/+0#4;
10'6+/' 241)4#//+0)
/1&' &'5%4+26+105
6#$.' 241)4#//+0) /1&'5
%106+07'& 5VCPFCTF /QFG /QFG 6GUV 1RVKQP $KVU /CTIKP 5JCFQY %QNWOP 5JCFQY 4GCF 9KVJQWV DQQUVGTU
KPVGTPCN QPN[ 2QYGT1P 4GUGV 7PWUGF 7PWUGF 7PWUGF 2CIG 2TQITCO 2CIG 2TQITCO 2CIG 2TQITCO &TCKP &KUVWTD ,QWHUQDO 0RGH &KTGEVKQP
/QFG 0WODGT #FFTGUU
normally operates internal mode operation. Internal mode default mode when pins both below When this mode, four mode inputs tied logic mode input also forced inactive that programming occurs. result, allowed read from OTP. part placed test mode halt mode, still responds correctly because these inputs override mode inputs.
Standard external mode where access only through external pins. This mode entered raising above clearing address counter zero pulsing high, then raising above
+DOW 0RGH +LJK
halt mode turns drivers OTP, shuts down sense amplifiers, kills voltage clamp circuit. mode entered same mode, after clearing address zero, address must incremented pulsing input time before raised above Halt mode also entered placing high. Internally, force halt mode also.
7HVW
This mode allows user read test contents. entered same mode except that address incremented twice before raising above
24'.+/+0#4;
25+44
/1&' &'5%4+26+105
10'6+/' 241)4#//+0)
When internal mode selected, force into test mode overriding mode inputs.
2SWLRQV
selecting this mode, option bits made available. bits word reserved hardwired option bits while rest free used. program option bits, raised above address counter cleared, then address counter incremented Then raised latch option mode. address counter again cleared, normal program cycle started. data Table placed data bus, input pulsed programming algorithm.
6#$.' 126+10 $+65 &GUETKRVKQP
&GHCWNV 9QTF 9QTF
KPVGTPCN QPN[
FKUCDNG (GGFDCEM FKUCDNG
GPCDNG 2WNNWR
FKUCDNG 2WNNWR
FKUCDNG 2WNNWR
FKUCDNG NGXGN
:6#.4%
:6#. RTQVGEVKQP
RTQVGEVGF RTQITCOOGF DCPFICR GPCDNGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 4GUGTXGF 2WNNWR
FKUCDNGF 2WNNWR
FKUCDNGF
protected, forced into option mode. other mode accessed externally.
016' program data word, placed appropriate position. leave
unprogrammed, place that position. When bits read using option mode, programmed bits read unprogrammed bits read 0DUJLQV
This mode allows read while having complete control gate voltage through pin. Enter this mode normal using address Since input also used latch modes, this function
25+44
24'.+/+0#4;
10'6+/' 241)4#//+0)
126+10 &'5%4+26+10
inhibited because input vary during this mode. only exit margin read mode reduce both inputs below thereby resetting mode latches.
6KDGRZ &ROXPQ
This mode allows reads writes shadow column. most significant data word (bit used read write column. other bits data word garbage.
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This mode allows reads writes shadow row.
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This mode allows reads with voltage boosters disabled; used only testing.
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This mode active automatically during power-on reset. initially used latch option bits longer required. option bits have been changed read continuously, this mode longer used.
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This mode allows programming locations with write cycle.
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This mode allows programming four locations with write cycle.
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This mode allows programming eight locations with write cycle.
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This mode connects lines simultaneously while disconnecting word lines. This mode used stress cell drains with high voltage simultaneously.
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This section describes option bits.
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This controls band-gap VBO. default, only enabled. this programmed, both band-gap enabled, reset occurs when lower than bigger (band-gap
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When programmed, pull-up transistors enabled P13. default disable.
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When programmed, pull-up transistors enabled P17. default disable.
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When programmed, enabled permanently. default that permanently enabled.
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This option switches oscillator drive 32-Khz applications. default normal oscillator mode.
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When programmed, pull-up transistors enabled P27. default disable.
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When programmed, pull-up transistors enabled P07. default disable.
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When programmed, pull-up transistors enabled P03. default disable.
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When programmed, level 0.4Vdd. default 0.5Vdd.
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crystal oscillator option sets oscillator input internal crystal oscillator. When this programmed, oscillator mode active. default crystal.
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purpose protect option disable access data from outside world, thereby protecting proprietary code from being read. Once this programmed, enters only option mode. cannot enter other mode. read attempted while protected, data comes only from option row. default protected.
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Read Operating Voltage: 4.50 Read Operating Frequency: 1.67 MHz) Read Operating Temperature: 105C Programming Voltage: 13.0 0.25 Program/Verify V88: 0.10 Programming Temperature: Supply Current: Specification Pins EPM: Table
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Recommended Levels:
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Power-on reset mode select assumed complete. Unless otherwise noted, levels power-on reset assumed completed before raised Refer power-up waveforms initial timings. signal must make both transitions each address.
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Unless otherwise noted, levels program/verify cycle repeats Over Program last cycle, programming algorithm.
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program/read mode default mode (addr=0) that occurs automatically when kept. already program/read mode (mode when kept. Different modes entered raising after number pulses. preceding example, raised after pulses, which placed mode
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modes entered first setting above address counter cleared with ADRST then incremented appropriate address. raised above latch mode, address counter must reset zero before continuing. Refer Standard Cell Documentation correct address sequence while page modes. input should ever exceed VPP. during program/verify must Variable from VPP. after latching mode
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uses Pierce oscillator with internal feedback circuit. advantages this circuit cost, large output signal, low-power level crystal, stability with respect temperature, impedances (not disturbed stray effects.) drawback requirement high gain amplifier compensate feedback path losses. Traces connecting crystal, capacitors, oscillator pins must short wide possible. Short wide traces reduce parasitic inductance resistance. components (capacitors, crystal, resistors) must placed close possible oscillator pins traces from oscillator pins integrated circuit (IC) ground side lead capacitors must guarded from other traces (clock, VCC, system ground) reduce cross-talk noise injection. Guarding traces usually accomplished keeping other traces system ground trace planes away from oscillator circuit placing device ground ring around traces/components. ground side oscillator lead capacitors must connected single trace (GND) pin. must shared with other system ground trace components except device pin. sharing ground side oscillator lead capacitors prevent differential system ground noise injection into oscillator.
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fast results, contact your local ZiLOG sale offices assistance ordering part(s).
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using logical instruction mask, individual bits within registers accessed set, clear, complement, test operations. allows different interrupts from variety sources. These interrupts masked their priorities using Interrupt Mask Register Interrupt Priority Register. Polled interrupt processing supported masking polled.
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submit code, obtain user which obtained contacting ZiLOG sales offices. Then www.zilog.com choose Code Submissions under Support left-hand bar. with your assigned user follow instructions your code. able download results within seconds. After verifying that correct, sign form that generated number indicated form send mask production appropriate sales office.
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product represented this document newly introduced ZiLOG completed full characterization product. document states what ZiLOG knows about this product this time, additional features nonconformance with some aspects document might found, either ZiLOG customers course further application characterization work. addition, ZiLOG cautions that delivery might uncertain times, start-up yield issues. ZiLOG, Inc. East Hamilton Avenue, Suite Campbell, 95008 Telephone (408) 558-8500 558-8300 Internet: +773:::=,/2*&20
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