5.0V 512K CMOS SRAM Features compatible AS7C4096 Industrial comme

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5.0V 512K CMOS SRAM Features compatible AS7C4096 Industrial comme

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AS7C4096A
5.0V 512K CMOS SRAM Features
compatible AS7C4096 Industrial commercial temperature Organization: 524,288 words bits Center power ground pins High speed
10/12/15/20 address access time output enable access time
Equal access cycle times Easy memory expansion with inputs TTL-compatible, three-state JEDEC standard packages protection 2000 volts Latch-up current
36-pin 44-pin TSOP
power consumption: ACTIVE
880mW/max
power consumption: STANDBY
55mW/max CMOS
Logic block diagram
Input buffer I/O1
arrangements
36-pin (400 mil)
I/O1 I/O2 I/O3 I/O4 I/O8 I/O7 I/O6 I/O5 I/O1 I/O2 I/O3 I/O4
44-pin TSOP
I/O8 I/O7 I/O6 I/O5
decoder
524,288 Array (4,194,304)
Sense
I/O8 Column decoder
Control Circuit
Selection guide
Maximum address access time Maximum outputenable access time Maximum operating current Maximum CMOS standby current Unit
5/27/05,
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS7C4096A
Functional description
AS7C4096A high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized 524,288 words bits. designed memory applications where fast data access, power, simple interfacing desired. Equal address access cycle times (tAA, tRC, tWC) 10/12/15/20 with output enable access times (tOE) ideal high-performance applications. chip enable input permits easy memory expansion with multiple-bank memory systems. When high device enters standby mode. device guaranteed exceed 55mW power consumption CMOS standby mode. write cycle accomplished asserting write enable (WE) chip enable (CE). Data input pins I/O1-I/O8 written rising edge (write cycle (write cycle avoid contention, external devices should drive pins only after outputs have been disabled with output enable (OE) write enable (WE). read cycle accomplished asserting output enable (OE) chip enable (CE), with write enable (WE) high. chip drives pins with data word referenced input address. When either chip enable output enable inactive, write enable active, output drivers stay high-impedance mode. chip inputs outputs TTL-compatible, operation from single 5.0V supply voltage. This device available industry standard 400-mil 36-pin 44-pin TSOP packages.
Absolute maximum ratings
Parameter Voltage relative Voltage relative Power dissipation Storage temperature (plastic) Temperature with applied current into output (low) Symbol Tstg Tbias IOUT -0.5 -0.5 +7.0 +0.5 +150 +125 Unit
NOTE: Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Truth table
Data Mode
High High DOUT
Standby (ISB, ISB1) Output disable (ICC) Read (ICC) Write (ICC)
5/27/05,
Alliance Semiconductor
AS7C4096A
Recommended operating condition
Parameter Supply voltage Input voltage Ambient operating temperature
commercial industrial
Symbol VCC(10/12/15/20) VIH* VIL**
-0.5
Nominal
Unit
1.5V pulse width less than -1.0V pulse width less than
operating characteristics (over operating range)1
Parameter Input leakage current Output leakage current Operating power supply current Symbol |ILI| |ILO| Standby power supply current Test conditions Max, Max, VOUT= Max, fMax, IOUT Max, fMax, IOUT Max, 0.2V, 0.2V 0.2V, Unit Notes
ISB1
Output voltage
Capacitance 1MHz, NOMINAL)4
Parameter Input capacitance capacitance Symbol CI/O Signals Test conditions VOUT Unit
5/27/05,
Alliance Semiconductor
AS7C4096A
Read cycle (over operating range)2,8
Parameter Read cycle time Address access time Chip enable (CE) access time Output enable (OE) access time Output hold from address change output High output high output High output high Power time Power down time Symbol tACE tCLZ tCHZ tOLZ tOHZ Unit Notes
switching waveforms
Rising input Falling input Undefined/don't care
Read waveform (address controlled)2,5,6,8
Address DOUT Data valid
Read waveform (CE, controlled)2,5,7,8
tRC1 tOLZ tACE DOUT tCLZ Supply current Data valid tOHZ tCHZ
5/27/05,
Alliance Semiconductor
AS7C4096A
Write cycle (over operating range)9
Parameter Write cycle time Chip enable (CE) write Address setup write Address setup time Write pulse width high) Write pulse width Address hold from write Write recovery time Data valid write Data hold time Write enable output high Output active from write Symbol tWP1 tWP2 Unit Notes
Write waveform controlled)9
Address DOUT Data valid
5/27/05,
Alliance Semiconductor
AS7C4096A
Write waveform controlled)9
Address Data valid
test conditions
Output load: Figure Input pulse level: 0.5V. Figures Input rise fall times: Figure Input output timing reference levels: 1.5V.
DOUT
+5.0V
Thevenin equivalent: DOUT +1.728V
0.5V
Figure Input pulse
Figure 5.0V Output load
Notes
During power-up, pull-up resistor required meet specification. test conditions, Test Conditions. tCLZ tCHZ specified with Figure Transition measured ±500 from steady-state voltage. This parameter guaranteed, tested. HIGH read cycle. read cycle. Address valid prior coincident with transition Low. read cycle timings referenced from last valid address first transitioning address. write cycle timings referenced from last valid address first transitioning address. 30pF, except high parameters, where 5pF.
5/27/05,
Alliance Semiconductor
AS7C4096A
Package dimensions
44434241403938 34333231 2726 2524
44-pin TSOP
111213 1819
0-5°
44-pin TSOP Min(mm) Max(mm) 0.05 0.15 0.95 1.05 0.30 0.45 0.21 0.12 18.31 18.52 10.06 10.26 11.68 11.94 0.80 (typical) 0.40 0.60 36-pin Min(mils) Max(mils) 0.128 0.148 0.025 0.105 0.115 0.015 0.020 0.026 0.032 0.007 0.013 .920 .930 0.045 0.055 0.370 0.395 0.405 0.435 0.445
36-pin Seating Plane
5/27/05,
Alliance Semiconductor
AS7C4096A
Ordering codes
Package TSOP Version Commercial Industrial Commercial Industrial AS7C4096A-10JC AS7C4096A-10JI AS7C4096A-10TC AS7C4096A-10TI AS7C4096A-12JC AS7C4096A-12JI AS7C4096A-12TC AS7C4096A-12TI AS7C4096A-15JC AS7C4096A-15JI AS7C4096A-15TC AS7C4096A-15TI AS7C4096A-20JC AS7C4096A-20JI AS7C4096A-20TC AS7C4096A-20TI
Note: suffix above part number Lead Free Parts. (Ex: AS7C4096A TIN)
Part numbering system
AS7C SRAM prefix 4096A Device number Access time Packages: TSOP Temperature ranges: Commercial, 70°C Industrial, -40°C 85°C N=Lead Free Parts
5/27/05,
Alliance Semiconductor
AS7C4096A
Revision History
Rev. v1.0 v1.1 Initial release Included ICC, ISB1 parameters Corrected following: TOE, VIH, History Revised Date 11/08/04 05/27/05
5/27/05,
Alliance Semiconductor
AS7C4096A
Alliance Semiconductor Corporation 2575, Augustine Drive, Santa Clara, 95054 Tel: 4900 Fax: 4999 www.alsc.com
Copyright Alliance Semiconductor Rights Reserved Part Number: AS7C4096A Document Version:
Copyright 2003 Alliance Semiconductor Corporation. rights reserved. three-point logo, name Intelliwatt trademarks registered trademarks Alliance. other brand product names trademarks their respective companies. Alliance reserves right make changes this document products time without notice. Alliance assumes responsibility errors that appear this document. data contained herein represents Alliance's best data and/or estimates time issuance. Alliance reserves right change correct this data time, without notice. product described herein under development, significant changes these specifications possible. information this product data sheet intended general descriptive information potential customers users, intended operate provide, guarantee warrantee user customer. Alliance does assume responsibility liability arising application product described herein, disclaims express implied warranties related sale and/or Alliance products including liability warranties related fitness particular purpose, merchantability, infringement intellectual property rights, except express agreed Alliance's Terms Conditions Sale (which available from Alliance). sales Alliance products made exclusively according Alliance's Terms Conditions Sale. purchase products from Alliance does convey license under patent rights, copyrights; mask works rights, trademarks, other intellectual property rights Alliance third parties. Alliance does authorize products critical components life-supporting systems where malfunction failure reasonably expected result significant injury user, inclusion Alliance products such lifesupporting systems implies that manufacturer assumes risk such agrees indemnify Alliance against claims arising from such use.

5.0V 512K CMOS SRAM Features compatible AS7C4096 Industrial comme

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