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Intel® XeonProcessor with Cache 1.80 2.40
Available 1.80, 2.20, 2.40 Dual processing server/workstation support Binary compatible with applications running previous members Intel's IA32 microprocessor line Intel® NetBurstmicro-architecture Hyper-Threading Technology Hardware support multithreaded applications System Bandwidth GB/second Rapid Execution Engine: Arithmetic Logic Units (ALUs) twice processor core frequency Hyper Pipelined Technology Advance Dynamic Execution Very deep out-of-order execution Enhanced branch prediction Level Execution Trace Cache stores micro-ops removes decoder latency from main execution loops Includes Level data cache
Advanced Transfer Cache (on-die, full speed Level cache) with 8-way associativity Error Correcting Code (ECC) Enables system support physical memory Streaming SIMD Extensions (SSE2) instructions double-precision floating point operations, media/video streaming, secure transactions Enhanced floating point multimedia unit enhanced video, audio, encryption, performance Power Management capabilities System Management mode Multiple low-power states Advanced System Management Features System Management Processor Information (PIROM) Scratch EEPROM Thermal Monitor Machine Check Architecture (MCA)
Intel® Xeonprocessor with cache designed high-performance dualprocessor workstation server applications. Based Intel® NetBurstmicroarchitecture Hyper-Threading Technology, binary compatible with previous Intel Architecture (IA-32) processors. Intel Xeon processor with cache scalable processors multiprocessor system providing exceptional performance applications running advanced operating systems such Windows XP*, Windows* 2000, Linux*, UNIX*. Intel Xeon processor with cache delivers compute power unparalleled value flexibility powerful workstations, internet infrastructure, departmental server applications. Intel® NetBurstmicro-architecture HyperThreading Technology deliver outstanding performance headroom peak internet server workloads, resulting faster response times, support more users, improved scalability.
Order Number: 298642-003 2002
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. Intel® Xeonprocessor contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800-548-4725 visiting Intel's website http://www.intel.com. Intel, Pentium, Pentium Xeon, Intel Xeon Intel NetBurst trademark registered trademarks Intel Corporation subsidiaries United States other countries. Copyright Intel Corporation, 2002 Other names brands claimed property others.
Contents
Contents
Introduction. Terminology 1.1.1 Processor Packaging Terminology State Data.11 References Electrical Specifications System GTLREF Power Ground Pins Decoupling Guidelines.13 2.3.1 Decoupling 2.3.2 System AGTL+ Decoupling System Clock (BCLK[1:0]) Processor Clocking.14 2.4.1 Clock. Filter 2.5.1 Mixing Processors Voltage Identification 2.6.1 Mixing Processors Different Voltages. Reserved Unused Pins System Signal Groups.20 Asynchronous GTL+ Signals 2.10 Maximum Ratings 2.11 Processor Specifications 2.12 AGTL+ System Specifications.28 2.13 System Specifications 2.14 Processor Timing Waveforms.32 System Signal Quality Specifications System Clock (BCLK) Signal Quality Specifications Measurement Guidelines System Signal Quality Specifications Measurement Guidelines System Signal Quality Specifications Measurement Guidelines 3.3.1 Overshoot/Undershoot Guidelines. 3.3.2 Overshoot/Undershoot Magnitude. 3.3.3 Overshoot/Undershoot Pulse Duration 3.3.4 Activity Factor 3.3.5 Reading Overshoot/Undershoot Specification Tables 3.3.6 Determining System Meets Overshoot/Undershoot Specifications Mechanical Specifications Mechanical Specifications Processor Package Load Specifications Insertion Specifications.57 Mass Specifications Materials Markings Pin-Out Diagram Listing Signal Definitions Processor Assignments.61 5.1.1 Listing Name. 5.1.2 Listing Number
Contents
Signal Definitions. Thermal Specifications Thermal Specifications Measurements Thermal Specifications 6.2.1 Processor Case Temperature Measurement Features Power-On Configuration Options. Clock Control Power States 7.2.1 Normal State-State 7.2.2 AutoHALT Powerdown State-State 7.2.3 Stop-Grant State-State 7.2.4 HALT/Grant Snoop State-State 7.2.5 Sleep State-State 7.2.6 Response During Power States. Thermal Monitor 7.3.1 Thermal Diode System Management (SMBus) Interface 7.4.1 Processor Information (PIROM) 7.4.2 Scratch EEPROM. 7.4.3 PIROM Scratch EEPROM Supported SMBus Transactions 7.4.4 SMBus Thermal Sensor 7.4.5 Thermal Sensor Supported SMBus Transactions 7.4.6 SMBus Thermal Sensor Registers 7.4.7 SMBus Thermal Sensor Alert Interrupt. 7.4.8 SMBus Device Addressing Boxed Processor Specifications Introduction. Mechanical Specifications 8.2.1 Boxed Processor Heatsink Dimensions 8.2.2 Boxed Processor Heatsink Weight 8.2.3 Boxed Processor Retention Mechanism Heatsink Supports Boxed Processor Requirements. 8.3.1 Intel® XeonProcessor with Cache Thermal Specifications 8.4.1 Boxed Processor Cooling Requirements. Debug Tools Specifications Logic Analyzer Interface (LAI) 9.1.1 Mechanical Considerations 9.1.2 Electrical Considerations
Contents
Figures
Buffers Buffers Typical VCCIOPLL, VCCA VSSA Power Distribution Phase Lock Loop (PLL) Filter Requirements Intel® XeonProcessor with Cache Voltage-Current Projections Electrical Test Circuit.33 Clock Waveform.33 Differential Clock Waveform.34 System Common Clock Valid Delay Timing Waveform System Source Synchronous (Address) Timing Waveform.35 System Source Synchronous (Data) Timing Waveform System Reset Configuration Timing Waveform Power-On Reset Configuration Timing Waveform Valid Delay Timing Waveform Test Reset (TRST#), Async GTL+ Input, PROCHOT# Timing Waveform THERMTRIP# Timing SMBus Timing Waveform.39 SMBus Valid Delay Timing Waveform Example VDC/SM_VCC Sequencing.40 BCLK[1:0] Signal Integrity Waveform.42 Low-to-High System Receiver Ringback Tolerance AGTL+ Asynchronous GTL+ High-to-Low System Receiver Ringback Tolerance AGTL+ Asynchronous GTL+ Low-to-High System Receiver Ringback Tolerance Buffers High-to-Low System Receiver Ringback Tolerance Buffers Maximum Acceptable Overshoot/Undershoot Waveform INT-mPGA Processor Package Assembly Drawing (Includes Socket) INT-mPGA Processor Package View: Component Placement Detail.52 INT-mPGA Processor Package Drawing INT-mPGA Processor Package View: Component Height Keep-in INT-mPGA Processor Package Cross Section View: Side Component Keep-in INT-mPGA Processor Package: Detail Flatness Tilt Drawing.56 Processor Top-Side Markings Processor Bottom-Side Markings.58 Processor Diagram: View.59 Processor Diagram: Bottom View Processor with Thermal Mechanical Components Exploded View Thermal Measurement Point Processor TCASE.91 Stop Clock State Machine Logical Schematic SMBus Circuitry Mechanical Representation Boxed Processor Passive Heatsink.109 Boxed Processor Retention Mechanism Clip .111 Multiple View Space Requirements Boxed Processor .112 Processor Wind Tunnel General Dimensions .114 Processor Wind Tunnel Detailed Dimensions .116
Contents
Tables
System Bus-to-Core Frequency Ratio. System Clock Frequency Select Truth Table BSEL[1:0]. Voltage Identification Definition System Signal Groups. Processor Absolute Maximum Ratings. Voltage Current Specifications System Differential BCLK Specifications. AGTL+ Signal Group Specifications. Signal Group Specifications Asynchronous GTL+ Signal Group Specifications SMBus Signal Group Specifications. AGTL+ Voltage Definitions. System Differential Clock Specifications System Common Clock Specifications. System Source Synchronous Specifications. Miscellaneous Signals+ Specifications. System Specifications (Reset Conditions) Signal Group Specifications SMBus Signal Group Specifications. BCLK Signal Quality Specifications. Ringback Specifications AGTL+ Asynchronous GTL+ Buffers Ringback Specifications Buffers. Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance Asynchronous GTL+ Signal Groups Overshoot/Undershoot Tolerance. INT-mPGA Processor Package Dimensions Package Dynamic Static Load Specifications Processor Mass. Processor Material Properties Listing Name Listing Number Signal Definitions. Processor Thermal Design Power. Power-On Configuration Option Pins Processor Information Format. Read Byte SMBus Packet Write Byte SMBus Packet Write Byte SMBus Packet Read Byte SMBus Packet Send Byte SMBus PacketReceive Byte SMBus Packet. SMBus Packet. SMBus Thermal Sensor Command Byte Assignments. Thermal Reference Register Values SMBus Thermal Sensor Status Register. SMBus Thermal Sensor Configuration Register SMBus Thermal Sensor Conversion Rate Registers Thermal Sensor SMBus Addressing
Contents
Memory Device SMBus Addressing .108 Power Signal Specifications .113
Revision History
Date Release January 2002 April 2002 2002 Revision -001 -002 -003 Initial datasheet release. Addition 2.40 Data Updated Figures Made PWRGOOD updates Description
Intel® XeonProcessor with Cache
Introduction
Intel® Xeonprocessor with cache based Intel® NetBurstmicroarchitecture, which operates significantly higher clock speeds delivers performance levels that significantly higher than previous generations IA-32 processors. While based Intel NetBurst micro-architecture, maintains tradition compatibility with IA-32 software. Intel NetBurst micro-architecture features begin with innovative techniques that enhance processor execution such Hyper Pipelined Technology, Rapid Execution Engine, Advanced Dynamic Execution, enhanced Floating Point Multimedia unit, Streaming SIMD Extensions (SSE2). Hyper Pipelined Technology doubles pipeline depth processor, allowing processor reach much higher core frequencies. Rapid Execution Engine allows integer ALUs processor twice core frequency, which allows many integer instructions execute half internal core clock period. Advanced Dynamic Execution improves speculative execution branch prediction internal processor. floating point multi-media units have been improved making registers bits wide adding separate register data movement. Finally, SSE2 adds instructions doubleprecision floating point, SIMD integer, memory management improvements video/ multimedia processing, secure transactions, visual internet applications. Also part Intel NetBurst micro-architecture, system caches Intel Xeon processor with cache provide tremendous throughput server workstation workloads. system provides high-bandwidth pipeline system memory I/O. quad-pumped running system clock making Gigabytes second (3,200 Megabytes second) data transfer rates possible. Execution Trace Cache level cache that stores approximately twelve thousand decoded micro-operations, which removes decoder latency from main execution path increases performance. Advanced Transfer Cache on-die level cache running speed processor core providing increased bandwidth over previous micro-architectures. addition Intel NetBurst micro-architecture, Intel Xeon processor with cache includes groundbreaking technology called Hyper-Threading technology, which enables multi-threaded software execute tasks parallel within processor resulting more efficient, simultaneous processor resources. Server applications realize increased performance from Hyper-Threading technology today, while workstation applications expected benefit from Hyper-Threading technology future through software processor evolution. combination Intel NetBurst micro-architecture Hyper-Threading technology delivers outstanding performance, throughput, headroom peak software workloads resulting faster response times improved scalability. Intel Xeon processor with cache intended high performance workstation server systems with processors single bus. processor supports both uni- dual-processor designs includes manageability features. Components manageability features include EEPROM Processor Information that accessible through SMBus interface. Processor Information includes information that relevant particular processor system which installed. Intel Xeon processor with cache packaged 603-pin interposer micro-PGA (INT-mPGA) package, utilizes surface mount socket with pins. Mechanical components used attaching thermal solutions baseboard should have high degree commonality with thermal solution components enabled Intel Xeon processor. Heatsinks retention mechanisms have been designed with manufacturability high priority. Hence, mechanical assembly completed from baseboard.
Intel® XeonProcessor with Cache
Intel Xeon processor with cache uses scalable system protocol referred "system bus" this document. processor system utilizes split-transaction, deferred reply protocol similar that introduced Pentium® processor system bus, compatible with Pentium processor system bus. Intel Xeon processor with cache system compatible with Intel Xeon processor system bus. system uses Source-Synchronous Transfer (SST) address data improve performance, transfers data four times clock data transfer rate). Along with data bus, address deliver addresses times clock referred `double-clocked' address bus. addition, Request Phase completes clock cycle. Working together, data address provide data bandwidth Gigabytes second. Finally, system also introduces transactions that used deliver interrupts. Signals system Assisted GTL+ (AGTL+) level voltages which fully described appropriate platform design guide (refer Section 1.3).
Terminology
symbol after signal name refers active signal, indicating signal asserted state when driven level. example, when RESET# low, reset been requested. Conversely, when high, nonmaskable interrupt occurred. case signals where name does imply active state describes part binary sequence (such address data), symbol implies that signal inverted. example, D[3:0] `HLHL' refers `A', D[3:0]# `LHLH' also refers High logic level, logic level). "System bus" refers interface between processor, system core logic (the chipset components), other agents. system multiprocessing interface processors, memory, I/O. this document, "system bus" used generic term Intel® Xeonprocessor with cache scalable system bus.
1.1.1
Processor Packaging Terminology
Commonly used terms explained here clarification:
603-pin socket connector which mates Intel® Xeonprocessor with
cache baseboard. 603-pin socket surface mount technology (SMT), zero insertion force (ZIF) socket utilizing solder ball attachment platform. 603-Pin Socket Design Guidelines details regarding this socket.
Flip Chip Ball Grid Array (FCBGA) Microprocessor packaging using "flip chip" design,
where processor attached substrate face-down better signal integrity, more efficient heat removal lower inductance.
Intel® Xeonprocessor with cache entire processor INT-mPGA
package, including processor core FC-BGA package, integrated heat spreader (IHS), interposer.
Integrated Heat Spreader (IHS) surface used attach heatsink other thermal
solution processor.
Interposer structure which processor core package pins mounted. Original Equipment Manufacturer. Processor core processor's execution engine. timing signal integrity
specifications pads processor core.
Intel® XeonProcessor with Cache
Processor Information (PIROM) SMBus accessible memory device located
processor interposer. This memory device contains information regarding processor's features. This device shared with scratch EEPROM. PIROM programmed during manufacturing write-protected. Section details PIROM.
Retention mechanism support components that mounted through baseboard
chassis provide mechanical retention processor heatsink assembly.
Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)
SMBus accessible memory device located processor interposer. This memory device used store information useful system management. Section details Scratch EEPROM.
SMBus System Management Bus. two-wire interface through which simple system
power management related devices communicate with rest system. based principals operation two-wire serial from Philips Semiconductor.
NOTE: "I2C two-wire communications bus/protocol developed Philips. SMBus subset bus/protocol developed Intel. Implementations bus/protocol SMBus bus/protocol require licenses from various entities, including Philips Electronics N.V. North American Philips Corporation."
State Data
data contained this document subject change. best information that Intel able provide publication date this document.
Intel® XeonProcessor with Cache
References
reader this specification should also familiar with material concepts presented following documents:.
Document AP-485, Intel® Processor Identification CPUID Instruction IA-32 Intel Architecture Software Developer's Manual Volume Basic Architecture Volume Instruction Reference Volume III: System Programming Guide Intel XeonTMProcessor Intel® Chipset Platform Design Guide Intel® XeonProcessor Thermal Design Guidelines -Pin Socket Design Guidelines Intel® XeonProcessor Specification Update CK00 Clock Synthesizer/Driver Design Guidelines DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines Dual Intel® Xeon Guidelines
Intel Order Number1 241618 245470 245471 245472 298252 298348 249672 249678 249206 249205 298646 298644 249679 298645 http://developer.intel.com2 http://developer.intel.com http://developer.intel.com http://developer.intel.com http://developer.intel.com http://www.sbs-forum.org/ smbus http://developer.intel.com http://support.intel.com/ support/processors/xeon
Processor Voltage Regulator Down (VRD) Design
ITP700 Debug Port Design Guide Intel® XeonProcessor with Cache System Compatibility Guidelines Intel® XeonProcessor with Cache Signal Integrity Models Intel® XeonProcessor with Cache Mechanical Models ProE* Format Intel® XeonProcessor with Cache Mechanical Models IGES* Format Intel® XeonProcessor with Cache Thermal Models (FloTherm* ICEPAK* format) Intel® XeonProcessor with Cache Core Boundary Scan Descriptor Language (BSDL) Model System Management Specification, Wired Management Design Guide Boxed Integration Notes
NOTES:
Contact your Intel representative latest revision documents without order numbers. signal integrity models IBIS format.
Intel® XeonProcessor with Cache
Electrical Specifications
System GTLREF
Most Intel® Xeonprocessor with cache system signals Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This signaling technology provides improved noise margins reduced ringing through voltage swings controlled edge rates. processor termination voltage level VCC, operating voltage processor core. termination voltage that determined processor core allows better voltage scaling processor system bus. Because speed improvements data address busses, signal integrity platform design methods become more critical than with previous processor families. System design guidelines detailed appropriate platform design guide (refer Section 1.3). AGTL+ inputs require reference voltage (GTLREF) which used receivers determine signal logical logical GTLREF must generated baseboard (See Table GTLREF specifications). Termination resistors provided processor silicon terminated core voltage (VCC). on-die termination resistors selectable feature enabled disabled ODTEN pin. agents, on-die termination enabled control reflections transmission line. middle agents, on-die termination must disabled. Intel chipsets will also provide on-die termination, thus eliminating need terminate baseboard most AGTL+ signals. Refer Section 2.12 details ODTEN resistor termination requirements. Note: Some AGTL+ signals include on-die termination must terminated baseboard. Table details regarding these signals. AGTL+ signals depend incident wave switching. Therefore timing calculations AGTL+ signals based flight time opposed capacitive deratings. Analog signal simulation system bus, including trace lengths, highly recommended when designing system. Please refer http://developer.intel.com obtain Intel® XeonProcessor with Cache Signal Integrity Models.
Power Ground Pins
clean on-chip power distribution, Intel Xeon processor with cache (power) (ground) inputs. pins must connected system power plane, while pins must connected system ground plane. processor pins must supplied voltage determined processor (Voltage pins.
Decoupling Guidelines
large number transistors high internal clock speeds, processor capable generating large average current swings between full power states. This cause voltages power planes below their minimum values bulk decoupling adequate. Larger bulk storage (CBULK), such electrolytic capacitors, supply current during longer lasting changes current demand component, such coming idle condition. Similarly, they storage well current when entering idle condition from running condition.
Intel® XeonProcessor with Cache
Care must taken baseboard design ensure that voltage provided processor remains within specifications listed Table Failure result timing violations reduced lifetime component. further information guidelines, refer appropriate platform design guidelines.
2.3.1
Decoupling
Regulator solutions need provide bulk capacitance with Effective Series Resistance (ESR) baseboard designer must ensure interconnect resistance from regulator pins) 603-pin socket. Bulk decoupling provided voltage regulation module (VRM) meet help meet large current swing requirements. remaining decoupling provided baseboard. power delivery path must capable delivering enough current while maintaining required tolerances (defined Table further information regarding power delivery, decoupling, layout guidelines, refer appropriate platform design guidelines.
2.3.2
System AGTL+ Decoupling
Intel® Xeonprocessor with cache integrates signal termination well part required high frequency decoupling capacitance processor package. However, additional high frequency capacitance must added baseboard properly decouple return currents from system bus. Bulk decoupling must also provided baseboard proper AGTL+ operation. Decoupling guidelines described appropriate platform design guidelines.
System Clock (BCLK[1:0]) Processor Clocking
BCLK[1:0] directly controls system interface speed well core frequency processor. previous generation processors, processor core frequency multiple BCLK[1:0] frequency. maximum processor ratio multiplier will during manufacturing. default setting will equal maximum speed processor. BCLK[1:0] inputs directly control operating speed system interface. processor core frequency configured during reset using values stored internally during manufacturing. stored value sets highest fraction which particular processor operate. Clock multiplying within processor provided internal PLL, which requires constant frequency BCLK[1:0] input with exceptions spread spectrum clocking. Processor specifications BCLK[1:0] inputs provided Table Table respectively. These specifications must while also meeting signal integrity requirements outlined Chapter 3.0. processor utilizes differential clock. Details regarding BCLK[1:0] driver specifications provided CK00 Clock Synthesizer/Driver Design Guidelines. Table contains supported fraction ratios their corresponding core frequencies.
Intel® XeonProcessor with Cache
Table
System Bus-to-Core Frequency Ratio
System Bus-to-Core Frequency Ratio 1/16 1/17 1/18 1/19 1/20 1/21 1/22 1/24 Core Frequency 1.60 1.70 1.80 1.90 2.10 2.20 2.40
2.4.1
Clock
system frequency maximum supported individual processor. BSEL[1:0] outputs used select system frequency. Table defines possible combinations signals frequency associated with each combination. frequency determined processor(s), chipset, clock synthesizer. system agents must operate same frequency. Individual processors will only operate their specified system clock frequency, (100 present generation processors). Baseboards designed Intel® Xeonprocessor employ system clock. these baseboards, BSEL[1:0] considered `reserved' processor socket. change required operation with Intel® Xeonprocessor with cache. Operation will default MHz.
Table System Clock Frequency Select Truth Table BSEL[1:0]
BSEL1 BSEL0 Clock Frequency Reserved Reserved Reserved
Filter
VCCA VCCIOPLL power sources required processor clock generator. This requirement identical that Intel Xeon processor. Since these PLLs analog nature, they require quiet power supplies minimum jitter. Jitter detrimental system: degrades external timings well internal core timings (i.e. maximum frequency). prevent this degradation, these supplies must pass filtered from VCC. typical filter topology shown Figure low-pass requirements, with input output measured across capacitor Figure follows:
gain pass band attenuation pass band (see drop next requirements)
Intel® XeonProcessor with Cache
attenuation from attenuation from core frequency
filter requirements illustrated Figure recommendations implementing filter refer appropriate platform design guidelines.
Figure Typical VCCIOPLL, VCCA VSSA Power Distribution
Trace 0.02 R-Trace
Socket
L1/L2
Processor interposer "pin" R-Socket VCCA R-Socket VSSA Processor
Baseboard that connects filter plane
R-Trace L1/L2
R-Socket
VCCIOPLL
Intel® XeonProcessor with Cache
Figure Phase Lock Loop (PLL) Filter Requirements
-0.5 forbidden zone
forbidden zone
passband
fpeak
fcore
high frequency band
NOTES: Diagram scale. specifications frequencies beyond fcore (core frequency). fpeak, existent, should less than 0.05 MHz.
2.5.1
Mixing Processors
Intel only supports those processor combinations operating with same system frequency, core frequency, settings, cache sizes. operating systems support multiple processors with mixed frequencies. Intel does support validate operation processors with different cache sizes. Mixing processors different steppings same model CPUID instruction) supported, outlined Intel® XeonProcessor Specification Update. Additional details provided AP-485, Intel Processor Identification CPUID Instruction application note. Unlike previous Intel® Xeonprocessors, Intel Xeon processor with cache does sample pins IGNNE#, LINT[0]/INTR, LINT[1]/NMI, A20M# establish core system ratio. Rather, processor runs tested frequency initial power-on. processor needs lower core frequency, must done when higher speed processor added system that contains lower frequency processor, system BIOS able effect change core system ratio.
Intel® XeonProcessor with Cache
Voltage Identification
specification processor defined this datasheet, supported power delivery solutions designed according Dual Intel® Xeon Processor Voltage Regulator Down (VRD) Design Guidelines, DC-DC Converter Design Guidelines, DC-DC Converter Design Guidelines. minimum voltage provided Table varies with processor frequency. This allows processors running higher frequency have relaxed minimum voltage specification. specifications have been such that voltage regulator design work with supported processor frequencies. Note that pins will drive valid correct logic levels when Intel® Xeonprocessor with cache provided with valid voltage applied SM_VCC pins. SM_VCC must correct stable prior enabling output that supplies VCC. Similarly, output must disabled before SM_VCC becomes invalid. Refer Figure details. processor uses five voltage identification pins, VID[4:0], support automatic selection processor voltages. Table specifies voltage level corresponding state VID[4:0]. this table refers high voltage refers voltage level. processor socket empty (VID[4:0] 11111), cannot supply voltage that requested, must disable voltage output. further details, Dual Intel® XeonProcessor Voltage Regulator Down (VRD) Design Guidelines, DC-DC Converter Design Guidelines DC-DC Converter Design Guidelines.
Intel® XeonProcessor with Cache
Table Voltage Identification Definition
Processor Pins VID4 VID3 VID2 VID1 VID0 VCC_VID output 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
2.6.1
Mixing Processors Different Voltages
Mixing processors operating with different settings (voltages) supported will validated Intel.
Intel® XeonProcessor with Cache
Reserved Unused Pins
Reserved pins must remain unconnected system baseboard. Connection these pins VCC, VSS, other signal (including another) result component malfunction incompatibility with future processors. Chapter listing processor location Reserved pins. reliable operation, unused inputs bidirectional signals should always connected appropriate signal level. system-level design, on-die termination been included processor allow signal termination accomplished processor silicon. Most unused AGTL+ inputs should left connects, AGTL+ termination provided processor silicon. However, Table details AGTL+ signals that include on-die termination. Unused active high inputs should connected through resistor ground (VSS). Unused outputs left unconnected, however this interfere with some functions, complicate debug probing, prevent boundary scan testing. resistor must used when tying bidirectional signals power ground. When tying signal power ground, resistor will also allow system testability. unused AGTL+ input signals, pull-up resistors same value on-die termination resistors (RTT). Table TAP, Asynchronous GTL+ inputs, Asynchronous GTL+ outputs include on-die termination. Inputs used outputs must terminated baseboard. Unused outputs terminated baseboard left unconnected. Note that leaving unused outputs unterminated interfere with some functions, complicate debug probing, prevent boundary scan testing. Signal termination these signal types discussed ITP700 Debug Port Design Guide. TESTHI[6:0] pins should individually connected pull-up resistor which matches trace impedance within TESTHI[3:0] TESTHI[6:5] tied together pulled with single resistor desired. However, utilization boundary scan test will functional these pins connected together. TESTHI4 must always pulled independently from other TESTHI pins. optimum noise margin, pull-up resistor values used TESTHI[6:0] pins should have resistance value within percent impedance baseboard transmission line traces. example, trace impedance then pull-up resistor value between should used. TESTHI[6:0] termination recommendations provided Intel® XeonProcessor Datasheet also suitable Intel® Xeonprocessor with cache. However, Intel recommends designs designs undergoing design updates follow trace impedance matching termination guidelines outlined this section.
System Signal Groups
order simplify following discussion, system signals have been combined into groups buffer type. AGTL+ input signals have differential input buffers, which GTLREF reference level. this document, term "AGTL+ Input" refers AGTL+ input group well AGTL+ group when receiving. Similarly, "AGTL+ Output" refers AGTL+ output group well AGTL+ group when driving. With implementation source synchronous data comes need specify sets timing parameters. common clock signals whose timings specified with respect rising edge BCLK0 (ADS#, HIT#, HITM#, etc.) second source synchronous signals which relative their respective strobe lines (data address) well
Intel® XeonProcessor with Cache
rising edge BCLK0. Asynchronous signals still present (A20M#, IGNNE#, etc.) become active time during clock cycle. Table identifies which signals common clock, source synchronous asynchronous.
Table System Signal Groups
Signal Group AGTL+ Common Clock Input Type Synchronous BCLK[1:0] Signals BPRI#, BR[3:1]#3,4, DEFER#, RESET#4, RS[2:0]#, RSP#, TRDY# ADS#, AP[1:0]#, BINIT#7, BNR#7, BPM[5:0]#2, BR0#2, DBSY#, DP[3:0]#, DRDY#, HIT#7, HITM#7, LOCK#, MCERR#7
AGTL+ Common Clock
Synchronous BCLK[1:0]
Signals
REQ[4:0]#,A[16:3]#6
Associated Strobe
ADSTB0# ADSTB1# DSTBP0#, DSTBN0# DSTBP1#, DSTBN1# DSTBP2#, DSTBN2# DSTBP3#, DSTBN3#
AGTL+ Source Synchronous
Synchronous assoc. strobe
A[35:17]#
D[15:0]#, DBI0# D[31:16]#, DBI1# D[47:32]#, DBI2# D[63:48]#, DBI3#
AGTL+ Strobes Asynchronous GTL+ Input Asynchronous GTL+ Output System Clock Input Output
Synchronous BCLK[1:0] Asynchronous Asynchronous Clock Synchronous Synchronous Synchronous SM_CLK
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#5, IGNNE#5, INIT#6, LINT0/INTR5, LINT1/NMI5, SMI#6, SLP#, STPCLK# FERR#, IERR#, THERMTRIP#, PROCHOT# BCLK1, BCLK0 TCK, TDI, TMS, TRST# SM_EP_A[2:0], SM_TS_A[1:0], SM_DAT, SM_CLK, SM_ALERT#, SM_WP BSEL[1:0], COMP[1:0], GTLREF, ODTEN, Reserved, SKTOCC#, TESTHI[6:0],VID[4:0], VCC, SM_VCC9, VCCA, VCCIOPLL, VSSA, VSS, VCCSENSE, VSSSENSE, PWRGOOD
SMBus Interface
Power/Other
Power/Other
NOTES: Refer Section signal descriptions. These signal groups terminated processor. Refer ITP700 Debug Port Design Guide corresponding Design Guide termination requirements further details. Intel® Xeonprocessor with cache utilizes only BR0# BR1#. BR2# BR3# driven processor must terminated VCC. additional details regarding BR[3:0]# signals, Section Section appropriate Platform Design Guidelines. These signals have on-die termination. Refer corresponding Platform Design Guidelines termination requirements. Note that Reset initialization function these pins software function Intel® Xeonprocessor with cache. value these pins during active-to-inactive edge RESET# determine processor configuration options. Section details. These signals driven simultaneously multiple agents (wired-or). These signals terminated processor's on-die termination. However, some signals this group include termination processor interposer. Section details.
Intel® XeonProcessor with Cache
SM_Vcc required correct logic operation Intel® Xeonprocessor with cache. Refer Figure details.
Asynchronous GTL+ Signals
Intel® Xeonprocessor with cache does utilize CMOS voltage levels signals that connect processor silicon. result, legacy input signals such A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# other non-AGTL+ signals IERR#, THERMTRIP# PROCHOT# utilize GTL+ output buffers. these asynchronous GTL+ signals follow same requirements AGTL+ signals, however outputs driven high (during logical 0to-1 transition) processor (the major difference between GTL+ AGTL+). Asynchronous GTL+ signals have setup hold time specifications relation BCLK[1:0]. However, asynchronous GTL+ signals required asserted least BCLKs order processor recognize them. Table Table specifications asynchronous GTL+ signal groups. SMBus signals derived from components mounted processor interposer along with processor silicon. required SM_VCC these signals volts. Section further details.
2.10
Maximum Ratings
Table lists processor's maximum environmental stress ratings. Functional operation absolute maximum minimum neither implied guaranteed. processor should receive clock while subjected these conditions. Functional operating parameters listed tables. Extended exposure maximum ratings affect device reliability. Furthermore, although processor contains protective circuitry resist damage from static electric discharge, should always take precautions avoid high static voltages electric fields.
Table Processor Absolute Maximum Ratings
Symbol TSTORAGE VinAGTL+ VinGTL+ VinSMBus IVID Parameter Processor storage temperature processor supply voltage with respect AGTL+ buffer input voltage with respect Async GTL+ buffer input voltage with respect SMBus buffer input voltage with respect current -0.3 -0.1 -0.1 -0.3 1.75 1.75 1.75 Unit Notes
This rating applies processor. Contact Intel storage requirements excess year.
Intel® XeonProcessor with Cache
2.11
Processor Specifications
processor specifications this section defined processor core (pads) unless noted otherwise. Section processor listings Section signal definitions. voltage current specifications versions processor detailed Table platform planning refer Figure Notice that graphs include Thermal Design Power (TDP) associated with maximum current levels. specifications AGTL+ signals listed Table system clock signal group SMBus interface signal group detailed Table Table respectively. specifications these signal groups listed Table Table through Table list processor specifications valid only while meeting specifications case temperature (TCASE specified Chapter 6.0), clock frequency, input voltages. Care should taken read notes associated with each parameter.
Intel® XeonProcessor with Cache
Table Voltage Current Specifications
Symbol Parameter Core Freq Intel Xeon processor with cache SMBus supply voltage Intel Xeon processor with cache power pins SMBus power supply GTLREF pins Stop-Grant/Sleep active SM_VCC freq. ICC_PLL ICC_SMBus ICC_GTLREF ISGnt/ISLP ITCC freq freq. freq freq freq 100.0 1.361 1.357 1.352 1.347 3.135 3.30 Refer Figure 1.465 1.463 1.46 1.458 3.465 42.4 45.3 48.1 122.5 18.6 18.6 Unit Notes1
NOTES: Unless otherwise noted, specifications this table apply processors. These voltages targets only. variable voltage source should exist systems event that different voltage required. Section Table more information. voltage specification requirements measured across vias platform VCC_SENSE VSS_SENSE pins close socket with bandwidth oscilloscope, maximum probe capacitance, milliohm minimum impedance. maximum length ground wire probe should less than Ensure external noise from system coupled scope probe. processor should subjected static level that exceeds VCC_MAX associated with particular current. Moreover, should never exceed VCC_VID. Failure adhere this specification shorten processor lifetime. Maximum current defined VCC_MAX. current specified also AutoHALT State. maximum instantaneous current processor will draw while thermal control circuit active indicated assertion PROCHOT#. SM_VCC required correct operation processor logic. Refer Figure details. This specification applies power pins VCCA VCCIOPLL. Section details. This parameter based design characterization tested 10.This specification applies each GTLREF pin. loadlines specify voltage limits measured VCC_SENSE VSS_SENSE pins. Voltage regulation feedback voltage regulator circuits must taken from processor pins. 12.Adherence this loadline specification required ensure reliable processor operation.
Intel® XeonProcessor with Cache
Figure Intel® XeonProcessor with Cache Voltage-Current Projections
1.51 Maximum Processor Voltage (VDC) 1.50 1.49 1.48 1.47 1.46 1.45 1.44 Processor Current
Table System Differential BCLK Specifications
Symbol VCROSS VRBM Parameter Input Voltage Input High Voltage Crossing Voltage Overshoot Undershoot Ringback Margin Threshold Region 0.660 0.45 0.300 0.200 VCROSS 0.100 0.710 0.30 0.55 0.300 VCROSS 0.100 Unit Figure Notes
NOTES:. Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Crossing Voltage defined absolute voltage where rising edge BCLK0 equal falling edge BCLK1. voltages observed processor. Overshoot defined absolute value maximum voltage allowed above level. Undershoot defined absolute value maximum voltage allowed below level. Ringback Margin defined absolute voltage difference between maximum Rising Edge Ringback maximum Falling Edge Ringback.
Intel® XeonProcessor with Cache
Threshold Region defined region centered about crossing voltage which differential receiver switches. includes input threshold hysteresis. referred these specifications refers instantaneous VCC.
Table AGTL+ Signal Group Specifications
Symbol Parameter Input High Voltage Input Voltage Output High Voltage Output Current Leakage High Leakage Buffer Resistance 1.10 GTLREF 0.90 GTLREF (0.50 RTT_min RON_min)
Unit
Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. defined minimum voltage level receiving agent that will interpreted logical high value. defined maximum voltage level receiving agent that will interpreted logical value. experience excursions above VCC. However, input signal drivers must comply with signal quality specifications Chapter 3.0. Refer Intel® XeonProcessor with Cache Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. VOL_MAX 0.450 guaranteed when driving into test load indicated Figure with enabled. Leakage with held Leakage with held VCC.
Table PWRGOOD Signal Group Specifications
Symbol VHYS VTVOH Parameter Input Hysteresis input high threshold voltage input high threshold voltage Output High Voltage Output Current Leakage High Leakage Buffer Resistance 8.75 Unit Notes
(VCC VHYS_MIN) (VCC VHYS_MAX) (VCC VHYS_MAX) (VCC VHYS_MIN) 13.75
NOTES:. Unless otherwise noted, specifications this table apply processor frequencies cache sizes. outputs open drain signal group must meet system signal quality specification Chapter 3.0. Refer Intel® XeonProcessor with Cache Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. maximum output current based maximum current handling capability buffer specified into test load. VOL_MAX 0.300V guaranteed when driving test load.
Intel® XeonProcessor with Cache
VHYS represents amount hysteresis, nominally centered about 0.5*VCC, inputs. Leakage with held 10.Leakage with held VCC.
Table Asynchronous GTL+ Signal Group Specifications
Symbol Parameter Input High Voltage Input Voltage Output High Voltage Output Current Leakage High Leakage Buffer Resistance 1.10 GTLREF 0.90 GTLREF Unit
Notes1,
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. outputs open drain defined minimum voltage level receiving agent that will interpreted logical high value. defined maximum voltage level receiving agent that will interpreted logical value. experience excursions above VCC. However, input signal drivers must comply with signal quality specifications Chapter 3.0. Refer Intel® XeonProcessor with Cache Signal Integrity Models characteristics. referred these specifications refers instantaneous VCC. maximum output current based maximum current handling capability buffer specified into test load. VOL_MAX 0.450 guaranteed when driving into test load indicated Figure with enabled. Leakage with held Leakage with held VCC.
Table SMBus Signal Group Specifications
Symbol CSMB Parameter Input Voltage Input High Voltage Output Voltage Output Current Input Leakage Current Output Leakage Current SMBus Capacitance -0.30 0.70 SM_VCC 0.30 SM_VCC 3.465 0.400 Unit Notes
15.0
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. These parameters based design characterization tested. specifications SMBus signal group measured processor pins. Platform designers need this value calculate maximum loading SMBus determine maximum rise fall times SMBus signals.
Intel® XeonProcessor with Cache
2.12
AGTL+ System Specifications
Routing topologies dependent number processors supported chipset used design. Please refer appropriate platform design guidelines. most cases, termination resistors required these integrated into processor. Table details which AGTL+ signals include on-die termination.The termination resistors enabled disabled through ODTEN pin. enable termination, this should pulled through resistor disable termination, this should pulled down through resistor. optimum noise margin, pull-up pull-down resistor values used ODTEN should have resistance value within percent impedance baseboard transmission line traces. example, trace impedance then value between should used. processor's on-die termination must enabled agent only. Please refer Table termination resistor values. more details platform design appropriate platform design guidelines. Valid high levels determined input buffers comparing with reference voltage called GTLREF. Table lists GTLREF specifications. AGTL+ reference voltage (GTLREF) should generated baseboard using high precision voltage divider circuits. important that baseboard impedance held specified tolerance, that intrinsic trace capacitance AGTL+ signal group traces known well-controlled. more details platform design appropriate platform design guidelines.
Table AGTL+ Voltage Definitions
Symbol GTLREF Design COMP[1:0] COMP[1:0] Design Parameter Reference Voltage Termination Resistance Termination Resistance COMP Resistance COMP Resistance 42.77 49.55 43.2 43.63 50.45 Units
Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies. tolerances this specification have been stated generically enable system designer calculate minimum values across range VCC. GTLREF generated from baseboard voltage divider percent resistors. Refer appropriate platform design guidelines implementation details. on-die termination resistance measured from AGTL+ output driver. Refer Intel® XeonProcessor with Cache Signal Integrity Models characteristics. COMP resistors pull downs provided baseboard with tolerance. appropriate platform design guidelines implementation details. referred these specifications refers instantaneous VCC. COMP resistance value varies platform. Refer appropriate platform design guideline recommended COMP resistance value. values COMP noted `New Designs' apply designs that optimized Intel® Xeonprocessor with cache. Refer appropriate platform design guideline recommended COMP resistance value.
Intel® XeonProcessor with Cache
2.13
System Specifications
processor system timings specified this section defined processor core (pads). Section listing signal definitions. Table through Table list specifications associated with processor system bus. AGTL+ timings referenced GTLREF both logic levels unless otherwise specified. timings specified this section should used conjunction with signal integrity models provided Intel. These signal integrity models, which include package information, available Intel® Xeonprocessor with cache IBIS format. AGTL+ layout guidelines also available appropriate platform design guidelines. Note: Care should taken read notes associated with particular timing parameter
Table System Differential Clock Specifications
Parameter System Clock Frequency BCLK[1:0] Period BCLK[1:0] Period Stability BCLK[1:0] Pulse High Time BCLK[1:0] Pulse Time BCLK[1:0] Rise Time BCLK[1:0] Fall Time 10.00 3.94 3.94 100.0 10.20 6.12 6.12 Unit Figure Notes
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. processor core clock frequency derived from BCLK. period specified here average period. given period vary from this specification governed period stability specification (T2). clock jitter specification, refer CK00 Clock Synthesizer/Driver Design Guidelines. this context, period stability defined worst case timing difference between successive crossover voltages. other words, largest absolute difference between adjacent clock periods must less than period stability. Slew rate measured between points clock swing VH).
Table System Common Clock Specifications
Parameter T10: Common Clock Output Valid Delay T11: Common Clock Input Setup Time T12: Common Clock Input Hold Time T13: RESET# Pulse Width 0.12 1.00 1.27 0.65 0.40 10.00 Unit Figure Notes1,
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization. common clock timings AGTL+ signals referenced Crossing Voltage (VCROSS) BCLK[1:0] rising edge BCLK0. common clock AGTL+ signal timings referenced GTLREF processor core.
Intel® XeonProcessor with Cache
Valid delay timings these signals specified into test circuit described Figure with GTLREF Specification minimum swing defined between AGTL+ VIL_MAX VIH_MIN. This assumes edge rate V/nS V/nS. RESET# asserted (active) asynchronously, must deasserted synchronously. This should measured after BCLK[1:0] become stable. Maximum specification applies only while PWRGOOD asserted.
Table System Source Synchronous Specifications
Parameter T20: Source Sync. Output Valid Delay (first data/ address only) T21: TVBD Source Sync. Data Output Valid Before Data Strobe T22: TVAD Source Sync. Data Output Valid After Data Strobe T23: TVBA Source Sync. Address Output Valid Before Address Strobe T24: TVAA Source Sync. Address Output Valid After Address Strobe T25: TSUSS Source Sync. Input Setup Time T26: THSS Source Sync. Input Hold Time T27: TSUCC Source Sync. Input Setup Time BCLK T28: TFASS First Address Strobe Second Address Strobe T29: TFDSS: First Data Strobe Subsequent Strobes T30: Data Strobe (DSTBN#) Output Valid Delay T31: Address Strobe Output Valid Delay 8.80 2.27 0.20 0.85 0.85 1.88 1.88 0.21 0.21 0.65 1.30 Unit BCLKs Figure Notes
BCLKs
10.20 4.23
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization. source synchronous timings referenced their associated strobe GTLREF. Source synchronous data signals referenced falling edge their associated data strobe. Source synchronous address signals referenced rising falling edge their associated address strobe. source synchronous AGTL+ signal timings referenced GTLREF processor core. Unless otherwise noted, these specifications apply both data address timings. Valid delay timings these signals specified into test circuit described Figure with GTLREF Specification minimum swing defined between AGTL+ VIL_MAX VIH_MIN. This assumes edge rate V/nS V/nS. source synchronous signals must meet specified setup time BCLK well setup time each respective strobe. This specification represents minimum time data address will valid before strobe. Refer appropriate platform design guidelines more information definitions these specifications. This specification represents minimum time data address will valid after strobe. Refer appropriate platform design guidelines more information definitions these specifications. 10.The rising edge ADSTB# must come approximately BCLK period after falling edge ADSTB#. this timing parameter, second, third, last data strobes respectively. 12.The second data strobe (the falling edge DSTBn#) must come approximately BCLK period (2.5 after first falling edge DSTBp#. third data strobe (the falling edge DSTBp#) must come
Intel® XeonProcessor with Cache
approximately BCLK period after first falling edge DSTBp#. last data strobe (the falling edge DSTBn#) must come approximately BCLK period (7.5 after first falling edge DSTBp#. 13.This specification applies only DSTBN[3:0]# measured second falling edge strobe. 14.This specification reflects typical value, minimum maximum.
Table Miscellaneous Signals+ Specifications
Parameter T35: Async GTL+ input pulse width T36: PWRGOOD RESET# de-assertion time T37: PWRGOOD inactive pulse width T38: PROCHOT# pulse width T39: THERMTRIP# Removal Unit BCLKs BCLKs Figure Notes
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. timings Asynchronous GTL+ signals referenced BCLK0 rising edge Crossing Voltage (VCROSS). Asynchronous GTL+ signal timings referenced GTLREF. These signals driven asynchronously. Refer Section additional timing requirements entering leaving power states. Refer PWRGOOD signal definition Section more detail information behavior signal. Length assertion PROCHOT# does equal internal clock modulation time. Time allocated after assertion PROCHOT# processor complete current instruction execution.
Table System Specifications (Reset Conditions)
Parameter T45: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Setup Time T46: Reset Configuration Signals (A[31:3]#, BR[3:0]#, INIT#, SMI#) Hold Time Before de-assertion RESET# After clock that de-asserts RESET#. Unit BCLKs BCLKs Figure Notes
Table Signal Group Specifications
Parameter T55: Period T56: Rise Time T57: Fall Time T58: TMS, Rise Time T59: TMS, Fall Time T61: TDI, Setup Time T62: TDI, Hold Time T63: Clock Output Delay T64: TRST# Assert Time 60.0 Unit TTCK Figure Notes 1,2,3,9
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. 100% tested. Specified design characterization.
Intel® XeonProcessor with Cache
timings signals referenced signal processor pins. signal timings (TMS, TDI, etc) referenced processor pins. Rise fall times measured from points signal swing. Referenced rising edge TCK. Referenced falling edge TCK. Specification minimum swing defined between 80%. This assumes minimum edge rate V/nS. TRST# must held asserted periods guaranteed that recognized processor. recommended that asserted while TRST# being deasserted.
Table SMBus Signal Group Specifications
Parameter T70: SM_CLK Frequency T71: SM_CLK Period T72: SM_CLK High Time T73: SM_CLK Time T74: SMBus Rise Time T75: SMBus Fall Time T76: SMBus Output Valid Delay T77: SMBus Input Setup Time T78: SMBus Input Hold Time T79: Free Time T80: Hold Time after Repeated Start Condition T81: Repeated Start Condition Setup Time T82: Stop Condition Setup Time 0.02 0.02 Unit Figure Notes
Unless otherwise noted, specifications this table apply processor frequencies cache sizes. These parameters based design characterization tested. timings SMBus signals referenced VIL_MAX VIL_MIN measured processor pins. Refer Figure Minimum time allowed between request cycles. Rise time measured from (VIL_MAX 0.15V) (VIH_MIN 0.15V). Fall time measured from (0.9 SM_VCC) (VIL_MAX 0.15V). parameters specified Table Following write transaction, internal device write cycle time 10ms must allowed before starting next transaction.
2.14
Processor Timing Waveforms
following figures used conjunction with timing tables, Table through Table Note: Figure through Figure following apply: common clock timings AGTL+ signals referenced Crossing Voltage (VCROSS) BCLK[1:0] rising edge BCLK0. common clock AGTL+ signal timings referenced GTLREF processor core (pads). source synchronous timings AGTL+ signals referenced their associated strobe (address data) GTLREF. Source synchronous data signals referenced falling edge their associated data strobe. Source synchronous address signals referenced
Intel® XeonProcessor with Cache
rising falling edge their associated address strobe. source synchronous AGTL+ signal timings referenced GTLREF processor core (pads). timings AGTL+ strobe signals referenced BCLK[1:0] VCROSS. AGTL+ strobe signal timings referenced GTLREF processor core (pads). Timing signals referenced signal processor pins. signal timings (TMS, TDI, etc.) referenced processor core (pads). timings SMBus signals referenced SM_CLK signal SM_VCC processor pins. SMBus signal timings (SM_DAT, SM_ALERT#, etc.) referenced VIL_MAX VIL_MIN processor pins.
Figure Electrical Test Circuit
ohms, d=420mils, So=169ps/in
Rload ohms 2.4nH 1.2pF Timings specified pad.
Figure Clock Waveform
T56, (Rise Time) T57, (Fall Time) (Period)
rise fall times, measured between 20%to 80%points waveform. referenced 0.5* Vcc.
Intel® XeonProcessor with Cache
Figure Differential Clock Waveform
Overshoot BCLK1 Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 Undershoot
(BCLK[1:0] period) BCLK[1:0] Period stability (not shown) (BCLK[1:0] pulse high time) (BCLK[1:0] pulse time) BCLK[1:0] rise time through threshold region BCLK[1:0] fall time through threshold region
Figure System Common Clock Valid Delay Timing Waveform
BCLK1 BCLK0
Common Clock Signal driver) Common Clock Signal receiver)
valid valid
valid
T10: Common Clock Output Valid Delay T11: Common Clock Input Setup T12: Common Clock Input Hold Time
Intel® XeonProcessor with Cache
Figure System Source Synchronous (Address) Timing Waveform
BCLK BCLK BCLK
BCLK1 BCLK0 ADSTB# driver)
valid valid
driver)
ADSTB# receiver)
receiver)
valid
valid
T23: Source Sync. Address Output Valid Before Address Strobe T24: Source Sync. Address Output Valid After Address Strobe T27: Source Sync. Input Setup BCLK T26: Source Sync. Input Hold Time T25: Source Sync. Input Setup Time T28: First Address Strobe Second Address Strobe T20: Source Sync. Output Valid Delay T31: Address Strobe Output Valid Delay
Intel® XeonProcessor with Cache
Figure System Source Synchronous (Data) Timing Waveform
BCLK1 BCLK0 DSTBp# driver)
BCLK BCLK BCLK
DSTBn# driver)
driver)
DSTBp# receiver)
DSTBn# receiver)
receiver)
T21: Source Sync. Data Output Valid Delay Before Data Strobe T22: Source Sync. Data Output Valid Delay After Data Strobe T27: Source Sync. Setup Time BCLK T30: Source Sync. Data Strobe (DSTBN#) Output Valid Delay T25: Source Sync. Input Setup Time T26: Source Sync. Input Hold Time T29: First Data Strobe Subsequent Strobes T20: Source Sync. Data Output Valid Delay
Intel® XeonProcessor with Cache
Figure System Reset Configuration Timing Waveform
BLCK RESET#
Configuration (A[31:3]#, BR0#, SMI#, INIT#) Safe Valid
Configuration (A[31:3]#, BR0#, SMI#, INIT#) Valid
(RESET# Pluse Width) (Reset Configuration Signals (A[14:5]#, BR0#, SMI#, INIT#) Setup Time) (Reset Configuration signals (A[14:5]#, BR0#, SMI#, INIT#) Hold Time)
Figure Power-On Reset Configuration Timing Waveform
BLCK
PWRGOOD RESET# (PWRGOOD Inactive Pluse Width) (PWRGOOD RESET# de-assertion time)
Intel® XeonProcessor with Cache
Figure Valid Delay Timing Waveform
Signal
Valid
(Valid Time) (Setup Time) (Hold Time)
Figure Test Reset (TRST#), Async GTL+ Input, PROCHOT# Timing Waveform
(TRST# Pulse Width), V=0.5*Vcc (PROCHOT# Pulse Width), V=GTLREF
Figure THERMTRIP# Timing
THERMTRIP# Power Down Sequence
THERMTRIP#
seconds Note: THERMTRIP# undefined when RESET active
Intel® XeonProcessor with Cache
Figure SMBus Timing Waveform
HD;STA
HD;STA
HD;DAT
HIGH
SU;DAT
SU;STA
SU;STO
Data START START
STOP
STOP
HIGH
HD;STA HD;DAT
SU;STA SU;STD
SU;DAT
Figure SMBus Valid Delay Timing Waveform
SM_CLK
DATA VALID SM_DAT
DATA OUTPUT
Intel® XeonProcessor with Cache
Figure Example VDC/SM_VCC Sequencing
T0=95% volt level VDC/SM_VCC PWR_OK OUTEN VID_OUT PWRGD Processor PWRGOOD Processor RESET 1ms<T36<10ms VID[4:0] 10mS 10ms 100ms
Power
PWRGD PWRGOOD
OUTEN
Processor
SM_VCC PWR_OK
Power Supply
volt level VDC/SM_VCC
Power Down
PWROK
OUTEN
Power Down Warning
Intel® XeonProcessor with Cache
System Signal Quality Specifications
This section documents signal quality metrics used derive topology routing guidelines through simulation. specifications made processor core (pad measurements). Source synchronous data transfer requires clean reception data signals their associated strobes. Ringing below receiver thresholds, non-monotonic signal edges, excessive voltage swing will adversely affect system timings. Ringback signal non-monotinicity cannot tolerated since these phenomena inadvertently advance receiver state machines. Excessive signal swings (overshoot undershoot) detrimental silicon gate oxide integrity, cause device failure absolute voltage limits exceeded. Additionally, overshoot undershoot degrade timing build inter-symbol interference (ISI) effects. these reasons, crucial that designer assure acceptable signal quality across systematic variations encountered volume manufacturing. Specifications signal quality measurements processor core only only observable through simulation. same true system timing specifications Section 2.13. Therefore, proper simulation processor system only means verify proper timing signal quality metrics.
System Clock (BCLK) Signal Quality Specifications Measurement Guidelines
Table describes signal quality specifications processor pads processor system clock (BCLK) signals. Figure describes signal quality waveform system clock processor pads.
Table BCLK Signal Quality Specifications
Parameter BCLK[1:0] Overshoot BCLK[1:0] Undershoot BCLK[1:0] Ringback Margin BCLK[1:0] Threshold Region 0.20 0.30 0.30 0.10 Unit Figure Notes
NOTES: Unless otherwise noted, specifications this table apply processor frequencies cache sizes. rising falling edge ringback voltage specified minimum (rising) maximum (falling) absolute voltage BCLK signal back after passing (rising) (falling) voltage limits. This specification absolute value.
Intel® XeonProcessor with Cache
Figure BCLK[1:0] Signal Integrity Waveform
Overshoot BCLK1 Rising Edge Ringback Threshold Region Crossing Voltage Crossing Voltage Ringback Margin Falling Edge Ringback, BCLK0 Undershoot
System Signal Quality Specifications Measurement Guidelines
Many scenarios have been simulated generate AGTL+ layout guidelines which available appropriate platform design guidelines. Table provides signal quality specifications processor signals simulating signal quality processor pads. Maximum allowable overshoot undershoot specifications given duration time detailed Table through Table Figure shows system ringback tolerance lowto-high transitions Figure shows ringback tolerance high-to-low transitions.
Table Ringback Specifications AGTL+ Asynchronous GTL+ Buffers
Signal Group AGTL+, Asynch GTL+ AGTL+, Asynch GTL+ Transition Maximum Ringback (with Input Diodes Present) GTLREF 0.100*GTLREF GTLREF 0.100*GTLREF Unit Figure Notes
NOTES: signal integrity specifications measured processor core (pads). Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Specifications edge rate V/nS receiver. values specified design characterization. Please Section maximum allowable overshoot. Ringback between GTLREF GTLREF supported. Intel recommends simulations exceed ringback value GTLREF allow margin other sources system noise
Intel® XeonProcessor with Cache
Table Ringback Specifications Buffers
Signal Group PWRGOO PWRGOO Maximum Ringback (with Input Diodes Present) Threshold Notes
Transition
Unit
Figure
VT+(max) VT-(max)
VT+(max)
VT-(min) VT+(min)
VT-(min)
NOTES: signal integrity specifications measured processor core (pads). Unless otherwise noted, specifications this table apply processor frequencies cache sizes. Specifications edge rate V/nS. values specified design characterization. Please section maximum allowable overshoot.
Figure Low-to-High System Receiver Ringback Tolerance AGTL+ Asynchronous GTL+ Buffers
+10% GTLREF -10%
Noise Margin
Intel® XeonProcessor with Cache
Figure High-to-Low System Receiver Ringback Tolerance AGTL+ Asynchronous GTL+ Buffers
+10% GTLREF -10%
Noise Margin
Figure Low-to-High System Receiver Ringback Tolerance PWRGOOD Buffers
Threshold Region switch receiver logic
(max) (min) (max)
Allowable Ringback
Intel® XeonProcessor with Cache
Figure High-to-Low System Receiver Ringback Tolerance PWRGOOD Buffers
Allowable Ringback
(min) (max) (min)
Threshold Region switch receiver logic
Intel® XeonProcessor with Cache
System Signal Quality Specifications Measurement Guidelines
Overshoot/Undershoot Guidelines
Overshoot undershoot) absolute value maximum voltage above below VSS. overshoot/undershoot specifications limit transitions beyond fast signal edge rates. processor damaged single and/or repeated overshoot undershoot events input, output, buffer charge large enough (i.e., over/undershoot great enough). Determining impact overshoot/undershoot condition requires knowledge magnitude, pulse direction, activity factor (AF). Permanent damage processor likely result excessive overshoot/undershoot. When performing simulations determine impact overshoot undershoot, diodes must properly characterized. protection diodes voltage clamps will provide overshoot undershoot protection. diodes modeled within Intel's signal integrity models clamp undershoot overshoot will yield correct simulation results. other signal integrity models being used characterize processor system bus, care must taken ensure that models clamp extreme voltage levels. Intel's signal integrity models also contain capacitance characterization. Therefore, removing diodes from signal integrity model will impact results yield excessive overshoot/undershoot.
3.3.1
3.3.2
Overshoot/Undershoot Magnitude
Magnitude describes maximum potential difference between signal voltage reference level (VSS). important note that overshoot undershoot conditions separate their impact must determined independently. Overshoot/undershoot magnitude levels must observe absolute maximum specifications listed Table through Table These specifications must violated time regardless activity system state. Within these specifications threshold levels that define different allowed pulse duration. Provided that magnitude overshoot/undershoot within absolute maximum specifications, pulse magnitude, duration activity factor must used determine overshoot/undershoot pulse within specifications.
3.3.3
Overshoot/Undershoot Pulse Duration
Pulse duration describes total time overshoot/undershoot event exceeds overshoot/ undershoot reference voltage (VCC). total time could encompass several oscillations above reference voltage. Multiple overshoot/undershoot pulses within single overshoot/undershoot event need measured determine total pulse duration. Note Oscillations below reference voltage subtracted from total overshoot/ undershoot pulse duration.
Intel® XeonProcessor with Cache
3.3.4
Activity Factor
Activity Factor (AF) describes frequency overshoot undershoot) occurrence relative clock. Since highest frequency assertion common clock signal every other clock, indicates that specific overshoot undershoot) waveform occurs every other clock cycle. Thus, 0.01 indicates that specific overshoot undershoot) waveform occurs time every clock cycles. source synchronous signals (address, data, associated strobes), activity factor reference strobe edge. highest frequency assertion source synchronous signal every active edge associated strobe. indicates that specific overshoot undershoot) waveform occurs every strobe cycle. specifications provided Table through Table show maximum pulse duration allowed given overshoot/undershoot magnitude specific activity factor. Each table entry independent others, meaning that pulse duration reflects existence overshoot/ undershoot events that magnitude ONLY. platform with overshoot/undershoot that just meets pulse duration specific magnitude where means that there other overshoot/undershoot events, even lesser magnitude (note that then event occurs times other events occur).
NOTE: Activity factor common clock AGTL+ signals referenced BCLK[1:0] frequency. Activity factor source synchronous (2x) signals referenced ADSTB[1:0]#. Activity factor source synchronous (4x) signals referenced DSTBP[3:0]#and DSTBN[3:0]#.
3.3.5
Reading Overshoot/Undershoot Specification Tables
processor overshoot/undershoot specification simple single value. Instead, many factors needed determine what overshoot/undershoot specification addition magnitude overshoot, following parameters must also known: width overshoot activity factor (AF). determine allowed overshoot particular overshoot event, following must done: Determine signal group that particular signal falls into. AGTL+ signals operating source synchronous domain, Table should used. AGTL+ signals operating source synchronous domain, Table should used. signal AGTL+ signal operating common clock domain, Table should used. Finally, other signals residing domain (asynchronous GTL+, TAP, etc.), Table should used. Determine magnitude overshoot undershoot (relative VSS). Determine activity factor (how often does this overshoot occurs). Next, from appropriate specification table, determine maximum pulse duration nanoseconds) allowed. Compare specified maximum pulse duration signal being measured. pulse duration measured less than pulse duration shown table, then signal meets specifications. Undershoot events must analyzed separately from overshoot events they mutually exclusive.
Intel® XeonProcessor with Cache
3.3.6
Determining System Meets Overshoot/Undershoot Specifications
overshoot/undershoot specifications listed following tables specify allowable overshoot/undershoot single overshoot/undershoot event. However most systems will have multiple overshoot and/or undershoot events that each have their parameters (duration, magnitude). While each overshoot meet overshoot specification, when total impact overshoot events considered, system fail. guideline ensure system passes overshoot undershoot specifications shown below: Ensure that signal ever exceeds -0.25 only overshoot/undershoot event magnitude occurs, ensure meets overshoot/ undershoot specifications following tables multiple overshoots and/or multiple undershoots occur, measure worst case pulse duration each magnitude compare results against specifications. these worst case overshoot undershoot events meet specifications (measured time specifications) table (where AF=1), then system passes.
following notes apply Table through Table Absolute Maximum Overshoot magnitude 1.8V must never exceeded. Absolute Maximum Overshoot measured referenced VSS, Pulse Duration overshoot measured relative VCC. Absolute Maximum Undershoot Pulse Duration undershoot measured relative VSS. Ringback below cannot subtracted from overshoots/undershoots. Lesser undershoot does allocate longer larger overshoot. System designers strongly encouraged follow Intel's layout guidelines. values specified design characterization.
Intel® XeonProcessor with Cache
Table Source Synchronous (400 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot 1.80 1.75 1.70 1.65 1.60 1.55 Absolute Maximum Undershoot 0.320 0.270 0.220 0.170 0.120 0.070 Pulse Duration (ns) 0.01 0.03 0.09 0.25 0.76 2.54 Pulse Duration (ns) 0.15 0.45 1.28 3.71 5.00 5.00 Pulse Duration (ns) 0.01 1.58 4.60 5.00 5.00 5.00 5.00
NOTES: These specifications measured processor pad. Assumes BCLK period referenced associated source synchronous strobes.
Table Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot 1.80 1.75 1.70 1.65 1.60 1.55 Absolute Maximum Undershoot 0.320 0.270 0.220 0.170 0.120 0.07 Pulse Duration (ns) 0.03 0.06 0.18 0.51 1.52 5.08 Pulse Duration (ns) 0.29 0.62 1.75 5.06 10.00 10.00 Pulse Duration (ns) 0.01 2.88 6.25 10.00 10.00 10.00 10.00
NOTES: These specifications measured processor pad. Assumes BCLK period referenced associated source synchronous strobes.
Intel® XeonProcessor with Cache
Table Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot 1.80 1.75 1.70 1.65 1.60 1.55 Absolute Maximum Undershoot 0.320 0.270 0.220 0.170 0.120 0.07 Pulse Duration (ns) 0.06 0.12 0.35 1.01 3.04 10.16 Pulse Duration (ns) 0.58 1.25 3.50 10.12 20.00 20.00 Pulse Duration (ns) 0.01 5.77 12.49 20.00 20.00 20.00 20.00
NOTES: These specifications measured processor pad. BCLK period WIRED processor signals tolerate upto overshoot/undershoot. referenced BCLK[1:0].
Table Asynchronous GTL+, PWRGOOD, Signal Groups Overshoot/Undershoot Tolerance
Absolute Maximum Overshoot 1.80 1.75 1.70 1.65 1.60 1.55 Absolute Maximum Undershoot 0.320 0.270 0.220 0.170 0.120 0.07 Pulse Duration (ns) 0.17 0.37 1.05 3.04 9.13 30.48 Pulse Duration (ns) 1.73 3.75 10.51 30.37 60.00 60.00 Pulse Duration (ns) 0.01 17.30 37.48 60.00 60.00 60.00 60.00
NOTES: These specifications measured processor pad. These signals assumed time domain.
Intel® XeonProcessor with Cache
Figure Maximum Acceptable Overshoot/Undershoot Waveform
Maximum Absolute Overshoot VMAX
Time-dependent Overshoot
GTLREF VMIN Maximum Absolute Undershoot Time-dependent Undershoot
000588
Intel® XeonProcessor with Cache
Intel® XeonProcessor with Cache
Mechanical Specifications
Intel® Xeonprocessor with cache uses Interposer Micro Grid Array (INTmPGA) package technology. Components package include flip-chip ball grid array (FCBGA) package containing processor covered integrated heat spreader (IHS) mounted pinned interposer. Mechanical specifications processor given this section. Section terminology definitions. Figure provides basic assembly drawing includes components which make entire processor. addition package components, several components located interposer, including EEPROM thermal sensor. Package dimensions provided Table Intel® Xeonprocessor with cache utilizes surface mount 603-pin zeroinsertion force (ZIF) socket installation into baseboard. 603-Pin Socket Design Guidelines further details processor socket. Figure through Figure following notes apply: Unless otherwise specified, following drawings dimensioned millimeters. dimensions tested, guaranteed design characterization. Figures drawings labelled "Reference Dimensions" provided informational purposes only. Reference Dimensions extracted from mechanical design database nominal dimensions with tolerance information applied. Reference Dimensions checked part processor manufacturing process. Unless noted such, dimensions parentheses without tolerances Reference Dimensions. Drawings scale. Figure INT-mPGA Processor Package Assembly Drawing (Includes Socket)
Note: This drawing scale reference only. 603-pin socket supplied reference only.
Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) between processor Processor Flip Chip interconnect FCBGA (Flip Chip Ball Grid Array) package FCBGA solder joints Processor interposer 603-pin socket 603-pin socket solder joints
Intel® XeonProcessor with Cache
Figure
Mechanical Specifications
INT-mPGA Processor Package View: Component Placement Detail
Intel® XeonProcessor with Cache
Figure
INT-mPGA Processor Package Drawing
Table INT-mPGA Processor Package Dimensions
Symbol
Milimeters Nominal 53.19 53.34 34.90 35.00 30.90 31.00 1.37 2.00 9.02 9.17 4.55 5.00 18.82 19.05 13.74 13.97 1.27 17.83 18.09 14.50 14.63 19.10 19.36 0.28 0.31
Notes 53.49 35.10 31.10 2.64 9.32 5.45 19.28 14.20 Nominal 18.34 14.76 19.61 0.36 0.25
Diameter
Figure details keep-in zone components mounted side processor interposer. components include EEPROM, thermal sensor, resistors capacitors.
Intel® XeonProcessor with Cache
Figure
INT-mPGA Processor Package View: Component Height Keep-in
Figure details keep-in specification pin-side components. processor contain side capacitors mounted processor package. These capacitors will exposed within opening interposer cavity. Figure INT-mPGA Processor Package Cross Section View: Side Component Keep-in
FCBGA Interposer 1.270mm 13.411mm Component Keepin Socket must allow clearance shoulders mate flush with this surface Component Keepin
Intel® XeonProcessor with Cache
Figure
INT-mPGA Processor Package: Detail
Kovar with plating micrometers over micrometer 0.254 Diametric true position, pin.
Intel® XeonProcessor with Cache
Figure details flatness tilt specifications Intel Xeon processor, respectively. Tilt measured with reference datum bottom processor interposer. Figure Flatness Tilt Drawing
Processor Package Load Specifications
Table provides dynamic static load specifications processor IHS. These mechanical load limits should exceeded during heat sink assembly, mechanical stress testing, standard drop shipping conditions. heat sink attach solutions must induce continuous stress onto processor with exception uniform load maintain heat sink-toprocessor thermal interface. recommended portion processor interposer mechanical reference load bearing surface thermal solutions.
Table Package Dynamic Static Load Specifications
Parameter Static Dynamic input (AF) Unit Unit
NOTES: This specification applies uniform compressed load. This maximum static force that applied heatsink clip maintain heatsink processor interface. These parameters based design characterization tested. Dynamic loading specifications defined assuming maximum duration 11ms. heatsink weight assumed pound. Shock input system during shock testing assumed G's. amplification factor.
Intel® XeonProcessor with Cache
Insertion Specifications
processor inserted removed times from 603-pin socket meeting 603-Pin Socket Design Guidelines document. Note that this specification based design characterization tested.
Mass Specifications
Table specifies processors mass. This includes components which make entire processor product.
Table Processor Mass
Processor Intel® Xeonprocessor with cache Mass (grams)
Materials
processor assembled from several components. basic material properties described Table
Table Processor Material Properties
Component Integrated Heat Spreader FC-BGA Interposer Interposer pins Material Nickel plated copper Resin Kovar with Gold over nickel
Intel® XeonProcessor with Cache
Markings
following section details processor top-side laser markings. provided identification processor. Figure Processor Top-Side Markings
INTEL CONFIDENTIAL
{ATPO}
NOTE:
Character size laser markings height 0.050" (1.27mm), width 0.032" (0.81mm). characters will upper case. Figure Processor Bottom-Side Markings
80528KC1.5G1M QXXXES {COO} {FPO}-[{SN}
Intel® XeonProcessor with Cache
Pin-Out Diagram
This section provides view processor grid. Figure Figure detail coordinates processor pins.
Figure
Processor Diagram: View
COMMON CLOCK
ADDRESS
COMMON CLOCK
Async JTAG
Vcc/Vss
Vcc/Vss
CLOCKS
Signal Power Ground
DATA
SM_VCC GTLREF Reserved
SMBus
Intel® XeonProcessor with Cache
Figure
Processor Diagram: Bottom View
Async JTAG
COMMON CLOCK
ADDRESS
COMMON CLOCK
SMBus
DATA
Signal Power Ground SM_VCC GTLREF Reserved
CLOCKS
Vcc/Vss
Vcc/Vss
Intel® XeonProcessor with Cache
Listing Signal Definitions
Processor Assignments
Section contains system signal groups Table Intel® Xeonprocessor with cache. This section provides sorted list Table Table Table listing processor pins ordered alphabetically name. Table listing processor pins ordered number.
5.1.1
Listing Name
Table Listing Name Table Listing Name
Name A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Name A28# A29# A30# A31# A32# A33# A34# A35# A20M# ADS# ADSTB0# ADSTB1# AP0# AP1# BCLK0 BCLK1 BINIT# BNR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPRI# BR0#
Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Common Source Sync Source Sync Common Common Common Common Common Common Common Common Common Common Common Common
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Intel® XeonProcessor with Cache Table Listing Name
Name BR1# BR2# BR3#
Table Listing Name
Name D32# D33# D34#
AD16 AA27 AA25 AD27 AA24 AB26 AB25 AB23 AA22 AA21 AB20 AB22 AB19 AA19 AE26 AC26 AD25 AE25 AC24 AD24 AE23 AC23 AA18 AC20 AC21 AE22 AE20 AD21 AD19 AB17
Signal Buffer Type
Common Common Common Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync
Direction Input Input Input Output
AB16 AA16 AC17 AE13 AD18 AB15 AD13 AD14 AD11 AC12 AE10 AC11 AD10 AA13 AA14 AC14 AB12 AB13 AA11 AA10 AB10 AC27 AD22 AE12 AC18
Signal Buffer Type
Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Common Common Source Sync Source Sync Source Sync Source Sync Common
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output
BSEL0 BSEL1 COMP0 COMP1 D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31#
D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DBSY# DEFER# DBI0# DBI1# DBI2# DBI3# DP0#
Output2 Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output
Intel® XeonProcessor with Cache Table Listing Name
Name DP1# DP2# DP3# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FERR# GTLREF GTLREF GTLREF GTLREF HIT# HITM# IERR# IGNNE# INIT# LINT0 LINT1 LOCK# MCERR# ODTEN PROCHOT# PWRGOOD REQ0# REQ1# REQ2# REQ3# REQ4# Reserved Reserved Reserved Reserved Reserved AE19 AC15 AE17 Signal Buffer Type
Common Common Common Common Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Source Sync Async GTL+ Power/Other Power/Other Power/Other Power/Other Common Common Async GTL+ Async GTL+ Async GTL+ Async GTL+ Async GTL+ Common Common Power/Other Async GTL+ Async GTL+ Source Sync Source Sync Source Sync Source Sync Source Sync Reserved Reserved Reserved Reserved Reserved
Table Listing Name
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET# RS0# RS1# RS2# RSP# SKTOCC# SLP# SM_ALERT# SM_CLK SM_DAT SM_EP_A0 SM_EP_A1 SM_EP_A2 SM_TS1_A0 SM_TS1_A1 SM_VCC SM_VCC SM_WP SMI# STPCLK# TESTHI0 TESTHI1 TESTHI2 TESTHI3 AE15 AE16 AD28 AC28 AC29 AA29 AB29 AB28 AA28 AE28 AE29 AD29 Signal Buffer Type
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Common Common Common Common Common Power/Other Async GTL+ SMBus SMBus SMBus SMBus SMBus SMBus SMBus SMBus Power/Other Power/Other SMBus Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other
Direction Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Output Input Input Input Input Input/Output Input/Output Input Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Reserved Reserved Reserved Reserved Reserved
Direction Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input Input Input Input Input Output Input Output Input Input/Output Input Input Input Input Input
Input Input Input Input Input Output Input Input Input Input
Intel® XeonProcessor with Cache Table Listing Name
Name TESTHI4 TESTHI5 TESTHI6
THERMTRIP#
Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Signal Buffer Type
Power/Other Power/Other Power/Other Async GTL+ Common Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction Input Input Input Output Input Input Input
Direction
TRDY# TRST#
Intel® XeonProcessor with Cache Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Listing Name
Name Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Direction
Direction
Intel® XeonProcessor with Cache Table Listing Name
Name AA12 AA20 AA26 AA31 AB14 AB18 AB24 AB30 AC10 AC16 AC22 AC31 AD12 AD20 AD26 AD30 AE14 Signal Buffer Type
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Table Listing Name
Name VCCA VCCIOPLL VCCSENSE VID0 VID1 VID2 VID3 VID4 AE18 AE24 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Output Output Output Output Output Output Direction
Direction
Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Intel® XeonProcessor with Cache Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel® XeonProcessor with Cache Table Listing Name
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Name
Name AA15 AA17 AA23 AA30 AB11 AB21 AB27 AB31 AC13 AC19 AC25 AC30 AD15 AD17 AD23 AD31 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel® XeonProcessor with Cache Table Listing Name
Name VSSA AE11 AE21 AE27 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Input Direction
Table Listing Name
Name VSSSENSE Signal Buffer Type Power/Other Direction Output
These "Reserved" pins Intel Xeon processor. systems utilizing Intel Xeon processor, system designer must terminate these signals processor VCC. Baseboard treating Reserved will operate correctly with clock MHz.
Intel® XeonProcessor with Cache
5.1.2
Listing Number
Table Listing Number Table Listing Number
Name Reserved SKTOCC# Reserved A32# A33# A26# A20# A14# A10# Reserved Reserved LOCK# HITM# Reserved Reserved Signal Buffer Type Reserved Power/Other Power/Other Reserved Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Reserved
Common
Name VID4 OTDEN A31# A27# A21# A22# A13# A12# A11# REQ0# REQ1# REQ4# LINT0 PROCHOT# VCCSENSE VID3
Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync
Common
Direction
Direction Reserved
Output
Output Reserved
Input
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output
Reserved Reserved Input/Output
Input/Output Input/Output
Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Power/Other
Common Common
Input/Output Input/Output
Input/Output Input/Output
Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Output Output Input Output
Input/Output Input/Output
Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Reserved Input Reserved
Intel® XeonProcessor with Cache
Table Listing Number
Name Reserved RSP# A35# A34# A30# A23# A16# A15# REQ3# REQ2# DEFER# IGNNE# SMI# VID2 STPCLK# INIT# MCERR# AP1# BR3# Signal Buffer Type Power/Other Reserved
Common
Table Listing Number
Name A29# A25# A18# A17# ADS# BR0# RS1# BPRI# Reserved VSSSENSE VID1 BPM5# IERR# BPM2# BPM4# AP0# BR2# A28# A24# COMP1 DRDY#
Direction
Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Common Common Power/Other
Common Common
Direction Input/Output Input/Output
Reserved Input
Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other
Common Common
Input/Output Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input Input
Input/Output Input/Output
Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Common
Reserved Output
Input/Output Input/Output
Power/Other
Common
Input Input Input Input Input
Power/Other Async GTL+ Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Async GTL+
Common
Output Input/Output Output
Power/Other
Common Common
Input/Output Input/Output
Power/Other
Common Common
Output Input
Input/Output Input
Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other
Common
Input Input/Output
Input/Output Input/Output
Power/Other
Common Common
Input/Output Input
Input
Power/Other
Input/Output
Intel® XeonProcessor with Cache
Table Listing Number
Name TRDY# RS0# HIT# FERR# VID0 BPM3# BPM0# BPM1# GTLREF BINIT# BR1# ADSTB1# A19# ADSTB0# DBSY# BNR# RS2# GTLREF TRST# THERMTRIP Signal Buffer Type
Common
Table Listing Number
Name A20M# LINT1 Signal Buffer Type Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Direction Input
Direction Input
Power/Other
Common Common
Input Input/Output
Power/Other Power/Other Async GTL+ Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
Common Common
Input Output
Output
Output
Input/Output Input/Output
Power/Other
Common
Input/Output Input
Power/Other Power/Other
Common Common
Input/Output Input
Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Input/Output Input/Output
Input/Output Input/Output
Power/Other
Common Common
Input/Output Input
Power/Other Power/Other Power/Other Async GTL+ Output Input Input
Intel® XeonProcessor with Cache
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel® XeonProcessor with Cache
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Table Listing Number
Name Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Direction
Intel® XeonProcessor with Cache
Table Listing Number
Name Reserved BCLK1 TESTHI0 TESTHI1 TESTHI2 GTLREF GTLREF Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Input Input Input Input Input Input Reserved Direction
Table Listing Number
Name Reserved BCLK0 TESTHI3 RESET# D62# DSTBP3# DSTBN3# DSTBP2# DSTBN2# DSTBP1# DSTBN1# DSTBP0# DSTBN0# Reserved Reserved SM_TS1_A1 BSEL0 Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Power/Other Power/Other
Common
Direction
Reserved Input
Input
Input Input/Output
Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Reserved Reserved SMBus Power/Other Power/Other Power/Other Power/Other Power/Other
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Reserved Reserved Input
Output2
Intel® XeonProcessor with Cache
Table Listing Number
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA30 AA31 AB10 AB11 Name VSSA TESTHI4 D61# D54# D53# D48# D49# D33# D24# D15# D11# D10# SM_TS1_A0 SM_EP_A0 BSEL1 VCCA D63# PWRGOOD DBI3# D55# Signal Buffer Type Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync SMBus SMBus Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Power/Other Power/Other Source Sync Source Sync Power/Other Input/Output Input/Output Input Output2 Input Input/Output Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input Direction
Table Listing Number
AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB31 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 Name D51# D52# D37# D32# D31# D14# D12# D13# SM_EP_A2 SM_EP_A1 Reserved D60# D59# D56# D47# D43# D41# D50# DP2# D34# DP0# Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other SMBus SMBus Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync
Common
Direction Input/Output Input/Output
Input/Output Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input Input
Reserved
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Input/Output Input/Output
Power/Other Source Sync
Common
Input/Output Input/Output
Power/Other
Intel® XeonProcessor with Cache
Table Listing Number
AC20 AC21 AC22 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30 AC31 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 Name D25# D26# D23# D20# D17# DBI0# SM_CLK SM_DAT Reserved VCCIOPLL TESTHI5 D57# D46# D45# D40# D38# D39# COMP0 D36# D30# D29# DBI1# D21# D18# Signal Buffer Type Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync SMBus SMBus Power/Other Power/Other Reserved Power/Other Power/Other Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input Input Reserved Input/Output Input/Output Input Output Input/Output Input/Output Direction Input/Output Input/Output
Table Listing Number
AD26 AD27 AD28 AD29 AD30 AD31 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE27 AE28 AE29 Name SM_ALERT# SM_WP Reserved TESTHI6 SLP# D58# D44# D42# DBI2# D35# Reserved Reserved DP3# DP1# D28# D27# D22# D19# D16# SM_VCC SM_VCC Signal Buffer Type Power/Other Source Sync SMBus SMBus Power/Other Power/Other Power/Other Power/Other Reserved Power/Other Async GTL+ Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Reserved Reserved
Common
Direction
Input/Output Output Input
Reserved Input Input Input/Output
Input/Output Input/Output
Input/Output Input/Output
Reserved Reserved Input/Output
Power/Other
Common
Input/Output Input/Output
Source Sync Power/Other Source Sync Source Sync Power/Other Source Sync Source Sync Power/Other Power/Other Power/Other
Input/Output Input/Output
Input/Output Input/Output
These "Reserved" pins Intel Xeon processor. systems utilizing Intel Xeon processor, system designer must terminate these signals processor VCC. Baseboards treating Reserved will operate correctly with clock MHz.
Intel® XeonProcessor with Cache
Signal Definitions
Table Signal Definitions (Page
Name Type Description A[35:3]# (Address) define byte physical memory address space. sub-phase address phase, these pins transmit address transaction. subphase these pins transmit transaction type information. These signals must connect appropriate pins agents system bus. A[35:3]# protected parity signals AP[1:0]#. A[35:3]# source synchronous signals latched into receiving buffers ADSTB[1:0]#. active-to-inactive transition RESET#, processors sample subset A[35:3]# pins determine their power-on configuration. Section 7.1. A20M# (Address-20 Mask) asserted, processor masks physical address (A20#) before looking line internal cache before driving read/ write transaction bus. Asserting A20M# emulates 8086 processor's address wrap-around MByte boundary. Assertion A20M# only supported real mode. A20M# asynchronous signal. However, ensure recognition this signal following write instruction, must valid along with TRDY# assertion corresponding write transaction. ADS# (Address Strobe) asserted indicate validity transaction address A[35:3]# pins. agents observe ADS# activation begin parity checking, protocol checking, address decode, internal snoop, deferred reply match operations associated with transaction. This signal must connect appropriate pins system agents. Address strobes used latch A[35:3]# REQ[4:0]# their rising falling edge. AP[1:0]# (Address Parity) driven request initiator along with ADS#, A[35:3]#, transaction type REQ[4:0]# pins. correct parity signal high even number covered signals number covered signals low. This allows parity high when covered signals high. AP[1:0]# should connect appropriate pins system agents. following table defines coverage model these signals. AP[1:0]# Request Signals A[35:24]# A[23:3]# REQ[4:0]# Subphase AP0# AP1# AP1# Subphase AP1# AP0# AP0#
A[35:3]#
A20M#
ADS#
ADSTB[1:0]#
BCLK[1:0]
differential pair BCLK (Bus Clock) determines frequency. processor system agents must receive these signals drive their outputs latch their inputs. external timing parameters specified with respect rising edge BCLK0 crossing falling edge BCLK1.
Intel® XeonProcessor with Cache
Table Signal Definitions (Page
Name Type Description BINIT# (Bus Initialization) observed driven processor system agents used, must connect appropriate pins such agents. BINIT# driver enabled during power configuration, BINIT# asserted signal condition that prevents reliable future information. BINIT# observation enabled during power-on configuration (see Section 7.1) BINIT# sampled asserted, symmetric agents reset their LOCK# activity request arbitration state machines. agents reset their transaction tracking state machines upon observation BINIT# assertion. Once BINIT# assertion been observed,
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