SST34HF1681 SST34HF168116Mb (x16) SRAM (x16) ComboMemory FEA
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Mbit Concurrent SuperFlash Mbit SRAM ComboMemory
SST34HF1681
SST34HF168116Mb (x16) SRAM (x16) ComboMemory
FEATURES:
Flash Organization: Dual-Bank Architecture Concurrent Read/Write Operation Mbit: Mbit Mbit SRAM Organization: Mbit: 512K Single 2.7-3.3V Read Write Operations Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) Hardware Sector Protection (WP#) Protects outer most sectors KWord) larger bank holding unprotects holding high Hardware Reset (RST#) Resets internal state machine reading data array Sector-Erase Capability Uniform KWord sectors Block-Erase Capability Uniform KWord blocks Read Access Time Flash: SRAM: Latched Address Data Fast Erase Word-Program: Sector-Erase Time: (typical) Block-Erase Time: (typical) Chip-Erase Time: (typical) Word-Program Time: (typical) Chip Rewrite Time: seconds (typical) Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Ready/Busy# CMOS Compatibility JEDEC Standard Command Conforms Common Flash Memory Interface (CFI) Packages Available 56-ball LFBGA (8mm 10mm)
PRODUCT DESCRIPTION
SST34HF1681 ComboMemory devices integrate CMOS flash memory bank with 512K CMOS SRAM memory bank Multi-Chip Package (MCP). These devices fabricated using SST's proprietary, highperformance CMOS SuperFlash technology incorporating split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST34HF1681 devices ideal applications such cellular phones, GPSs, PDAs other portable electronic devices power small form factor system. SST34HF1681 features dual flash memory bank architecture allowing concurrent operations between flash memory banks SRAM. devices read data from either bank while Erase Program operation progress opposite bank. flash memory banks partitioned into Mbit Mbit with bottom sector protection options storing boot code, program code, configuration/parameter data user data. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore, system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. SST34HF1681 devices offer guaranteed endurance 10,000 cycles. Data retention rated greater than years. With high performance Word-Program, flash memory banks provide typical Word-Program time µsec. entire flash memory bank erased programmed word-by-word typically seconds SST34HF1681, when using interface features such Toggle Data# Polling indicate completion Program operation. protect against inadvertent flash write, SST34HF1681 devices contain onchip hardware software data protection schemes. flash SRAM operate independent memory banks with respective bank enable signals. memory bank selection done bank enable signals. SRAM bank enable signal, BES1# BES2, selects
©2002 Silicon Storage Technology, Inc. S71214-00-000 2/02
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Concurrent SuperFlash, CSF, ComboMemory trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications SRAM bank. flash memory bank enable signal, BEF#, used with Software Data Protection (SDP) command sequence when controlling Erase Program operations flash memory bank. memory banks superimposed same memory address space where they share common address lines, data lines, which minimize power consumption area. Designed, manufactured, tested applications requiring power small form factor, SST34HF1681 offered both commercial extended temperatures small footprint package meet board space constraint requirements.
Flash Read Operation
Read operation SST34HF1681 controlled BEF# OE#, both have system obtain data from outputs. BEF# used device selection. When BEF# high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either BEF# high. Refer Read cycle timing diagram further details (Figure
Flash Word-Program Operation
SST34HF1681 programmed word-by-word basis. Before Program operations, memory must erased first. Program operation consists three steps. first step three-byte load sequence Software Data Protection. second step load word address word data. During Word-Program operation, addresses latched falling edge either BEF# WE#, whichever occurs last. data latched rising edge either BEF# WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth BEF#, whichever occurs first. Program operation, once initiated, will completed typically within Figures BEF# controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands issued during internal Program operation ignored.
Device Operation
SST34HF1681 uses BES1#, BES2 BEF# control operation either flash SRAM memory bank. When BEF# low, flash bank activated Read, Program Erase operation. When BES1# low, BES2 high SRAM activated Read Write operation. BEF# BES1# cannot level, BES2 cannot high level same time. bank enable signals asserted, contention will result device suffer permanent damage. address, data, control lines shared flash SRAM memory banks which minimizes power consumption loading. device goes into standby when BEF# BES1# bank enables raised VIHC (Logic High) when BEF# high BES2 low.
Concurrent Read/Write Operation
Dual bank architecture SST34HF1681 devices allows Concurrent Read/Write operation whereby user read from bank while program erase other bank. This operation used when user needs read system code bank while updating data other bank. Figure Dual-Bank Memory Organization. CONCURRENT READ/WRITE STATE TABLE
Flash Bank Read Write Write Operation Write Operation Bank Write Read Operation Write Operation Write SRAM Operation Operation Read Read Write Write
Flash Sector/Block-Erase Operation
Sector/Block-Erase operation allows system erase device sector-by-sector block-by-block basis. SST34HF1681 offer both Sector-Erase Block-Erase mode. sector architecture based uniform sector size KWord. Block-Erase mode based uniform block size KWord. SectorErase operation initiated executing six-byte command sequence with Sector-Erase command (30H) sector address (SA) last cycle. Block-Erase operation initiated executing six-byte command sequence with Block-Erase command (50H) block address (BA) last cycle. sector block address latched falling edge sixth pulse, while command (30H 50H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. Figures timing waveforms. commands issued during Sector- Block-Erase operation ignored.
S71214-00-000 2/02
Note: purposes this table, write means Block-, Sector, Chip-Erase, Word-Program applicable appropriate bank.
©2002 Silicon Storage Technology, Inc.
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Flash Chip-Erase Operation
SST34HF1681 provide Chip-Erase operation, which allows user erase unprotected sectors/blocks state. This useful when device must quickly erased. Chip-Erase operation initiated executing sixbyte command sequence with Chip-Erase command (10H) address 5555H last byte sequence. Erase operation begins with rising edge sixth BEF#, whichever occurs first. During Erase operation, only valid read Toggle Bits Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands issued during Chip-Erase operation ignored.
Ready/Busy# (RY/BY#)
SST34HF1681 includes Ready/Busy# (RY/BY#) output signal. During initiated operation, e.g., Erase, Program, Read operation, RY/BY# actively pulled low, indicating controlled operation Progress. status RY/BY# valid after rising edge fourth CE#) pulse Program operation. Sector-, Block- Bank-Erase, RY/BY# valid after rising edge sixth (CE#) pulse. RY/BY# open drain output that allows several devices tied parallel external pull resistor. Ready/ Busy# high impedance whenever high RST# low. There recovery time (TBR) required before valid data read data bus. commands entered immediately after RY/BY# goes high.
Flash Write Operation Status Detection
SST34HF1681 provide hardware software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. hardware detection uses Ready/ Busy# (RY/BY#) pin. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge WE#, which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Ready/Busy# (RY/ BY#), Data# Polling (DQ7) Toggle (DQ6) read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Flash Data# Polling (DQ7)
When SST34HF1681 internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles. During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling (DQ7) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- ChipErase, Data# Polling (DQ7) valid after rising edge sixth BEF#) pulse. Figure Data# Polling (DQ7) timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after becomes true data.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Flash Toggle Bits (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating i.e., toggling between When internal Program Erase operation completed, will stop toggling. device then ready next operation. Toggle (DQ6) valid after rising edge fourth BEF#) pulse Program operation. Sector-, Block- Chip-Erase, Toggle (DQ6) valid after rising edge sixth BEF#) pulse. Figure Toggle timing diagram Figure flowchart. There recovery time (TBR) required before valid data read data bus. commands entered immediately after longer toggles.
Hardware Reset (RST#)
RST# provides hardware method resetting device read array data. When RST# held least TRP, in-progress operation will terminate return Read mode (see Figure 18). When internal Program/Erase operation progress, minimum period TRHR required after RST# driven high before valid Read take place (see Figure 17). Erase operation that been interrupted needs reinitiated after device resumes normal operation mode ensure data integrity. Figures timing diagrams.
Software Data Protection (SDP)
SST34HF1681 provide JEDEC standard Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion three-byte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte sequence. SST34HF1681 shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode within TRC. contents DQ15-DQ8 "Don't Care" during command sequence.
Data Protection
SST34HF1681 provide both hardware software features protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: BEF# pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, BEF# high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Common Flash Memory Interface (CFI) Hardware Block Protection
SST34HF1681 provide hardware block protection which protects outermost KWord Bank block protected when held low. Figure BlockProtection location. user disable block protection driving high thus allowing erase program data into protected sectors. must held high prior issuing write command remain stable until after entire Write operation completed. SST34HF1681 also contain information describe characteristics device. order enter Query mode, system must write three-byte sequence, same Software Entry command with (CFI Query command) address 555H last byte sequence. Once device enters Query mode, system read data addresses given Tables through system must write Exit command return Read mode from Query mode.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Product Identification
Product Identification mode identifies device SST34HF1681 manufacturer SST. This mode accessed software operations only. hardware device Read operation, which typically used programmers cannot used this device because shared lines between flash SRAM multi-chip package. Therefore, application high voltage damage this device. Users software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Tables software operation, Figure Software Entry Read timing diagram Figure Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
ADDRESS Manufacturer's Device SST34HF1681 0001H 2761H
T1.0
SRAM Read
SRAM Read operation SST34HF1681 controlled BES1#, both have with BES2 high system obtain data from outputs. BES1# BES2 used SRAM bank selection. output control used gate data from output pins. data high impedance state when high. Refer Read cycle timing diagram, Figure further details.
SRAM Write
SRAM Write operation SST34HF1681 controlled BES1#, both have low, BES2 have high system write SRAM. During Word-Write operation, addresses data referenced rising edge either BES1#, WE#, falling edge BES2 whichever occurs first. write time measured from last falling edge BES#1 rising edge BES2 first rising edge BES1#, falling edge BES2. Refer Write cycle timing diagram, Figures further details.
DATA 00BFH
0000H
Product Identification Mode Exit/ Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read mode. This command also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Please note that Software Exit/ Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform Figure flowchart.
SRAM Operation
With BES1# low, BES2 BEF# high, SST34HF1681 operates 512K CMOS SRAM, with fully static operation requiring external clocks timing strobes. SST34HF1681 SRAM mapped into first KWord address space. When BES1#, BEF# high BES2 low, memory banks deselected device enters standby. Read Write cycle times equal. control signals UBS# LBS# provide access upper data byte lower data byte. Table SRAM Read Write data byte control modes operation.
©2002 Silicon Storage Technology, Inc. S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
FUNCTIONAL BLOCK DIAGRAM
Address Buffers SuperFlash Memory (Bank
RST# BEF# LBS# UBS# BES1# BES2 RY/BY#
SuperFlash Memory (Bank Control Logic Buffers DQ15
Address Buffers Most significant address
Mbit SRAM
B1.2
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Bottom Sector Protection; KWord Blocks; KWord Sectors
FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H A7FFFH A0000H 9FFFFH 98000H 97FFFH 90000H 8FFFFH 88000H 87FFFH 80000H 7FFFFH 78000H 77FFFH 70000H 6FFFFH 68000H 67FFFH 60000H 5FFFFH 58000H 57FFFH 50000H 4FFFFH 48000H 47FFFH 40000H 3FFFFH 38000H 37FFFH 30000H 2FFFFH 28000H 27FFFH 20000H 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH 001000H 000FFFH 000000H Block Block Block
Bank Bank
Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block Block
KWord Sector Protection (Four KWord Sectors)
Block
F02.0
FIGURE SST34HF1681, MBIT CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2002 Silicon Storage Technology, Inc. S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
VIEW (balls facing down)
DQ15 DQ14
DQ13 DQ12 VDDS VDDF DQ11
BES2 RST# RY/BY# LBS# UBS#
DQ10
BEF# BES1#
SST34HF1681
F03.0
FIGURE ASSIGNMENTS 56-BALL LFBGA (8MM TABLE DESCRIPTION
Symbol
10MM) COMBOMEMORY PINOUT
Name
Functions provide flash address, A19-A0. provide SRAM address, A18-A0 output data during Read cycles receive input data during Write cycles. Data internally latched during flash Erase/Program cycle. outputs tri-state when high BES1# high BES2 BEF# high. activate Flash memory bank when BEF#
Address Inputs DQ15-DQ0 Data Inputs/Outputs
BEF# BES1# BES2 UBS# LBS# RST# RY/BY#
Flash Memory Bank Enable
SRAM Memory Bank Enable activate SRAM memory bank when BES1# SRAM Memory Bank Enable activate SRAM memory bank when BES2 high Output Enable Write Enable Upper Byte Control (SRAM) Lower Byte Control (SRAM) Write Protect Reset Ready/Busy# gate data output buffers control Write operations enable DQ15-DQ8 enable DQ7-DQ0 protect unprotect sectors from Erase Program operation Reset return device Read mode output status Program Erase Operation RY/BY# open drain output, 100K pull-up resistor required allow RY/BY# transition high indicating device ready read. 2.7-3.3V Power Supply Flash only 2.7-3.3V Power Supply SRAM only Unconnected pins
T2.1
Ground Power Supply (Flash) Power Supply (SRAM) Connection
VDDF VDDS
Most Significant Address
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE OPERATIONAL MODES SELECTION1
Mode Full Standby Output Disable BEF# Flash Read Flash Write Flash Erase SRAM Read BES1# BES22 SRAM Write Product Identification3
LBS#
UBS#
DQ0-7 HIGH-Z HIGH-Z HIGH-Z DOUT DOUT HIGH-Z DOUT HIGH-Z
DQ8-15 HIGH-Z HIGH-Z HIGH-Z DOUT DOUT DOUT HIGH-Z HIGH-Z
Manufacturer's Device
T3.2
VIH, other value. apply BEF# VIL, BES1# BES2 same time Software mode only With A19-A1 Manufacturer's 00BFH, read with A0=0, SST34HF1681 Device 2761H, read with A0=1
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Software Entry5 Query Entry5 Software Exit/ Exit6
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 5555H 5555H 5555H 5555H 5555H 5555H 5555H Data2
Write Cycle Addr1 5555H 5555H 5555H Data2 Data
Write Cycle Addr1 2AAAH 2AAAH 2AAAH Data2
Write Cycle Addr1 SAX4 BAX4 5555H Data2
T4.1
Address format A14-A0 (Hex),Address A19-A15 VIH, other value, Command sequence. Data format DQ15-DQ8 VIH, other value, Command sequence. Program Word address Sector-Erase; uses A19-A11 address lines BAX, Block-Erase; uses A19-A15 address lines device does remain Software Product Identification Mode powered down. With A20-A1 Manufacturer's 00BFH, read with A0=0 SST34HF1681 Device 2761H, read with A0=1.
TABLE QUERY IDENTIFICATION STRING1
Address Data 0051H 0052H 0059H 0001H 0007H 0000H 0000H 0000H 0000H 0000H 0000H
T5.0
Data Query Unique ASCII string "QRY"
Primary command Address Primary Extended Table Alternate command (00H none exists) Address Alternate extended Table (00H none exits)
Refer publication more details.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE SYSTEM INTERFACE INFORMATION
Address Data 0027H 0036H 0000H 0000H 0004H 0000H 0004H 0006H 0001H 0000H 0001H 0001H Data
(Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts
(Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts (00H pin) (00H pin) Typical time Word-Program Typical time size buffer program (00H supported) Typical time individual Sector/Block-Erase Typical time Chip-Erase Maximum time Word-Program times typical Maximum time buffer program times typical Maximum time individual Sector/Block-Erase times typical Maximum time Chip-Erase times typical
T6.0
TABLE DEVICE GEOMETRY INFORMATION
Address Data 0015H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0008H 0000H 001FH 0000H 0000H 0001H Bytes KByte/block (0100H 256)
T7.0
Data Device size Byte (15H Bytes) Flash Device Interface description; 0001H x16-only asynchronous interface Maximum number byte multi-byte write (00H supported) Number Erase Sector/Block sizes supported device Sector Information Number sectors; 256B sector size) 1023 1024 sectors (03FF 1023) Bytes KByte/sector (0008H Block Information Number blocks; 256B block size) blocks (001F
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Operating Temperature -20°C +85°C Storage Temperature -65°C +125°C Voltage Ground Potential .-0.5V VDD1+0.3V Transient Voltage (<20 Ground Potential -1.0V VDD1+1.0V Package Power Dissipation Capability 25°C) 1.0W Output Short Circuit Current2
VDDF VDDS Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Extended Ambient Temp +70°C -20°C +85°C
2.7-3.3V 2.7-3.3V
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE OPERATING CHARACTERISTICS (VDD VDDF
Limits Symbol Parameter Active Current Read Flash SRAM Concurrent Operation Write1 Flash SRAM VILC VIHC VOLF VOHF VOLS VOHS Standby Current Reset Current Input Leakage Current Output Leakage Current Input Voltage Input Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Flash Output Voltage Flash Output High Voltage SRAM Output Voltage SRAM Output High Voltage VDD-0.3 3.0V 3.3V Units Test Conditions Address input VIL/VIH, f=1/TRC Min, VDD=VDD Max, open OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH, BES2=VIL BEF#=VIH, BES1#=VIL BES2=VIH BEF#=VIH, BES1#=VIL BES2=VIH WE#=VIL BEF#=VIL, BES1#=VIH, BES2=VIL, OE#=VIH BEF#=VIH, BES1#=VIL BES2=VIH Max, BEF#=BES1#=VIHC, BES2=VILC Reset=VSS±0.3V VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD VDD=VDD =-500 VDD=VDD
T8.1
VDDS 2.7-3.3V)
VDD-0.2
active while Erase Program progress.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T9.0
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T10.1
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE FLASH RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T11.0
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
CHARACTERISTICS
TABLE SRAM READ CYCLE TIMING PARAMETERS
SST34HF1681-70 Symbol TRCS TAAS TBES TOES TBYES TBLZS
SST34HF1681-90 Units
T12.0
Parameter Read Cycle Time Address Access Time Bank Enable Access Time Output Enable Access Time UBS#, LBS# Access Time BES# Active Output Output Enable Active Output UBS#, LBS# Active Output BES# High-Z Output Output Disable High-Z Output UBS#, LBS# High-Z Output Output Hold from Address Change
TOLZS1 TBYLZS1 TBHZS1 TOHZS TOHS
TBYHZS1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE SRAM WRITE CYCLE TIMING PARAMETERS
SST34HF1681-70 Symbol TWCS TBWS TAWS TASTS TWPS TWRS TBYWS TODWS TOEWS TDSS TDHS Parameter Write Cycle Time Bank Enable End-of-Write Address Valid End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time UBS#, LBS# End-of-Write Output Disable from Output Enable from High Data Set-up Time Data Hold from Write Time SST34HF1681-90 Units
T13.0
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Preliminary Specifications TABLE FLASH READ CYCLE TIMING PARAMETERS 2.7-3.3V
SST34HF1681-70 Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time BEF# Active Output Active Output BEF# High High-Z Output High High-Z Output Output Hold from Address Change RST# Pulse Width RST# High Before Read RST# Read SST34HF1681-90 Units
T14.0
This parameter measured only initial qualification after design process change that could affect this parameter. This parameter applies Sector-Erase, Block-Erase Program operations. This parameter does apply Chip-Erase.
TABLE FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol TOES TOEH TWPH1 TCPH1 TDH1 TIDA1 TBY1 TBR1 TSCE Parameter Word-Program Time Address Setup Time Address Hold Time BEF# Setup Time BEF# Hold Time High Setup Time High Hold Time BEF# Pulse Width Pulse Width Pulse Width High BEF# Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time RY/BY# Delay Time Bus# Recovery Time Sector-Erase Block-Erase Chip-Erase Units
T15.2
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
TRCS ADDRESSES AMSS-0 TAAS BES1# TBES TOHS
BES2
TBES TBLZS TBHZS TOES TOLZS TOHZS TBYES TBYLZS TBYHZS DATA VALID
F04.0
UBS#, LBS#
DQ15-0
AMSS Most Significant SRAM Address
FIGURE SRAM READ CYCLE TIMING DIAGRAM
TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS
TAWS TBWS BES1#
BES2
TBWS
TBYWS UBS#, LBS# TODWS TOEWS TDSS TDHS NOTE
DQ15-8, DQ7-0
NOTE
VALID DATA
F05.0
Notes: High during Write cycle, outputs will remain high impedance. BES1# goes BES2 goes high coincident with after goes Low, output will remain high impedance. BES1# goes High BES2 goes coincident with before goes High, output will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1
©2002 Silicon Storage Technology, Inc. S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
TWCS ADDRESSES AMSS-0 TWPS TWRS
TBWS BES1#
BES2
TBWS TAWS TASTS TBYWS
UBS#, LBS# TDSS DQ15-8, DQ7-0 TDHS
NOTE
VALID DATA
NOTE
F06.0
Notes: High during Write cycle, outputs will remain high impedance. Because signals output state this time, input signals reverse polarity must applied.
FIGURE SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
ADDRESS A19-0 BEF# TCLZ DATA VALID TOLZ
TOHZ
TCHZ HIGH-Z DATA VALID
F07.0
DQ15-0
HIGH-Z
FIGURE FLASH READ CYCLE TIMING DIAGRAM
ADDRESS A19-0 5555 BEF# RY/BY# DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) Note: VIH, other value. VALID
F08.2
2AAA
5555
ADDR
TWPH
FIGURE FLASH CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
ADDRESS A19-0 5555 BEF# TCPH 2AAA 5555 ADDR
RY/BY# DQ15-0
XXAA
XX55
XXA0
DATA WORD (ADDR/DATA)
VALID
F09.2
Note: VIH, other value.
FIGURE FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A19-0 BEF# TOEH DATA# DATA# VALID DATA
F10.1
TOES
FIGURE FLASH DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
ADDRESS A19-0 BEF# TOEH
READ CYCLES WITH SAME OUTPUTS
VALID DATA
F11.2
FIGURE FLASH TOGGLE TIMING DIAGRAM
SIX-BYTE CODE CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
BEF#
RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10
VALID
F12.2
Note: This device also supports BEF# controlled Chip-Erase operation. BEF# signals interchageable long minimum timings met. (See Table VIH, other value.
FIGURE FLASH CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
SIX-BYTE CODE BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY#
DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX50
VALID
F13.2
Note: This device also supports BEF# controlled Block-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Block Address VIH, other value.
FIGURE FLASH CONTROLLED BLOCK-ERASE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA
BEF#
RY/BY# DQ15-0
XXAA
XX55
XX80
XXAA
XX55
XX30
VALID
F14.2
Note: This device also supports BEF# controlled Sector-Erase operation. BEF# signals interchageable long minimum timings met. (See Table Sector Address VIH, other value.
FIGURE FLASH CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
THREE-BYTE SEQUENCE SOFTWARE ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001
BEF#
TWPH DQ15-0 XXAA XX55 XX90 00BF
Device
F15.2
TIDA
Device 2761H SST34HF1681 Note: VIH, other value
FIGURE FLASH SOFTWARE ENTRY
READ
THREE-BYTE SEQUENCE QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555
BEF#
TWPH DQ15-0 XXAA XX55 XX98
F16.1
TIDA
Note:
VIH, other value.
FIGURE FLASH ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
5555
2AAA
5555
DQ15-0
XXAA
XX55
XXF0 TIDA
BEF#
TWHP
F17.1
Note: VIH, other value
FIGURE FLASH SOFTWARE EXIT/CFI EXIT
RY/BY# RST#
BEF#/OE# TRHR
F26.0
FIGURE RST# TIMING (WHEN
INTERNAL OPERATION PROGRESS)
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
RY/BY# RST#
BEF#
F19.1
FIGURE RST# TIMING (DURING SECTOR-
BLOCK-ERASE
OPERATION)
VIHT INPUT VILT
F20.0
REFERENCE POINTS
OUTPUT
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TESTER
F21.0
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Start
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XXA0H Address: 5555H
Load Word Address/Word Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F22.0
Note: VIH, other value.
FIGURE WORD-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Internal Timer Program/Erase Initiated
Toggle Program/Erase Initiated
Data# Polling Program/Erase Initiated
Wait TBP, TSCE,
Read word
Read
Program/Erase Completed
Read same word
true data?
Does match? Program/Erase Completed
Program/Erase Completed
F23.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Query Entry Command Sequence
Software Product Entry Command Sequence
Software Exit/CFI Exit Command Sequence
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX98H Address: 5555H
Load data: XX90H Address: 5555H
Load data: XXF0H Address: 5555H
Wait TIDA
Wait TIDA
Wait TIDA
Read data
Read Software
Return normal operation
F24.1
Note: VIH, other value.
FIGURE SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Chip-Erase Command Sequence Load data: XXAAH Address: 5555H
Sector-Erase Command Sequence Load data: XXAAH Address: 5555H
Block-Erase Command Sequence Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XX80H Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XXAAH Address: 5555H
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX55H Address: 2AAAH
Load data: XX10H Address: 5555H
Load data: XX30H Address:
Load data: XX50H Address:
Wait TSCE
Wait
Wait
Chip erased FFFFH
Sector erased FFFFH
Block erased FFFFH
F25.0
Note: VIH, other value.
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
PRODUCT ORDERING INFORMATION
Device Speed Suffix1 Suffix2 Package Modifier balls Package Type LFBGA (8mm 10mm 1.4mm, 0.45mm ball size) Temperature Range Commercial +70°C Extended -20°C +85°C Minimum Endurance =10,000 cycles Read Access Speed Bank Split SRAM Density SRAM Mbit Flash Density Mbit Voltage 2.7-3.3V Device Family
SST34HF16xx
Valid combinations SST34HF1681 SST34HF1681-70-4C-L1P SST34HF1681-90-4C-L1P SST34HF1681-70-4E-L1P SST34HF1681-90-4E-L1P
Note: Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
PACKAGING DIAGRAMS
BOTTOM VIEW VIEW
10.00 0.20 5.60 0.80
0.80 CORNER 1.30 0.10 5.60 8.00 0.20
0.45 0.05 (56X) CORNER
SIDE VIEW
0.12 0.35 0.05
SEATING PLANE
56-lfbga-L1P-8x10-450mic-3
Note: Although many dimensions similar those JEDEC Publication MO-210, this specific package registered. linear dimensions millimeters. Coplanarity: 0.12 actual shape corners slightly different than portrayed drawing.
56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) PACKAGE CODE:
10MM
©2002 Silicon Storage Technology, Inc.
S71214-00-000 2/02
Mbit Concurrent SuperFlash Mbit SRAM ComboMemory SST34HF1681
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71214-00-000 2/02
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