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SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST2


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Kbit Mbit Mbit Mbit (x8) Small-Sector Flash
SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
SST29SF/VF512 040512Kb (x8) Byte-Program, Small Erase Sector flash memories
FEATURES:
Organized 128K 256K 512K Single Voltage Read Write Operations 4.5-5.5V-only SST29SF512/010/020/040 2.7-3.6V SST29VF512/010/020/040 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption: Active Current: (typical) Standby Current: (typical) SST29SF512/010/020/040 (typical) SST29VF512/010/020/040 Sector-Erase Capability Uniform Byte sectors Fast Read Access Time: Latched Address Data Fast Erase Byte-Program: Sector-Erase Time: (typical) Chip-Erase Time: (typical) Byte-Program Time: (typical) Chip Rewrite Time: second (typical) SST29SF/VF512 seconds (typical) SST29SF/VF010 seconds (typical) SST29SF/VF020 seconds (typical) SST29SF/VF040 Automatic Write Timing Internal Generation End-of-Write Detection Toggle Data# Polling Compatibility SST29SFxxx CMOS Compatibility SST29VFxxx JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm) 32-pin PDIP
PRODUCT DESCRIPTION
SST29SF512/010/020/040 SST29VF512/010/ 020/040 128K 256K 512K CMOS Small-Sector Flash (SSF) manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST29SFxxx devices write (Program Erase) with 4.5-5.5V power supply. SST29VFxxx devices write (Program Erase) with 2.73.6V power supply. These devices conform JEDEC standard pinouts memories. Featuring high performance Byte-Program, SST29SFxxx SST29VFxxx devices provide maximum Byte-Program time µsec. protect against inadvertent write, they have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, these devices offered with guaranteed endurance least 10,000 cycles. Data retention rated greater than years. SST29SFxxx SST29VFxxx devices suited applications that require convenient economical updating program, configuration, data memory. system applications, they significantly improve performance
©2002 Silicon Storage Technology, Inc. S71160-05-000 2/02
reliability, while lowering power consumption. They inherently less energy during Erase Program than alternative flash technologies. total energy consumed function applied voltage, current, time application. Since given voltage range, SuperFlash technology uses less current program shorter erase time, total energy consumed during Erase Program operation less than alternative flash technologies. They also improve flexibility while lowering cost program, data, configuration storage applications. SuperFlash technology provides fixed Erase Program times, independent number Erase/Program cycles that have occurred. Therefore system software hardware does have modified de-rated necessary with alternative flash technologies, whose Erase Program times increase with accumulated Erase/Program cycles. meet high density, surface mount requirements, SST29SFxxx SST29VFxxx devices offered 32lead PLCC 32-lead TSOP packages. mil, 32-pin PDIP also offered SST29SFxxx devices. Figures pinouts.
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Small-Sector Flash trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Device Operation
Commands used initiate memory operation functions device. Commands written device using standard microprocessor write sequences. command written asserting while keeping low. address latched falling edge CE#, whichever occurs last. data latched rising edge CE#, whichever occurs first.
pulse, while command (20H) latched rising edge sixth pulse. internal Erase operation begins after sixth pulse. End-of-Erase operation determined using either Data# Polling Toggle methods. Figure timing waveforms. commands issued during Sector-Erase operation ignored.
Chip-Erase Operation
SST29SFxxx SST29VFxxx devices provide Chip-Erase operation, which allows user erase entire memory array "1s" state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 555H last byte sequence. internal Erase operation begins with rising edge sixth CE#, whichever occurs first. During internal Erase operation, only valid read Toggle Data# Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during ChipErase operation will ignored.
Read
Read operation SST29SFxxx SST29VFxxx devices controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
Byte-Program Operation
SST29SFxxx SST29VFxxx devices programmed byte-by-byte basis. Before programming, sector where byte exists must fully erased. Program operation accomplished three steps. first step three-byte load sequence Software Data Protection. second step load byte address byte data. During Byte-Program operation, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. third step internal Program operation which initiated after rising edge fourth CE#, whichever occurs first. Program operation, once initiated, will completed, within Figures controlled Program operation timing diagrams Figure flowcharts. During Program operation, only valid reads Data# Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Write Operation Status Detection
SST29SFxxx SST29VFxxx devices provide software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). End-of-Write detection mode enabled after rising edge which initiates internal Program Erase operation. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Sector-Erase Operation
Sector-Erase operation allows system erase device sector-by-sector basis. SST29SFxxx SST29VFxxx offer Sector-Erase mode. sector architecture based uniform sector size Bytes. Sector-Erase operation initiated executing six-bytecommand sequence with Sector-Erase command (20H) sector address (SA) last cycle. sector address latched falling edge sixth
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Data# Polling (DQ7)
When SST29SFxxx SST29VFxxx devices internal Program operation, attempt read will produce complement true data. Once Program operation completed, will produce true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read will produce `0'. Once internal Erase operation completed, will produce `1'. Data# Polling valid after rising edge fourth CE#) pulse Program operation. Sector- Chip-Erase, Data# Polling valid after rising edge sixth CE#) pulse. Figure Data# Polling timing diagram Figure flowchart.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 2.5V SST29SFxxx. Write operation inhibited when less than 1.5V. SST29VFxxx. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP)
SST29SFxxx SST29VFxxx provide JEDEC approved Software Data Protection scheme data alteration operations, i.e., Program Erase. Program operation requires inclusion series threebyte sequence. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. These devices shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device read mode, within TRC.
Toggle (DQ6)
During internal Program Erase operation, consecutive attempts read will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth CE#) pulse Program operation. Sector ChipErase, Toggle valid after rising edge sixth CE#) pulse. Figure Toggle timing diagram Figure flowchart.
Data Protection
SST29SFxxx SST29VFxxx devices provide both hardware software features protect nonvolatile data from inadvertent writes.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Product Identification
Product Identification mode identifies devices SST29SF512, SST29SF010, SST29SF020, SST29SF040 SST29VF512, SST29VF010, SST29VF020, SST29VF040 manufacturer SST. This mode accessed software operations. Users Software Product Identification operation identify part (i.e., using device when using multiple manufacturers same socket. details, Table software operation, Figure Software Entry Read timing diagram Figure Software Entry command sequence flowchart. TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST29SF512 SST29VF512 SST29SF010 SST29VF010 SST29SF020 SST29VF020 SST29SF040 SST29VF040 0001H 0001H 0001H 0001H 0001H 0001H 0001H 0001H
T1.1
Product Identification Mode Exit/Reset
order return standard Read mode, Software Product Identification mode must exited. Exit accomplished issuing Software Exit command sequence, which returns device Read operation. Please note that Software Exit command ignored during internal Program Erase operation. Table software command codes, Figure timing waveform, Figure flowchart.
Data
0000H
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Memory Address
Address Buffers Latches Y-Decoder
B1.1
Control Logic
Buffers Data Latches
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512
32-lead PLCC View
F02a.4
FIGURE ASSIGNMENTS 32-LEAD PLCC
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
SST29SF/VF040 SST29SF/VF020 SST29SF/VF010 SST29SF/VF512
SST29SF/VF512 SST29SF/VF010 SST29SF/VF020 SST29SF/VF040
Standard Pinout View
F01.2
FIGURE ASSIGNMENTS 32-LEAD TSOP (8MM
SST29SF040 SST29SF020 SST29SF010 SST29SF512
14MM)
SST29SF512 SST29SF010 SST29SF020 SST29SF040
32-pin PDIP View
F02b.4
FIGURE ASSIGNMENTS 32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Preliminary Specifications TABLE DESCRIPTION
Symbol AMS1-A0 DQ7-DQ0 Name Address Inputs Data Input/output Functions provide memory addresses. During Sector-Erase AMS-A8 address lines will select sector. output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide power supply voltage: 4.5-5.5V SST29SF512/010/020/040 2.7-3.6V SST29VF512/010/020/040
Chip Enable Output Enable Write Enable Power Supply Ground Connection
connected internally
T2.3
Most significant address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020, SST29SF/VF040
TABLE OPERATION MODES SELECTION
Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode Table
T3.4
DOUT High High DOUT High DOUT
Address Sector address, Chip-Erase
VIH, other value.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Preliminary Specifications TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Byte-Program Sector-Erase Chip-Erase Software Entry4,5 Software Exit6 Software Exit6 Write Cycle Addr1 555H 555H 555H 555H 555H Data 2AAH 555H
T4.5
Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH Data
Write Cycle Addr1 555H 555H 555H 555H Data
Write Cycle Addr1 555H 555H Data Data
Write Cycle Addr1 2AAH 2AAH Data
Write Cycle Addr1 SAX3 555H Data
Address format A14-A0 (Hex), Address VIH, other value, Command sequence SST29SF/VF512. Addresses AMS-A15 VIH, other value, Command sequence SST29SF/VF020 SST29SF/VF040. Most significant address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020, SST29SF/VF040 SST29SF/VF010. Program Byte address Sector-Erase; uses AMS-A7 address lines SST29SF/VFxxx device does remain Software Product mode powered down. With AMS-A1 Manufacturer's BFH, read with SST29SF512 Device 20H, read with SST29SF512 Device 21H, read with SST29SF010 Device 22H, read with SST29VF010 Device 23H, read with SST29SF020 Device 24H, read with SST29SF020 Device 25H, read with SST29SF040 Device 13H, read with SST29VF040 Device 14H, read with Both Software Exit operations equivalent
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Through Hold Lead Soldering Temperature Seconds) 300°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Industrial
SST29SF512/010/020/040
4.5-5.5V 4.5-5.5V
OPERATING RANGE
Range Commercial Industrial
SST29VF512/010/020/040
2.7-3.6V 2.7-3.6V
Ambient Temp +70°C -40°C +85°C
Ambient Temp +70°C -40°C +85°C
CONDITIONS
TEST
Input Rise/Fall Time Output Load Figures Output Load
TABLE OPERATING CHARACTERISTICS 4.5-5.5V SST29SFXXX
Limits Symbol Parameter Power Supply Current Read Write ISB1 ISB2 VIHC Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.3 Units Test Conditions Address input=VIL/VIH, f=1/TRC VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIH, VDD=VDD CE#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=2.1 VDD=VDD IOH=-400 VDD=VDD
T5.3
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Preliminary Specifications TABLE OPERATING CHARACTERISTICS 2.7-3.6V SST29VFXXX
Limits Symbol Parameter Power Supply Current Read Write VIHC Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage (CMOS) Output Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 Units Test Conditions Address input=VIL/VIH, f=1/TRC VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T6.5
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
Parameter Power-up Read Operation Power-up Program/Erase Operation
Minimum
Units
T7.1
TPU-WRITE1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE 25°C, Mhz, other pins open)
Parameter CI/O1
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T8.1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T9.2
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS 4.5-5.5V SST29SFXXX
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output
Output Hold from Address Change
2.7-3.6V SST29VFXXX
SST29SF/VFxxx-55 SST29SF/VFxxx-70 Units
T10.6
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS 4.5-5.5V SST29SFXXX 2.7-3.6V SST29VFXXX
Symbol TOES TOEH TWPH1 TCPH TSCE
Parameter Byte-Program Time Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Pulse Width High Pulse Width High Data Setup Time Data Hold Time Software Access Exit Time Sector-Erase Chip-Erase
Units
TIDA1
T11.7
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
ADDRESS AMS-0
TOLZ
TOHZ TCHZ HIGH-Z DATA VALID
F03.1
DQ7-0
HIGH-Z
TCLZ
DATA VALID
Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 DQ7-0 DATA BYTE (ADDR/DATA) TWPH ADDR
F04.1
Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
INTERNAL PROGRAM OPERATION STARTS ADDRESS AMS-0 DQ7-0 DATA BYTE (ADDR/DATA) TCPH ADDR
F05.1
Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS AMS-0 TOEH TOES
F06.1
Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
ADDRESS AMS-0 TOEH TOES
READ CYCLES WITH SAME OUTPUTS F07.1
Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE TOGGLE TIMING DIAGRAM
SIX-BYTE CODE SECTOR-ERASE ADDRESS AMS-0
DQ7-0
F10.2
Note: device also supports controlled Sector-Erase operation. signals interchangeable long minimum timings met. (See Table Most significant address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
SIX-BYTE CODE CHIP-ERASE ADDRESS AMS-0
TSCE
DQ7-0
F17.2
Note: This device also supports controlled Chip-Erase operation. signals interchageable long minimum timings met. (See Table Note: Most Significant Address SST29SF/VF512, SST29SF/VF010, SST29SF/VF020 SST29SF/VF040
FIGURE CONTROLLED CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence Software Entry ADDRESS A14-0 0000 0001
TIDA
TWPH DQ7-0 Device
F08.2
Note: Device SST29SF512, SST29SF010, SST29SF020, SST29SF040 SST29VF512, SST29VF010, SST29VF020, SST29VF040
FIGURE SOFTWARE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
THREE-BYTE SEQUENCE SOFTWARE EXIT RESET
ADDRESS A14-0
DQ7-0
TIDA
F21.0
FIGURE SOFTWARE EXIT RESET
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (3.0 logic VILT logic "0". Measurement reference points inputs outputs (1.5 VDD) (1.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
SST29SFXXX
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F11.0
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Input rise fall times (10% 90%)
Note: VINPUT Test VOUTPUT Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
SST29VFXXX
TEST LOAD EXAMPLE SST29SF512/010/020/040 TESTER HIGH
TEST LOAD EXAMPLE SST29VF512/010/020/040
TESTER
F12b.2
F12.2
FIGURE TEST LOAD EXAMPLES
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Start
Load data: Address: 555H
Load data: Address: 2AAH
Load data: Address: 555H
Load Byte Address/Byte Data
Wait Program (TBP, Data# Polling bit, Toggle operation) Program Completed
F13.1
FIGURE BYTE-PROGRAM ALGORITHM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Internal Timer ByteProgram/Erase Initiated
Toggle ByteProgram/Erase Initiated
Data# Polling ByteProgram/Erase Initiated
Wait TBP, TSCE,
Read byte
Read
Program/Erase Completed
Read same byte
true data?
Does match?
Program/Erase Completed
Program/Erase Completed
F14.0
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Software Entry Command Sequence
Software Exit Reset Command Sequence
Load data: Address: 555H
Load data: Address: 555H
Load data: Address:
Load data: Address: 2AAH
Load data: Address: 2AAH
Wait TIDA
Load data: Address: 555H
Load data: Address: 555H
Return normal operation
Wait TIDA
Wait TIDA
Read Software
Return normal operation
F15.1
FIGURE SOFTWARE COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Chip-Erase Command Sequence Load data: Address: 555H
Sector-Erase Command Sequence Load data: Address: 555H
Load data: Address: 2AAH
Load data: Address: 2AAH
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: 555H
Load data: Address: 2AAH
Load data: Address: 2AAH
Load data: Address: 555H
Load data: Address:
Wait TSCE
Wait
Chip erased
Sector erased
F19.2
FIGURE ERASE COMMAND SEQUENCE
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
PRODUCT ORDERING INFORMATION
Device SST29xFxxx Speed Suffix1 Suffix2 Package Modifier pins leads Package Type PLCC TSOP (type 14mm) PDIP Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed Device Density Mbit Mbit Mbit Kbit Function Chip- Sector-Erase Byte-Program Voltage 4.5-5.5V 2.7-3.6V
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Preliminary Specifications Valid combinations SST29SF512 SST29SF512-55-4C-NH SST29SF512-70-4C-NH SST29SF512-55-4I-NH SST29SF512-70-4I-NH SST29SF512-55-4C-WH SST29SF512-70-4C-WH SST29SF512-55-4I-WH SST29SF512-70-4I-WH SST29SF512-70-4C-PH
Valid combinations SST29VF512 SST29VF512-55-4C-NH SST29VF512-70-4C-NH SST29VF512-55-4I-NH SST29VF512-70-4I-NH SST29VF512-55-4C-WH SST29VF512-70-4C-WH SST29VF512-55-4I-WH SST29VF512-70-4I-WH
Valid combinations SST29SF010 SST29SF010-55-4C-NH SST29SF010-70-4C-NH SST29SF010-55-4I-NH SST29SF010-70-4I-NH SST29SF010-55-4C-WH SST29SF010-70-4C-WH SST29SF010-55-4I-WH SST29SF010-70-4I-WH SST29SF010-70-4C-PH
Valid combinations SST29VF010 SST29VF010-55-4C-NH SST29VF010-70-4C-NH SST29VF010-55-4I-NH SST29VF010-70-4I-NH SST29VF010-55-4C-WH SST29VF010-70-4C-WH SST29VF010-55-4I-WH SST29VF010-70-4I-WH
Valid combinations SST29SF020 SST29SF020-55-4C-NH SST29SF020-70-4C-NH SST29SF020-55-4I-NH SST29SF020-70-4I-NH SST29SF020-55-4C-WH SST29SF020-70-4C-WH SST29SF020-55-4I-WH SST29SF020-70-4I-WH SST29SF020-70-4C-PH
Valid combinations SST29VF020 SST29VF020-55-4C-NH SST29VF020-70-4C-NH SST29VF020-55-4I-NH SST29VF020-70-4I-NH SST29VF020-55-4C-WH SST29VF020-70-4C-WH SST29VF020-55-4I-WH SST29VF020-70-4I-WH
Valid combinations SST29SF040 SST29SF040-55-4C-NH SST29SF040-70-4C-NH SST29SF040-55-4I-NH SST29SF040-70-4I-NH SST29SF040-55-4C-WH SST29SF040-70-4C-WH SST29SF040-55-4I-WH SST29SF040-70-4I-WH SST29SF040-70-4C-PH
Valid combinations SST29VF040 SST29VF040-55-4C-NH SST29VF040-70-4C-NH SST29VF040-55-4I-NH SST29VF040-70-4I-NH
Note:
SST29VF040-55-4C-WH SST29VF040-70-4C-WH SST29VF040-55-4I-WH SST29VF040-70-4I-WH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Identifier
1.05 0.95 0.50
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
14MM
©2002 Silicon Storage Technology, Inc.
S71160-05-000 2/02
Kbit Mbit Mbit Mbit Small-Sector Flash SST29SF512 SST29SF010 SST29SF020 SST29SF040 SST29VF512 SST29VF010 SST29VF020 SST29VF040
Identifier
.075 .065 Base Plane Seating Plane
1.655 1.645
PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 .150 .120
.012 .008 .600
.080 .070
.065 .045
.022 .016
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71160-05-000 2/02

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