SST29EE512 SST29LE512 SST29VE512 SST29EE VE512512Kb Page-Write fl
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Kbit (64K Page-Write EEPROM
SST29EE512 SST29LE512 SST29VE512
SST29EE VE512512Kb Page-Write flash memories
FEATURES:
Single Voltage Read Write Operations 4.5-5.5V SST29EE512 3.0-3.6V SST29LE512 2.7-3.6V SST29VE512 Superior Reliability Endurance: 100,000 Cycles (typical) Greater than years Data Retention Power Consumption Active Current: (typical) (typical) 3.0/2.7V Standby Current: (typical) Fast Page-Write Operation Bytes Page, Pages Page-Write Cycle: (typical) Complete Memory Rewrite: (typical) Effective Byte-Write Cycle Time: (typical) Fast Read Access Time 4.5-5.5V operation: 3.0-3.6V operation: 2.7-3.6V operation: Latched Address Data Automatic Write Timing Internal Generation Write Detection Toggle Data# Polling Hardware Software Data Protection Product Identification accessed Software Operation Compatibility JEDEC Standard Flash EEPROM Pinouts command sets Packages Available 32-lead PLCC 32-lead TSOP (8mm 14mm, 20mm) 32-pin PDIP
PRODUCT DESCRIPTION
SST29EE/LE/VE512 CMOS, Page-Write EEPROMs manufactured with SST's proprietary, high performance CMOS SuperFlash technology. splitgate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST29EE/LE/VE512 write with single power supply. Internal Erase/Program transparent user. SST29EE/LE/VE512 conform JEDEC standard pinouts byte-wide memories. Featuring high performance Page-Write, SST29EE/ LE/VE512 provide typical Byte-Write time µsec. entire memory, i.e., Kbyte, written pageby-page little seconds, when using interface features such Toggle Data# Polling indicate completion Write cycle. protect against inadvertent write, SST29EE/LE/VE512 have on-chip hardware Software Data Protection schemes. Designed, manufactured, tested wide spectrum applications, SST29EE/LE/VE512 offered with guaranteed Page-Write endurance 10,000 cycles. Data retention rated greater than years. SST29EE/LE/VE512 suited applications that require convenient economical updating program, configuration, data memory. system applications, SST29EE/LE/VE512 significantly improve performance reliability, while lowering power consumption. SST29EE/LE/VE512 improve flexibility while lowering cost program, data, configuration storage applications. meet high density, surface mount requirements, SST29EE/LE/VE512 offered 32-lead PLCC 32lead TSOP packages. 600-mil, 32-pin PDIP package also available. Figures pinouts.
Device Operation
Page-Write EEPROM offers in-circuit electrical write capability. SST29EE/LE/VE512 require separate Erase Program operations. internally timed Write cycle executes both erase program transparently user. SST29EE/LE/VE512 have industry standard optional Software Data Protection, which recommends always enabled. SST29EE/LE/ VE512 compatible with industry standard EEPROM pinouts functionality.
©2002 Silicon Storage Technology, Inc. S71060-06-000 2/02
logo SuperFlash registered trademarks Silicon Storage Technology, Inc. Small-Sector Flash trademarks Silicon Storage Technology, Inc. These specifications subject change without notice.
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Read
Read operations SST29EE/LE/VE512 controlled OE#, both have system obtain data from outputs. used device selection. When high, chip deselected only standby power consumed. output control used gate data from output pins. data high impedance state when either high. Refer Read cycle timing diagram further details (Figure
consists specific three-byte load sequence that allows writing selected page will leave SST29EE/ LE/VE512 protected Page-Write. page-load cycle consists loading Bytes data into page buffer. internal Write cycle consists TBLCO time-out write timer operation. During Write operation, only valid reads Data# Polling Toggle Bit. Page-Write operation allows loading Bytes data into page buffer SST29EE/LE/ VE512 before initiation internal Write cycle. During internal Write cycle, data page buffer written simultaneously into memory array. Hence, Page-Write feature SST29EE/LE/VE512 allows entire memory written little seconds. During internal Write cycle, host free perform additional tasks, such fetch data from other locations system write next page. each Page-Write operation, bytes that loaded into page buffer must have same page address, i.e. through A16. byte loaded with user data will written FFH. Figures Page-Write cycle timing diagrams. after completion three-byte load sequence initial byte-load cycle, host loads second byte into page buffer within byte-load cycle time (TBLC) SST29EE/LE/VE512 will stay page-load cycle. Additional bytes then loaded consecutively. page-load cycle will terminated additional byte loaded into page buffer within (TBLCO) from last byte-load cycle, i.e., subsequent high-to-low transition after last rising edge CE#. Data page buffer changed subsequent byte-load cycle. page-load period continue indefinitely, long host continues load device within byte-load cycle time page loaded determined page address last byte loaded.
Write
Page-Write SST29EE/LE/VE512 should always JEDEC Standard Software Data Protection (SDP) three-byte command sequence. SST29EE/LE/VE512 contain optional JEDEC approved Software Data Protection scheme. recommends that always enabled, thus, description Write operations will given using enabled format. three-byte Enable Write commands identical; therefore, time Write command issued, Software Data Protection automatically assured. first time three-byte command given, device becomes enabled. Subsequent issuance same command bypasses data protection page being written. desired Page-Write, entire device remains protected. additional descriptions, please application notes Proper JEDEC Standard Software Data Protection Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories. Write operation consists three steps. Step three-byte load sequence Software Data Protection. Step byte-load cycle page buffer SST29EE/LE/VE512. Steps same timing both operations. Step internally controlled Write cycle writing data loaded page buffer into memory array nonvolatile storage. During both three-byte load sequence byte-load cycle, addresses latched falling edge either WE#, whichever occurs last. data latched rising edge either WE#, whichever occurs first. internal Write cycle initiated TBLCO timer after rising edge CE#, whichever occurs first. Write cycle, once initiated, will continue completion, typically within Figures controlled Page-Write cycle timing diagrams Figures flowcharts. Write operation three functional cycles: Software Data Protection load sequence, page-load cycle, internal Write cycle. Software Data Protection
©2002 Silicon Storage Technology, Inc.
Software Chip-Erase
SST29EE/LE/VE512 provide Chip-Erase operation, which allows user simultaneously clear entire memory array state. This useful when entire device must quickly erased. Software Chip-Erase operation initiated using specific six-byte load sequence. After load sequence, device enters into internally timed cycle similar Write cycle. During Erase operation, only valid read Toggle Bit. Table load sequence, Figure timing diagram, Figure flowchart.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Write Operation Status Detection
SST29EE/LE/VE512 provide software means detect completion Write cycle, order optimize system Write cycle time. software detection includes status bits: Data# Polling (DQ7) Toggle (DQ6). write detection mode enabled after rising whichever occurs first, which initiates internal Write cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data# Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either DQ6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 2.5V. Write Inhibit Mode: Forcing low, high, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP)
SST29EE/LE/VE512 provide JEDEC approved optional Software Data Protection scheme data alteration operations, i.e., Write Chip-Erase. With this scheme, Write operation requires inclusion series three byte-load operations precede data loading operation. three-byte load sequence used initiate Write cycle, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. SST29EE/LE/VE512 shipped with Software Data Protection disabled. software protection scheme enabled applying three-byte sequence device, during page-load cycle (Figures device will then automatically into data protect mode. subsequent Write operation will require preceding three-byte sequence. Table specific software command codes Figures timing diagrams. device into unprotected mode, six-byte sequence required. Table specific codes Figure timing diagram. Write attempted while enabled device will non-accessible state recommends Software Data Protection always enabled. Figure flowcharts. SST29EE/LE/VE512 Software Data Protection global command, protecting unprotecting) pages entire memory array once enabled disabled). Therefore using single Page-Write will enable entire array. Single pages themselves cannot enabled disabled, although page addressed during write will written. Single power supply reprogrammable nonvolatile memories unintentionally altered. strongly recommends that Software Data Protection (SDP) always enabled. SST29EE/LE/VE512 should programmed using command sequence. recommends Disable Command Sequence issued device prior writing.
Data# Polling (DQ7)
When SST29EE/LE/VE512 internal Write cycle, attempt read last byte loaded during byte-load cycle will receive complement true data. Once Write cycle completed, will show true data. Note that even though have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval Figure Data# Polling timing diagram Figure flowchart.
Toggle (DQ6)
During internal Write cycle, consecutive attempts read will produce alternating `0's `1's, i.e., toggling between When Write cycle completed, toggling will stop. device then ready next operation. Figure Toggle timing diagram Figure flowchart. initial read Toggle will typically "1".
Data Protection
SST29EE/LE/VE512 provide both hardware software features protect nonvolatile data from inadvertent writes.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet Please refer following Application Notes more information using SDP: Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories Proper JEDEC Standard Software Data Protection TABLE PRODUCT IDENTIFICATION
Address Manufacturer's Device SST29EE512 SST29LE512 SST29VE512 0001H 0001H 0001H
T1.2
Data
0000H
Product Identification
Product Identification mode identifies device SST29EE/LE/VE512 manufacturer SST. This mode accessed software. details, Table Figure software entry, Read timing diagram Figure entry command sequence flowchart.
Product Identification Mode Exit
order return standard Read mode, Software Product Identification mode must exited. Exiting accomplished issuing Software Exit (reset) operation, which returns device Read operation. Reset operation also used reset device Read mode after inadvertent transient condition that apparently causes device behave abnormally, e.g., read correctly. Table software command codes, Figure timing waveform, Figure flowchart.
FUNCTIONAL BLOCK DIAGRAM
X-Decoder
SuperFlash Memory
Address Buffer Latches Y-Decoder Page Latches
Control Logic
Buffers Data Latches
B1.1
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
32-lead PLCC View
F19.1
FIGURE ASSIGNMENTS 32-LEAD PLCC
Standard Pinout View
F01.2
FIGURE ASSIGNMENTS 32-LEAD TSOP
32-pin PDIP View
F02.2
FIGURE ASSIGNMENTS 32-PIN PDIP
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet TABLE DESCRIPTION
Symbol A15-A7 A6-A0 Name Address Inputs Column Address Inputs Data Input/output Functions provide memory addresses. addresses define page Write cycle. Column Addresses toggled load page data output data during Read cycles receive input data during Write cycles. Data internally latched during Write cycle. outputs tri-state when high. activate device when low. gate data output buffers. control Write operations. provide: 5.0V supply (4.5-5.5V) SST29EE512 3.0V supply (3.0-3.6V) SST29LE512 2.7V supply (2.7-3.6V) SST29VE512
DQ7-DQ0
Chip Enable Output Enable Write Enable Power Supply
Ground Connection Unconnected pins.
T2.2
TABLE OPERATION MODES SELECTION
Mode Read Page-Write Standby Write Inhibit Software Chip-Erase Product Identification Software Mode Enable Mode Disable Mode Manufacturer's (BFH) Device Table Table Table
T3.4
DOUT High High DOUT High DOUT
Address AIN, Table
VIH, other value. Device SST29EE512 SST29LE/VE512
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet TABLE SOFTWARE COMMAND SEQUENCE
Command Sequence Software Data Protect Enable Page-Write Software Entry4,5 Software Exit Alternate Software Entry6 Write Cycle Addr1 5555H Data Write Cycle Addr1 2AAAH Data Write Cycle Addr1 5555H Data Write Cycle Addr1 Addr2 Data Data Write Cycle Addr1 Data Write Cycle Addr1 Data
Software Chip-Erase3 5555H 5555H 5555H 5555H
2AAAH 2AAAH 2AAAH 2AAAH
5555H 5555H 5555H 5555H
5555H
2AAAH
5555H
5555H
2AAAH
5555H
T4.3
Address format A14-A0 (Hex), Address VIH, other value." Page-Write consists loading Bytes (A6-A0) software Chip-Erase function supported industrial temperature part. Please contact require this function industrial temperature part. device does remain Software Product mode powered down. With A14-A1 Manufacturer's BFH, read with SST29EE512 Device 5DH, read with SST29LE/VE512 Device 3DH, read with Alternate six-byte Software Product Command Code Note: This product supports both JEDEC standard three-byte command code sequence SST's original six-byte command code sequence. designs, recommends that three-byte command code sequence used.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+0.5V Transient Voltage (<20 Ground Potential -2.0V VDD+2.0V Voltage Ground Potential -0.5V 14.0V Package Power Dissipation Capability 25°C) 1.0W Through Hold Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current1
Outputs shorted more than second. more than output shorted time.
OPERATING RANGE
Range Commercial Industrial
SST29EE512
4.5-5.5V 4.5-5.5V
Ambient Temp +70°C -40°C +85°C
OPERATING RANGE
Range Commercial Industrial
SST29LE512
3.0-3.6V 3.0-3.6V
Ambient Temp +70°C -40°C +85°C
OPERATING RANGE
Range Commercial Industrial
SST29VE512
2.7-3.6V 2.7-3.6V
Ambient Temp +70°C -40°C +85°C
CONDITIONS
TEST
Input Rise/Fall Time Output Load Gate Figures
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet TABLE OPERATING CHARACTERISTICS 4.5-5.5V SST29EE512
Limits Symbol Parameter Power Supply Current Read Write ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Units Test Conditions Address input=VIL/VIH, f=1/TRC Min, VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH, VDD=VDD CE#=OE#=WE#=VIH, VDD=VDD CE#=OE#=WE#=VDD -0.3V, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=2.1 VDD=VDD IOH=-400 VDD=VDD
T5.1
TABLE OPERATING CHARACTERISTICS 3.0-3.6V SST29LE512 2.7-3.6V SST29VE512
Limits Symbol Parameter Power Supply Current Read Write ISB1 ISB2 Standby Current (TTL input) Standby Current (CMOS input) Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Units Test Conditions Address input=VIL/VIH, f=1/TRC Min, VDD=VDD CE#=OE#=VIL, WE#=VIH, I/Os open CE#=WE#=VIL, OE#=VIH, VDD=VDD CE#=OE#=WE#=VIH, VDD=VDD CE#=OE#=WE#=VDD -0.3V, VDD=VDD VIN=GND VDD, VDD=VDD VOUT=GND VDD, VDD=VDD VDD=VDD VDD=VDD IOL=100 VDD=VDD IOH=-100 VDD=VDD
T6.2
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ1 TPU-WRITE
Parameter Power-up Read Operation Power-up Write Operation
Minimum
Units
T7.0
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE CAPACITANCE
Parameter CI/O
25°C, Mhz, other pins open)
Description Capacitance Input Capacitance
Test Condition VI/O
Maximum
T8.0
CIN1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS
Symbol NEND TDR1 ILTH1
Parameter Endurance Data Retention Latch
Minimum Specification 10,000
Units Cycles Years
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard
T9.5
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
CHARACTERISTICS
TABLE READ CYCLE TIMING PARAMETERS
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST29EE512
SST29EE512-70 SST29EE512-90 Units
T10.2
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE READ CYCLE TIMING PARAMETERS
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST29LE512
SST29LE512-150 SST29LE512-200 Units
T11.1
This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE READ CYCLE TIMING PARAMETERS
Symbol TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time Active Output Active Output High High-Z Output High High-Z Output Output Hold from Address Change
SST29VE512
SST29VE512-200 SST29VE512-250 Units
T12.1
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Data Sheet TABLE PAGE-WRITE CYCLE TIMING PARAMETERS
SST29EE512 Symbol TOES TOEH
SST29LE/VE512 Units
T13.6
Parameter Write Cycle (Erase Program) Address Setup Time Address Hold Time Setup Time Hold Time High Setup Time High Hold Time Pulse Width Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software Access Exit Time Software Chip-Erase
0.05
TBLC1 TBLCO1 TIDA1 TSCE
0.05
This parameter measured only initial qualification after design process change that could affect this parameter.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
ADDRESS A15-0 HIGH-Z TCLZ DATA VALID TOLZ
TOHZ
TCHZ DATA VALID
F03.0
FIGURE READ CYCLE TIMING DIAGRAM
Three-Byte Sequence Enabling ADDRESS A15-0 5555 2AAA 5555
TOES
TOEH
TBLC
TBLCO
BYTE DATA VALID BYTE BYTE
F04.1
FIGURE CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Three-Byte Sequence Enabling ADDRESS A15-0 5555 2AAA 5555
TOES
TBLC
TBLCO
TOEH
BYTE DATA VALID BYTE BYTE
F05.1
FIGURE CONTROLLED PAGE-WRITE CYCLE TIMING DIAGRAM
ADDRESS A15-0 TOEH TOES
TBLCO
F06.0
FIGURE DATA# POLLING TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
ADDRESS A15-0 TOEH TOES
TBLCO
READ CYCLES WITH SAME OUTPUTS
F07.0
FIGURE TOGGLE TIMING DIAGRAM
Six-Byte Sequence Disabling Software Data Protection ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TBLC
F08.1
TBLCO
FIGURE SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Six-Byte Code Software Chip-Erase ADDRESS A14-0 5555 2AAA 5555 5555 2AAA 5555
TSCE
TBLC
F09.2
TBLCO
FIGURE SOFTWARE CHIP-ERASE TIMING DIAGRAM
Three-Byte Sequence Software Entry ADDRESS A14-0 5555 2AAA 5555 0000 TIDA DEVICE 0001
TBLC DEVICE SST29EE512 SST29LE512/29VE512
F10.2
FIGURE SOFTWARE ENTRY
READ
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Three-Byte Sequence Software Exit Reset ADDRESS A14-0 5555 2AAA 5555
TIDA
TBLC
F11.0
FIGURE SOFTWARE EXIT RESET
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
VIHT
INPUT REFERENCE POINTS
OUTPUT
VILT
F12.1
test inputs driven VIHT (2.4V) logic VILT (0.4 logic "0". Measurement reference points inputs outputs (2.0 (0.8 Input rise fall times (10% 90%)
Note: VHIGH Test VLOW Test VIHT VINPUT HIGH Test VILT VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
TEST LOAD EXAMPLE TESTER HIGH
F13.1
FIGURE TEST LOAD EXAMPLE
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Start Software Data Protect Write Command
Figure
Page Address
Byte Address
Load Byte Data
Increment Byte Address
Byte Address 128? Wait TBLCO
Wait Write (TWC, Data# Polling Toggle operation) Write Completed
FIGURE WRITE ALGORITHM
F14.1
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Internal Timer
Toggle
Data# Polling
Page-Write Initiated
Page-Write Initiated
Page-Write Initiated
Wait
Read byte from page
Read (Data last byte loaded)
Write Completed
Read same byte
true data?
Write Completed
Does match?
Write Completed
F15.1
FIGURE WAIT OPTIONS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Software Data Protect Enable Command Sequence Write data: Address: 5555H
Software Data Protect Disable Command Sequence Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 5555H
Write data: Address: 5555H
Load Bytes page data
Optional Page Load Operation
Write data: Address: 5555H
Wait TBLCO
Write data: Address: 2AAAH
Wait
Write data: Address: 5555H
Enabled
Wait TBLCO
Wait
Disabled
F16.1
FIGURE SOFTWARE DATA PROTECTION FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Software Product Entry Command Sequence Write data: Address: 5555H
Software Product Exit Reset Command Sequence Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 2AAAH
Write data: Address: 5555H
Write data: Address: 5555H
Pause
Pause
Read Software
Return normal operation
F17.1
FIGURE SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
Software Chip-Erase Command Sequence Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 5555H
Write data: Address: 5555H
Write data: Address: 2AAAH
Write data: Address: 5555H
Wait TSCE
Chip-Erase
F18.2
FIGURE SOFTWARE CHIP-ERASE COMMAND CODES
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
PRODUCT ORDERING INFORMATION
Device SST29xE512 Speed Suffix1 Suffix2 Package Modifier leads pins Package Type TSOP (type 20mm) PLCC PDIP TSOP (type 14mm) Temperature Range Commercial +70°C Industrial -40°C +85°C Minimum Endurance 10,000 cycles Read Access Speed =150 Function Page-Write Voltage 4.5-5.5V 3.0-3.6V 2.7-3.6V
Valid combinations SST29EE512 SST29EE512-70-4C-NH SST29EE512-70-4I-NH SST29EE512-70-4C-WH SST29EE512-70-4I-WH SST29EE512-70-4C-EH SST29EE512-70-4I-EH SST29EE512-70-4C-PH
Valid combinations SST29LE512 SST29LE512-150-4C-NH SST29LE512-150-4I-NH SST29LE512-150-4C-WH SST29LE512-150-4I-WH SST29LE512-150-4C-EH SST29LE512-150-4I-EH
Valid combinations SST29VE512 SST29VE512-200-4C-NH SST29VE512-200-4I-NH
Note: Note:
SST29VE512-200-4C-WH SST29VE512-200-4I-WH
SST29VE512-200-4C-EH SST29VE512-200-4I-EH
Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations. software Chip-Erase function supported industrial temperature part. Please contact require this function industrial temperature part.
©2002 Silicon Storage Technology, Inc.
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
PACKAGING DIAGRAMS
VIEW
Optional Identifier .048 .042 .495 .485 .453 .447
SIDE VIEW
.112 .106 .020 MAX. .029 .023 .040 .030
BOTTOM VIEW
.042 .048 .595 .553 .585 .547 .032 .026
.021 .013 .400 .530 .490
.050 .015 Min. .050 .095 .075 .140 .125 .032 .026
Note: Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .008 inches. Coplanarity: mils.
32-plcc-NH-3
32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
1.05 0.95 0.50
Identifier
8.10 7.90
0.27 0.17
12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80
0.15 0.05
0.70 0.50 Note: Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (max/min). Coplanarity: Maximum allowable mold flash 0.15 package ends, 0.25 between leads.
32-tsop-WH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
©2002 Silicon Storage Technology, Inc.
14MM
S71060-06-000 2/02
Kbit Page-Write EEPROM SST29EE512 SST29LE512 SST29VE512
1.05 0.95 Identifier 0.50
8.10 7.90
0.27 0.17
18.50 18.30 DETAIL 1.20 max. 0.70 0.50 20.20 19.80
0.15 0.05
0.70 0.50 Note: 1.Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. 2.All linear dimensions millimeters (max/min). 3.Coplanarity: 4.Maximum allowable mold flash 0.15 package ends, 0.25mm between leads.
32-tsop-EH-7
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
20MM
Identifier
.075 .065 Base Plane Seating Plane
1.655 1.645
PLCS. .200 .170
.625 .600 .550 .530
.050 .015 .100 .150 .120
.012 .008 .600
.080 .070
.065 .045
.022 .016
Note: Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (max/min). Dimensions include mold flash. Maximum allowable mold flash .010 inches. 32-pdip-PH-3
32-PIN PLASTIC DUAL IN-LINE PINS (PDIP) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.sst.com
©2002 Silicon Storage Technology, Inc. S71060-06-000 2/02
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