FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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LC2MOS Complete, 12-Bit, kHz, Sampling ADCs AD7870/AD7875/AD7876
FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Converter On-Chip Reference Laser-Trimmed Clock Parallel, Byte Serial Digital Interface Input Frequency (AD7870, AD7875) Data Access Time Power: Variety Input Ranges: AD7870 AD7875 AD7876
GENERAL DESCRIPTION
AD7870/AD7875/AD7876 fast, complete, 12-bit converter. consists track/hold amplifier, successiveapproximation ADC, buried Zener reference versatile interface logic. features self-contained internal clock which laser trimmed guarantee accurate control conversion time. external clock timing components required; on-chip clock overridden external clock required. parts offer choice three data output formats: single, parallel, 12-bit word; 8-bit bytes, serial data. Fast access times standard control inputs ensure easy interfacing modern microprocessors digital signal processors. parts operate from power supplies. AD7870 AD7876 accept input signal ranges respectively, while AD7875 accepts unipolar input range. parts convert full power signals kHz. AD7870/AD7875/AD7876 feature accuracy specifications such linearity, full-scale offset error. addition, AD7870 AD7875 fully specified dynamic performance parameters including distortion signal-to-noise ratio. parts available 24-pin, inch-wide, plastic hermetic dual-in-line package (DIP). AD7870 AD7875 available 28-pin plastic leaded chip carrier (PLCC), while AD7876 available 24-pin small outline (SOIC) package.
PRODUCT HIGHLIGHTS
Complete 12-Bit Chip. AD7870/AD7875/AD7876 provides functions necessary analog-to-digital conversion combines 12-bit with internal clock, track/hold amplifier reference single chip. Dynamic Specifications Users. AD7870 AD7875 fully specified tested parameters, including signal-to-noise ratio, harmonic distortion intermodulation distortion. Fast Microprocessor Interface. Data access times make parts compatible with modern 16-bit microprocessors digital signal processors. digital timing parameters tested guaranteed over full operating temperature range.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
unless otherwise=noted.) A6ND DGND external, unless otherwise stated. Specifications
Parameter
DYNAMIC PERFORMANCE2 Signal Noise Ratio3 (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Track/Hold Acquisition Time ACCURACY Resolution Minimum Resolution which Missing Codes Guaranteed Integral Nonlinearity Integral Nonlinearity Differential Nonlinearity Bipolar Zero Error Positive Full-Scale Error4 Negative Full-Scale Error4 ANALOG INPUT Input Voltage Range Input Current REFERENCE OUTPUT +25°C Tempco Reference Load Sensitivity (REF OUT/I)
AD7870
Units
Test Conditions/Comments
Sine Wave, fSAMPLE Typically 71.5 Sine Wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
2.99 3.01
2.99 3.01
2.99 3.01
Bits Bits Volts ppm/°C
2.99 3.01 2.99 3.01
Reference Load Current Change (0-500 Reference Load Should Changed During Conversion.
LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current (12/8/CLK Input Only) Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11-DB0 Floating-State Leakage Current Floating-State Output Capacitance5 CONVERSION TIME External Clock (fCLK MHz) Internal Clock POWER REQUIREMENTS Power Dissipation
min/µs
ISOURCE ISINK
Specified Performance Specified Performance Typically Typically Typically
NOTES Temperature ranges follows: Versions; +70°C: Versions; -25°C +85°C: Versions; -55°C +125°C. (pk-pk) calculation includes distortion noise components. Measured with respect internal reference includes bipolar offset error. Sample tested +25°C ensure compliance. Specifications subject change without notice.
REV.
AD7870/AD7875/AD7876
Parameter ACCURACY Resolution Minimum Resolution Which Missing Codes Guaranteed Integral Nonlinearity +25°C TMIN TMAX (AD7875 Only) TMIN TMAX (AD7876 Only) Differential Nonlinearity Unipolar Offset Error (AD7875 Only) Bipolar Zero Error (AD7876 Only) Full-Scale Error +25°C2 Full-Scale Track/Hold Acquisition Time DYNAMIC PERFORMANCE3 (AD7875 ONLY) Signal-to-Noise Ratio4 (SNR) +25°C TMIN TMAX Total Harmonic Distortion (THD) Peak Harmonic Spurious Noise Intermodulation Distortion (IMD) Second Order Terms Third Order Terms ANALOG INPUT AD7875 Input Voltage Range AD7875 Input Current AD7876 Input Voltage Range AD7876 Input Current REFERENCE OUTPUT +25°C Tempco Reference Load Sensitivity (REF OUT/I) AD7875/AD7876 Units Test Conditions/Comments
1.5/-1.0
Bits Bits ppm/°C
Typical Full-Scale Error Typical ppm/°C
Sine Wave, fSAMPLE Typically 71.5 Sine Wave, fSAMPLE Typically kHz, fSAMPLE Typically kHz, kHz, fSAMPLE kHz, kHz, fSAMPLE
2.99 3.01
2.99 3.01
2.99 3.01
Volts Volts ppm/°C
Typical Tempco ppm/°C Reference Load Current Change µA-500 Reference Load Should Changed During Conversion.
LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input Current, Input Current (12/8/CLK Input Only) Input Capacitance, CIN5 LOGIC OUTPUTS Output High Voltage, Output Voltage, DB11-DB0 Floating-State Leakage Current Floating-State Output Capacitance5 CONVERSION TIME External Clock (fCLK MHz) Internal Clock POWER REQUIREMENTS
min/µs
ISOURCE ISINK
AD7870
NOTES Temperature ranges follows: AD7875: Versions, +70°C; Versions, -40°C +85°C; Version, -55°C +125°C. AD7876: Versions, -40°C +85°C; Version, -55°C +125°C. Includes internal reference error calculated after unipolar offset error (AD7875) bipolar zero error (AD7876) been adjusted out. Full-scale error refers both positive negative full-scale error AD7876. Dynamic performance parameters tested AD7876 these typically same AD7875. calculation includes distortion noise components. Sample tested +25°C ensure compliance. Specifications subject change without notice.
REV.
AD7870/AD7875/AD7876 TIMING CHARACTERISTICS1,
Parameter t115 t126 Limit TMIN, TMAX Versions)
(VDD
AGND DGND Figures 12.)
Units Conditions/Comments CONVST Pulse Width Setup Time (Mode Pulse Width Hold Time (Mode Delay Data Access Time after Relinquish Time after HBEN Setup Time HBEN Hold Time SSTRB SCLK Falling Edge Setup Time SCLK Cycle Time SCLK Valid Data Delay. SCLK Rising Edge SSTRB Relinquish Time after SCLK Setup Time (Mode BUSY Propagation Delay Data Setup Time Prior BUSY Hold Time (Mode HBEN Setup Time HBEN Hold Time
Limit TMIN, TMAX Versions)
NOTES Timing specifications bold print 100% production tested. other times sample tested ensure compliance. input signals specified with (10% timed from voltage level Serial timing measured with pull-up resistor SDATA SSTRB pull-up SCLK. capacitance three outputs measured with load circuits Figure defined time required output cross defined time required data lines change when loaded with circuits Figure SCLK mark/space ratio (measured from voltage level 40/60 60/40. SDATA will drive higher capacitive loads this will since increases external time constant (4.7 hence time reach Specifications subject chance without notice.
ABSOLUTE MAXIMUM RATINGS*
AGND -0.3 AGND +0.3 AGND DGND -0.3 +0.3 AGND AGND Digital Inputs DGND -0.3 +0.3 Digital Outputs DGND -0.3 +0.3 Operating Temperature Range Commercial Versions AD7870) +70°C Commercial Versions AD7875) +70°C Industrial Versions AD7870) .-25°C +85°C Industrial Versions AD7875/AD7876) -40°C +85°C Extended Versions) -55°C +125°C Storage Temperature Range -65°C +150°C Lead Temperature (Soldering, sec) +300°C Power Dissipation (Any Package) +75°C Derates above +75°C mW/°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
High-Z High-Z Figure Load Circuits Access Time
High-Z
High-Z
Figure Load Circuits Output Float Delay
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD7870/AD7875/AD7876 feature proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD7870/AD7875/AD7876
AD7870 ORDERING GUIDE
Model1, AD7870JN AD7870KN AD7870LN AD7870JP AD7870KP AD7870LP AD7870AQ AD7870BQ AD7870CQ AD7870SQ4 AD7870TQ4
Temperature Range +70°C +70°C +70°C +70°C +70°C +70°C -25°C +85°C -25°C +85°C -25°C +85°C -55°C +125°C -55°C +125°C
Voltage Range
(dBs)
Integral Nonlinearity (LSB)
Package Option3 N-24 N-24 N-24 P-28A P-28A P-28A Q-24 Q-24 Q-24 Q-24 Q-24
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data shee Contact local sales office LCCC (Leadless Ceramic Chip Carrier) availability. Narrow Plastic DIP; Plastic Leaded Chip Carrier (PLCC); Cerdip. Available /883B processing only.
AD7875 ORDERING GUIDE
Model1, AD7875KN AD7875LN AD7875KP AD7875LP AD7875BQ AD7875CQ AD7875TQ4
Temperature Range +70°C +70°C +70°C +70°C -40°C +85°C -40°C +85°C -55°C +125°C
Voltage Range
(dBs)
Integral Nonlinearity (LSB)
Package Option3 N-24 N-24 P-28A P-28A Q-24 Q-24 Q-24
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet. Contact local sales office LCCC (Leadless Ceramic Chip Carrier) availability. Narrow Plastic DlP; Plastic Leaded Chip Carrier (PLCC); Cerdip. Available /883B processing only.
AD7876 ORDERING GUIDE
Model1 AD7876BN AD7876CN AD7876BR AD7876CR AD7876BQ AD7876CQ AD7876TQ3
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C
Voltage Range
Integral Nonlinearity (LSB)
Package Option2 N-24 N-24 R-24 R-24 Q-24 Q-24 Q-24
NOTES order MIL-STD-883, Class processed parts, /883B part number. Contact local sales office military data sheet. Narrow Plastic DIP; Cerdip; Small Outline (SOIC). Available /883B processing only.
REV.
AD7870/AD7875/AD7876
FUNCTION DESCRIPTION
Mnemonic BUSY/INT Function
8-11
13-16
Read. Active logic input. This input used conjunction with enable data outputs. Busy/Interrupt, Active logic output indicating converter status. timing diagrams. Clock input. external TTL-compatible clock applied this input pin. Alternatively, tying this enables internal laser-trimmed clock oscillator. DB11/HBEN Data (MSB)/High Byte Enable. function this dependent state 12/8/CLK input (see below). When 12-bit parallel data selected, this provides DB11 output. When byte data selected, this becomes HBEN logic input HBEN used 8-bit interfacing. When HBEN low, DB7/LOW DB0/DB8 become DB0. With HBEN high, DB7/LOW DB0/DB8 used upper byte data (see Table DB10/SSTRB Data 10/Serial Strobe. When 12-bit parallel data selected, this provides DB10 output. SSTRB active open-drain output that provides strobe framing pulse serial data. external pull-up resistor required SSTRB. DB9/SCLK Data 9/Serial Clock. When 12-bit parallel data selected, this provides output. SCLK gated serial clock output derived from internal external clock. 12/8/CLK input then SCLK runs continuously. 12/8/CLK then SCLK gated after serial transmission complete. SCLK open-drain output requires external pull-up resistor. DB8/SDATA Data 8/Serial Data. When 12-bit parallel data selected, this provides output. SDATA opendrain serial data output which used with SCLK SSTRB serial data transfer. Serial data valid falling edge SCLK while SSTRB low. external pull-up resistor required SDATA. DB7/LOW- Three-state data outputs which controlled Their function depends 12/8/CLK HBEN DB4/LOW inputs. With 12/8/CLK high, they always DB7-DB4. With 12/8/CLK their function controlled HBEN (see Table DGND Digital Ground. Ground reference digital circuitry. DB3/DB11- Three-state data outputs which controlled Their function depends 12/8/CLK HBEN DB0/DB8 inputs. With 12/8/CLK high, they always DB3-DB0. With 12/8/CLK their function controlled HBEN (see Table Table Output Data Byte Interfacing HBEN HIGH DB7/LOW DB6/LOW DB5/LOW DB4/LOW DB3/DB11 DB11(MSB) DB2/DB10 DB10 DB1/DB9 DB0/DB8 (LSB)
AGND 12/8/CLK
CONVST
Positive Supply, Analog Ground. Ground reference track/hold, reference DAC. Voltage Reference Output. internal reference provided this pin. external load capability Analog Input. analog input range AD7870, AD7876 AD7875. Negative Supply, Three Function Input. Defines data format serial clock format. With this output data format 12-bit parallel only. With this either byte serial data available SCLK continuous. With this byte serial data again available SCLK continuous. Convert Start. high transition this input puts track/hold into hold mode starts conversion. This input asynchronous input. Chip Select. Active logic input. device selected when this input active. With CONVST tied low, conversion initiated when goes low.
SOIC
CONFIGURATIONS
PLCC2
CONFIGURATIONS SAME AD7875 AD7876. AD7870 AD7875 AVAILABLE PLCC; AD7870A AVAILABLE PLASTIC DIP; AD7875 AD7876 AVAILABLE SOIC DIP.
REV.
AD7870/AD7875/AD7876
CONVERTER DETAILS
AD7870/AD7875/AD7876 complete 12-bit converter, requiring external components apart from power supply decoupling capacitors. comprised 12-bit successive approximation based fast settling voltageoutput DAC, high speed comparator SAR, track/hold amplifier, buried Zener reference, clock oscillator control logic.
INTERNAL REFERENCE
equal conversion time plus track/hold amplifier acquisition time. input clock throughput rate max. operation track/hold essentially transparent user. track/hold amplifier goes from tracking mode hold mode start conversion. CONVST input used start conversion then track hold transition occurs rising edge CONVST. starts conversion, this transition occurs falling edge
ANALOG INPUT
AD7870/AD7875/AD7876 on-chip temperature compensated buried Zener reference which factory trimmed Internally provides both reference bias required bipolar operation (AD7870 AD7876). reference output available (REF OUT) capable providing external load. maximum recommended capacitance normal operation reference required external ADC, should decoupled with resistor series with parallel combination tantalum capacitor ceramic capacitor. These decoupling components required remove voltage spikes caused ADC's internal operation.
three parts differ from each other analog input voltage range which they handle. AD7870 accepts input signals, AD7876 accepts input range, while input range AD7875 Figure shows AD7870 analog input. analog input range into input resistance typically designed code transitions occur midway between successive integer values (i.e., LSB, LSBs, LSBs FS-3/2 LSBs). output code complement binary with FS/4096 V/4096 1.46 ideal input/output transfer function shown Figure
Figure AD7870 Analog Input Figure Reference Circuit
reference output voltage applications using AD7875 AD7876, reference required. Figure shows scale voltage provide either external reference.
AD7876 analog input structure shown Figure analog input range into input resistance typically before, designed code transitions occur midway between successive integer values. output code complement with FS/4096 V/4096 4.88 ideal input/output transfer function shown Figure
Figure Generating Reference
TRACK-AND-HOLD AMPLIFIER
track-and-hold amplifier analog input AD7870/AD7875/AD7876 allows accurately convert input frequencies 12-bit accuracy. input bandwidth track/hold amplifier much greater than Nyquist rate even when operated maximum throughput rate. cutoff frequency occurs typically kHz. track/hold amplifier acquires input signal 12-bit accuracy less than overall throughput rate REV.
Figure AD7876 Analog Input
Figure shows analog input AD7875. input range into input resistance typically Once again, designed code transitions occur midway between successive integer values. output code
AD7870/AD7875/AD7876
straight binary with FS/4096 V/4096 1.22 ideal input/output transfer function shown Figure input voltage below ground. trim procedure follows: apply voltage -0.73 mV(-1/2 LSB) Figure adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Gain error adjusted either first code transition (ADC negative full-scale) last code transition (ADC positive full scale). trim procedures both cases follows (see Figure
Figure AD7875 Analog Input
Figure Offset Full-Scale Adjust Circuit
Positive Full-Scale Adjust
Figure AD7870/AD7876 Transfer Function
Apply voltage 2.9978 (FS/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Apply voltage -2.9993 (-FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
OFFSET FULL-SCALE ADJUSTMENT-AD7876
Figure AD7875 Transfer Function
OFFSET FULL-SCALE ADJUSTMENT-AD7870
offset full-scale adjustment AD7876 similar that just outlined AD7870. trim procedure, those applications that require adjustment, follows: apply voltage -2.44 (-1/2 LSB) adjust offset voltage until output code flickers between 1111 1111 1111 0000 0000 0000. Full-scale error adjusted either first code transition (ADC negative full scale) last code transition (ADC positive full scale). trim procedure both case follows (see Figure
Positive Full-Scale Adjust
most digital signal processing (DSP) applications, offset full-scale errors have little effect system performance. Offset error always eliminated analog domain coupling. Full-scale error effect linear does cause problems long input signal within full dynamic range ADC. Some applications will require that input signal span full analog input dynamic range. such applications, offset full-scale error will have adjusted zero. Where adjustment required, offset error must adjusted before full-scale error. This achieved trimming offset driving analog input AD7870 while
Apply voltage 9.9927 (FS/2 -3/2 LSBs) Adjust until output code flickers between 0111 1111 1110 0111 1111 1111.
Negative Full-Scale Adjust
Apply voltage -9.9976 (FS/2 LSB) adjust until output code flickers between 1000 0000 0000 1000 0000 0001.
REV.
AD7870/AD7875/AD7876
OFFSET FULL-SCALE ADJUSTMENT-AD7875
Similar AD7870, most applications which AD7875 will used will require offset full-scale adjustment. applications that require adjustment, offset error must adjusted before full-scale (gain) error. This achieved applying input voltage 0.61 (1/2 LSB) Figure adjusting offset voltage until output code flickers between 0000 0000 0000 0000 0000 0001. full-scale adjustment, apply input voltage 4.9982 LSBs) adjust until output code flickers between 1111 1111 1110 1111 1111 1111.
TIMING CONTROL
functions. Serial data available during conversion with word length bits; four leading zeros, followed 12-bit conversion result starting with MSB. data synchronized serial clock output (SCLK) framed serial strobe (SSTRB). Data clocked high transition serial clock valid falling edge this clock while SSTRB output low. SSTRB goes within three clock cycles after CONVST, first serial data (which first leading zero) valid first falling edge SCLK. three serial lines open-drain outputs require external pull-up resistors. serial clock derived from clock source which internal external. Normally, SCLK required during serial transmission only. these cases, shut down conversion allow multiple ADCs share common serial bus. However, some serial systems (e.g., TMS32020) require serial clock which runs continuously. Both options available AD7870/AD7875/AD7876 using 12/8/CLK input. With this input serial clock (SCLK) runs continuously; when 12/8/CLK SCLK turned transmission.
MODE INTERFACE
AD7870/AD7875/AD7876 capable basic operating modes. first mode (Mode CONVST line used start conversion drive track/hold into hold mode. conversion track/hold returns tracking mode. intended principally digital signal processing other applications where precise sampling time required. these applications, important that signal sampling occurs exactly equal intervals minimize errors sampling uncertainty jitter. these cases, CONVST line driven timer some precise clock source. second mode achieved hard-wiring CONVST line low. This mode (Mode intended systems where microprocessor total control ADC, both initiating conversion reading data. starts conversion microprocessor will normally driven into WAIT state duration conversion BUSY/INT.
DATA OUTPUT FORMATS
addition operating modes, AD7870/AD7875/ AD7876 also offers choice three data output formats, serial parallel. parallel data formats single, 12-bit parallel word 16-bit data buses two-byte format 8-bit data buses. data format controlled 12/8/ input. logic high this selects 12-bit parallel output format only. logic applied this allows user access either serial byte formatted data. Three pins previously assigned four MSBs parallel form used serial communications while fourth becomes control input byte-formatted data. three possible data output formats selected either modes operation.
Parallel Output Format
Conversion initiated going pulse CONVST input. rising edge this CONVST pulse starts conversion drives track/hold amplifier into hold mode. Conversion will initiated low. BUSY/INT status output assumes function this mode. normally high goes conversion. This line used interrupt microprocessor. read operation accesses data line reset high falling edge CONVST input must high when brought operate correctly this mode. input should hardwired this mode. Data cannot read from part during conversion because on-chip latches disabled when conversion progress. applications where precise sampling critical, CONVST pulse generated from microprocessor line OR-gated with decoded address. some applications, depending power supply turn-on time, AD7870/AD7875/AD7876 perform conversion power-up. this case, line will power-up dummy read AD7870/AD7875/AD7876 will required reset line before starting conversion. Figure shows Mode timing diagram 12-bit parallel data output format (12/8/CLK read conversion accesses bits data same time. Serial data available this data output format.
parallel formats available part 12-bit wide data word two-byte data word. first, bits data available same time DB11 (MSB) through (LSB). second, reads required access data. When this data format selected, DB11/HBEN assumes HBEN function. HBEN selects which byte data read from ADC. When HBEN low, lower bits data placed data during read operation; with HBEN high, upper bits 12-bit word placed data bus. These bits right justified thereby occupy lower nibble data while upper nibble contains four zeros.
Serial Output Format
Serial data available AD7870/AD7875/AD7876 when 12/8/CLK input this case DB10/ SSTRB, DB9/SCLK DB8/SDATA pins assume their serial REV.
Figure Mode Timing Diagram, 12-Bit Parallel Read
AD7870/AD7875/AD7876
Figure Mode Timing Diagram, Byte Serial Read
Mode timing diagram byte serial data shown Figure goes conversion reset high first falling edge This first read conversion either access byte high byte data depending status HBEN (Figure shows byte only example). diagram shows both noncontinuously continuously running clock (dashed line).
MODE INTERFACE
BUSY function. BUSY goes start conversion, stays during conversion returns high when conversion complete. normally used parallel interfaces drive microprocessor into WAIT state duration conversion. Figure shows Mode timing diagram 12-bit parallel data output format (12/8/CLK this case, behaves like slow memory. major advantage this interface that allows microprocessor start conversion, WAIT then read data with single READ instruction. user does have worry about servicing interrupts ensuring that software delays long enough avoid reading during conversion.
second interface mode achieved hard wiring CONVST conversion initiated taking while HBEN low. track/hold amplifier goes into hold mode falling edge this mode, BUSY/INT assumes
Figure Mode Timing Diagram, 12-Bit Parallel Read
-10-
REV.
AD7870/AD7875/AD7876
Figure Mode Timing Diagram, Byte Serial Read
Mode timing diagram byte serial data shown Figure two-byte data read, lower byte (DB0-DB7) accessed first since HBEN must start conversion. behaves like slow memory this first read, second read access upper byte data normal read. Operation serial functions identical between Mode Mode timing diagram Figure shows both noncontinuously continuously running SCLK (dashed line).
DYNAMIC SPECIFICATIONS
sine-wave signal very distortion input which sampled sampling rate. Fast Fourier Transform (FFT) plot generated from which data obtained. Figure shows typical 2048 point plot AD7870KN/AD7875KN with input signal sampling frequency kHz. obtained from this graph 72.6 should noted that harmonics taken into account when calculating SNR.
AD7870 AD7875 specified 100% tested dynamic performance specifications well traditional specifications such integral differential nonlinearity. Although AD7876 production tested parameters, dynamic performance similar AD7870 AD7875. specifications required signal processing applications such speech recognition, spectrum analysis high speed modems. These applications require information ADC's effect spectral content input signal. Hence, parameters which AD7870 AD7875 specified include SNR, harmonic distortion, intermodulation distortion peak harmonics. These terms discussed more detail following sections.
Signal-to-Noise Ratio (SNR)
measured signal-to-noise ratio output ADC. signal magnitude fundamental. Noise nonfundamental signals half sampling frequency (FS/2) excluding dependent upon number quantization levels used digitization process; more levels, smaller quantization noise. theoretical signal noise ratio sine wave input given
(6.02N 1.76)
Figure Plot
Effective Number Bits
where number bits. Thus ideal 12-bit converter, output spectrum from evaluated applying REV.
formula given relates number bits. Rewriting formula, (2), possible measure performance expressed effective number bits (N). 1.76 6.02 effective number bits device calculated directly from measured SNR. -11-
AD7870/AD7875/AD7876
Figure shows typical plot effective number bits versus frequency AD7870KN/AD7875KN with sampling frequency kHz. effective number bits typically falls between 11.7 11.85 corresponding figures 72.2 73.1
Figure Effective Number Bits Frequency
Total Harmonic Distortion (THD)
ratio harmonics value fundamental. AD7870/AD7875, defined
Linearity Plot
Figure Plot
where amplitude fundamental amplitudes second through sixth harmonic. also derived from plot output spectrum.
Intermodulation Distortion
With inputs consisting sine waves frequencies, active device with nonlinearities will create distortion products difference frequencies where etc. Intermodulation terms those which neither equal zero. example, second order terms include while third order terms include (2fa fb), (2fa fb), 2fb) 2fb). Using CCIF standard where input frequencies near input bandwidth used, second third order terms different significance. second order terms usually distanced frequency from original sine waves while third order terms usually frequency close input frequencies. result, second third order terms specified separately. calculation intermodulation distortion specification where ratio individual distortion products amplitude fundamental expressed dBs. this case, input consists two, equal amplitude, distortion sine waves. Figure shows typical plot AD7870/ AD7875.
Peak Harmonic Spurious Noise
When sine wave specified frequency applied input AD7870/AD7875 several million samples taken, histogram showing frequency occurrence each 4096 codes generated. From this histogram data possible generate integral linearity plot shown Figure This shows very good integral linearity performance from AD7870/AD7875 input frequency kHz. absence large spikes plot shows good differential linearity. Simplified versions formulae used outlined below. INL(i)
4096
where INL(i) integral linearity code V(fs) V(o) estimated full-scale offset transitions V(i) estimated transition code. V(i) estimated code transition point derived follows: V(i)
cum(i
where peak signal amplitude, number histogram samples cum(i) in=0V(n) occurrences
Peak harmonic spurious noise defined ratio value next largest component output spectrum FS/2 excluding value fundamental. Normally, value this specification will determined largest harmonic spectrum, parts where harmonics buried noise floor peak will noise peak.
Figure Plot
-12-
REV.
AD7870/AD7875/AD7876
MICROPROCESSOR INTERFACE
AD7870/AD7875/AD7876 wide variety interfacing options. offers operating modes three data-output formats. Fast data access times allow direct interfacing most microprocessors including processors.
Parallel Read Interfacing
Figures show interfaces ADSP-2100, TMS32010 TMS32020 processors. operating Mode parallel read three interfaces. external timer controls conversion start asynchronously microprocessor. each conversion BUSY/INT interrupts microprocessor. conversion result read from with following instruction: ADSP-2100: DM(ADC) TMS32010: D,ADC TMS32020: D,ADC ADSP-2100 Register Data Memory Address AD7870/AD7875/AD7876 Address Some applications require that conversions initiated microprocessor rather than external timer. option decode CONVST signal from address that write operation starts conversion. Data read conversion described earlier. Note, read operation must attempted during conversion.
Figure TMS32020 Parallel Interface
Byte Read Interfacing
68008 Interface Figure shows 8-bit interface MC68008 microprocessor. this interface, 12/8/CLK input tied DB11/HBEN driven from microprocessor least significant address bit. Conversion start control provided microprocessor. this interface example, Move instruction from address both starts conversion reads conversion result. MOVEW ADC,DO AD7870/AD7875/AD7876 address 68008 register This byte read instruction. During first read operation, BUSY conjunction with forces microprocessor WAIT conversion. conversion byte (DB7-DB0) loaded into D15-D8 register high byte (DB15-DB7) loaded into D7-D0 register. following Rotate instruction register swaps high bytes correct format. Note, while executing byte read instruction above, WAIT states inserted during first read operation only second.
Figure ADSP-2100 Parallel Interface
Figure TMS32010 Parallel Interface
Figure MC68008 Byte Interface
REV.
-13-
AD7870/AD7875/AD7876
Serial Interfacing
Figures show AD7870/AD7875/AD7876 configured serial interfacing. four interfaces, configured Mode operation. interfaces show timer driving CONVST input, this could generated from decoded address required. SCLK, SDAT SSTRB open-drain outputs. these required drive capacitive loads excess buffering recommended. DSP56000 Serial Interface Figure shows serial interface between AD7870/ AD7875/AD7876 DSP56000. interface arrangement two-wire with configured noncontinuous clock operation (12/8/CLK DSP56000 configured normal mode asynchronous operation with gated clock. also 16-bit word with inputs control this configuration, DSP56000 assumes valid data first falling edge SCK. Since provides valid data this first edge, there need strobe framing pulse data. SCLK SDATA gated when performing conversion. During conversion, data valid SDATA output clocked into receive data shift register DSP56000. When this register received bits data, generates internal interrupt DSP56000 read data from register.
Figure NEC7720 Serial Interface
TMS32020 Serial Interface Figure shows serial interface between AD7870/ AD7875/ AD7876 TMS32020. AD7870/AD7875/AD7876 configured continuous clock operation. Note, will interface correctly TMS32020 configured noncontinuous clock. Data clocked into data receive register (DRR) TMS32020 during conversion. with previous interfaces, when 16-bit word received TMS32020 generates internal interrupt read data from DRR.
Figure TMS32020 Serial Interface
Figure DSP56000 Serial Interface
DSP56000 AD7870/AD7875/AD7876 also configured continuous clock operation (12/8/CLK this case, strobe pulse required DSP56000 indicate when data valid. SSTRB output inverted applied input DSP56000 provide this strobe pulse. other conditions connections same gated clock operation. NEC7720/77230 Serial Interface serial interface between AD7870/AD7875/AD7876 NEC7720 shown Figure interface shown, configured continuous clock operation. This changed noncontinuous clock simply tying 12/8/ input with other connections remaining same. NEC7720 expects valid data rising edge input therefore inverter required SCLK output ADC. NEC7720 configured 16-bit data word. Once bits data have been received register NEC7720, internal interrupt generated read contents register. NEC77230 interface similar that just outlined NEC7720. However, clock input NEC77230 SICLK. Additionally, inverter required between SCLK output this SICLK input since NEC77230 assumes data valid falling edge SICLK.
ADSP-2101/ADSP-2102 Serial Interface Figure shows serial interface between AD7870/AD7875/ AD7876 ADSP-2101/ADSP-2102. configured continuous clock operation. Data clocked into serial port register ADSP-2101/ADSP-2102 during conversion. with previous interfaces, when 16-bit data word received ADSP-2101/ADSP-2102 internal microprocessor interrupt generated data read from serial port register.
Figure ADSP-2101/ADSP-2102 Serial Interface
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AD7870/AD7875/AD7876
STAND-ALONE OPERATION AD7870/AD7875/AD7876 used Mode parallel interface mode stand-alone operation. this case, conversion initiated with pulse input. This pulse must longer than conversion time ADC. BUSY output used drive input. Data latched from DB0-DB11 outputs external latch rising edge BUSY. grounds between signal source appears error voltage series with input signal.
DATA ACQUISITION BOARD
Figure shows AD7870/AD7875/AD7876 data acquisition circuit. corresponding printed circuit board (PCB) layout silkscreen shown Figures board layout three interface ports: serial parallel. parallel ports directly compatible with ADSP-2100 evaluation board expansion connector. only additional component required full data acquisition system antialiasing filter. There component grid provided near analog input which used such filter other input conditioning circuitry. facilitate this option there shorting plug (labelled PCB) analog input track. this shorting plug used, analog input connects buffer amplifier driving ADC; this shorting plug omitted, wire link used connect analog input component grid.
INTERFACE CONNECTIONS
Figure Stand-Alone Operation
APPLICATION HINTS
Good printed circuit board (PCB) layout important overall circuit design itself achieving high speed performance. designer conscious noise both itself preceding analog circuitry. Switching mode power supplies recommended switching spikes will feed through comparator causing noisy code transitions. Other causes concern ground loops digital feedthrough from microprocessors. These factors which influence ADC, proper layout which minimizes these effects essential best performance.
LAYOUT HINTS
There parallel connectors labeled SKT4 SKT6 serial connector labeled SKT5. shorting plug option (LK3 Figure 12/8/CLK input configures appropriate interface (see Function Description). SKT6 96-contact (3-ROW) Eurocard connector which directly compatible with ADSP-2100 Evaluation Board Prototype Expansion Connector. expansion connector ADSP-2100 eight decoded chip enable outputs labeled ECE1 ECE8. ECE6 used drive input data acquisition board. avoid selecting board sockets same time, ADSP-2100 board must removed. addition, ADSP-2100 expansion connector four interrupts labelled EIRQ0 EIRQ3. BUSY/ output connects EIRQ0. There single wait state generator connected EDMACK allow interface faster versions ADSP-2100. SKT4 26-way (2-ROW) connector. This connector contains signal contacts SKT6 with exception EDMACK which connected SKT6 only. also contains decoded STRB inputs which necessary TMS32020 interfacing. SKT4 pinout shown Figure
Ensure that layout printed circuit board digital analog signal lines separated much possible. Take care digital track alongside analog signal track. Guard (screen) analog input with AGND. Establish single point analog ground (star ground) separate from logic system ground AGND close possible ADC. Connect other grounds AD7870/AD7875/AD7876 DGND this single analog ground point. connect other digital grounds this analog ground point. impedance analog digital power supply common returns essential noise operation ADC, make foil width these tracks wide possible. ground planes minimizes impedance paths also guards analog circuitry from digital noise. circuit layout Figures have both analog digital ground planes which kept separated only joined together AD7870/ AD7875/AD7876 AGND pin.
NOISE
Keep input signal leads signal return leads from AGND short possible minimize input noise coupling. applications where this possible, shielded cable between source ADC. Reduce ground circuit impedance much possible since potential difference REV. -15-
Figure SKT4, Connector Pinout
AD7870/AD7875/AD7876
SKT5 D-type connector which meant serial interfacing only. inverted DB9/SCLK output also provided this connector systems which accept data rising clock edge. SKT5 pinout shown Figure SKT1, SKT2 SKT3 three connectors which provide input connections analog input, CONVST input external clock input. external clock source optional, there shorting plug (LK2) input which must connected either (for ADCs internal clock) SKT3.
POWER SUPPLY CONNECTIONS
requires analog power supplies digital supply analog supplies labelled range both supplies (see silkscreen Figure 29). Connection digital supply made through connectors (SKT4 SKT6). supply required generated from voltage regulator power supply input (IC3 Figure 27).
Figure SKT5, D-Type Connector Pinout
SHORTING PLUG OPTIONS
COMPONENT LIST
There seven shorting plug options which must before using board. These outlined below: Connects analog input buffer amplifier. analog input also connected component grid signal conditioning. Selects either internal clock external clock source. Configures 12/8/CLK input appropriate serial parallel interface. Connects input directly parallel connectors decoded STRB input. This shorting plug setting depends microprocessor e.g., TMS32010 separate output while TMS32020 STRB outputs. LK5- Connect pull-up resistors SSTRB, SCLK SDATA. These shorting plugs should removed parallel interfacing.
C10, R3*, LK1, LK3, LK5, LK6, SKT1, SKT2, SKT3 SKT4 SKT5 SKT6
AD711 AD7870/AD7875/AD7876 Analog-toDigital Converter MC79L05 Regulator 74HC00 Quad NAND Gate 74HC74 Dual D-Type Flip Flop Capacitors Capacitors Pull-Up Resistors Pull-Up Resistors Pull-Up Resistor Shorting Plugs
Sockets 26-Contact (2-Row) Connector 9-Contact D-Type Connector 96-Contact (3-Row) Eurocard Connector
*Required Serial Communication only.
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AD7870/AD7875/AD7876
Figure Data Acquisition Circuit Using AD7870/AD7875/AD7876
Figure Silkscreen Figure
REV.
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AD7870/AD7875/AD7876
Figure Component Side Layout Figure
Figure Solder Side Layout Figure
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AD7870/AD7875/AD7876
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
24-Pin Plastic (N-24)
28-Pin PLCC (P-28A)
24-Pin Cerdip (Q-24)
24-Pin SOIC (R-24)
REV.
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C1336-10-8/90
PRINTED U.S.A.

FEATURES Complete Monolithic 12-Bit with: Track/Hold Amplifier Convert

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