Cypress EZ-USB family contains high-performance 8051 core that feature

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Cypress EZ-USB family contains high-performance 8051 core that feature

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EZ-USB Ports
Cypress EZ-USB family contains high-performance 8051 core that features 24-MHz operation, 4-clock cycles, bytes internal register RAM, expanded interrupts, UARTS data pointers. While EZ-USB most respects standard (but enhanced) 8051 processor, there some architectural differences that must accounted when writing firmware. major architectural difference that ports implemented differently than standard 8051. This note explains differences, concludes with code example waveforms using `MOVX @R0' instruction. differences ports follows: 8051 uses three SFRS (Special Function Registers) control three ports EZ-USB family does implement P0-P3. Instead, implements three different ports PORTA, PORTB, PORTC, controls them using added registers external (`MOVX') memory space. 8051 implements "quasi-bidirectional" pin, while EZ-USB chip explicitly sets direction using added register bits. Both 8051 EZ-USB chip multiplex port alternate functions onto pins. 8051 switches between special function port setting port HIGH, effectively turning input that special function override state. EZ-USB chip selects between port special functions (such UART TxD) using added register bits. PORTACFG RxD1OUT OEA7 OUTA OUTA7 PINSA PINA7 PINA6 PINA5 PINA4 OUTA6 OUTA5 OEA6 OEA5 RxD0OUT Port Configuration T1OUT T0OUT 7F9C OEA2 OEA1 OEA0 7F96 OUTA2 OUTA1 OUTA0 7F99 PINA3 PINA2 PINA1 PINA0 During `MOVX @R0' `MOVX @R1' instruction 8051 sends contents port upper address lines A[15.0], contents lower address lines A[7.0]. Since EZ-USB chip does have high address byte instead provided added location 92H.
EZ-USB Port Details
Figure shows basic structure EZ-USB pin, followed registers PORTA. There corresponding registers PORTB PORTC.
Alternate Function
PINS
Figure EZ-USB Input/Output
7F93
Port Output Enable OEA4 OEA3
Port Outputs OUTA4 OUTA3
Port Pins
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EZ-USB Ports
four registers that control PORTA have following functions: PORTACFG register bits select either PORTA pins (bit=0) indicated alternate function (bit=1). default these bits register bits individually enable eight PORTA output buffers (1=enabled). OUTA register bits stored latches that connected pin, depending states PORTACFG pins (the direction alternate function overrides setting). PINSA register bits indicate states regardless configuration: port input, port output, alternate function.
DPTR 8051 Instructions that DPTR operates identically 8051 EZ-USB family. example, instruction, `MOVX @DPTR' does following: Outputs 16-bit contents DPTR address bus. Floats data read operation. Generates strobe. Reads contents data into accumulator. R0/R1 similar 8051 indirect address mode uses supply address byte. Where does upper address byte come from? high byte comes from different places 8051 EZ-USB family, illustrated Figure 8051, upper address byte provided from port register. previously mentioned, EZ-USB chips implement instead implement ports PORTA, PORTB, PORTC using memory-mapped control registers. Since port does exist, EZ-USB 8051 core implements Special Function Register (SFR) location 0x92 whose only purpose supply upper address byte `MOVX @R0/R1' instructions.
`MOVX @R0/R1' Instruction
8051 indirect address modes. uses data pointer (DPTR) 16-bit index register, other uses register 8-bit index register. Data transferred from outside memory using `MOVX' (move external) instruction conjunction with symbol indicate indirect addressing.
8051
EZ-U
0x92
Figure Different Registers Supply Upper Address A[15.8]
Listing
movxtest.a51 18-Nov-98 test movx instruction AN2131 ;-$NOMOD51 disable predefined 8051 registers $nolist $INCLUDE (REG320.INC) $include (ezregs.inc) $list MOVXPAGE NAME movxtest ISEG stack stack: CSEG absolute Segment Address LJMP start Jump over interrupt vectors
EZ-USB Ports
100h -start: SP,#STACK-1 stack dptr,#PORTCCFG a,#11000000b read write strobes movx @dptr,a dptr,#OEC output enables, port movx @dptr,a same bits, b7-b6 a,#80H somewhere external memory MOVXPAGE,a MPAGE register loop: movx @r0,a write data sjmp loop
This code illustrates `movx @r0' instruction. location 0x92 named "MOVXPAGE" line following statements enable strobes: Lines 24-26: PORTCFG bits select alternate functions (RD# WR#). Only pulse used this example. Lines 27-28: PORTC.7 PORTC.6 output buffers enabled.
MOVXPAGE register initialized off-chip upper address byte 0x80 line Then continuous loop writes accumulator external memory, increments accumulator, repeats. This example meant only show timing data strobes, contents unimportant. Normally would also initialized reflect lower external address byte. Figure shows line data example code. D[0] line toggles every write, expected.
Figure Waveforms Data
Cypress Semiconductor Corporation, 2000. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

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