SST37VF512 SST37VF010 SST37VF020 SST37VF040 FEATURES: Organized 1
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Kbit Mbit Mbit Mbit (x8) Many-Time Programmable Flash
SST37VF512 SST37VF010 SST37VF020 SST37VF040
FEATURES: Organized 128K 256K 512K 2.7-3.6V Read Operation Superior Reliability Endurance: least 1000 Cycles Greater than years Data Retention Power Consumption Active Current: (typical) Standby Current: (typical) Fast Read Access Time Fast Byte-Program Operation Byte-Program Time: (typical) Chip-Program Time: seconds (typical) SST37VF512 seconds (typical) SST37VF010 seconds (typical) SST37VF020 seconds (typical) SST37VF040 Electrical Erase Using Programmer Does require source Chip-Erase Time: (typical) CMOS Compatibility JEDEC Standard Byte-wide Flash EEPROM Pinouts Packages Available 32-Pin PDIP 32-Pin PLCC 32-Pin TSOP (8mm 14mm) PRODUCT DESCRIPTION SST37VF512/010/020/040 devices 128K 256K 512K CMOS, Many-Time Programmable (MTP), cost flash, manufactured with SST's proprietary, high performance CMOS SuperFlash technology. split-gate cell design thick oxide tunneling injector attain better reliability manufacturability compared with alternate approaches. SST37VF512/010/020/040 electrically erased programmed least 1000 times using external programmer, e.g., change contents devices inventory. SST37VF512/010/020/040 have erased prior programming. These devices conform JEDEC standard pinouts byte-wide flash memories. Featuring high performance Byte-Program, SST37VF512/010/020/040 provide typical Byte-Program time Designed, manufactured, tested wide spectrum applications, these devices offered with endurance least 1000 cycles. Data retention rated greater than years. SST37VF512/010/020/040 suited applications that require infrequent writes power nonvolatile storage. These devices will improve flexibility, efficiency, performance while matching cost nonvolatile applications that currently UV-EPROMs, OTPs, mask ROMs. meet surface mount conventional through hole requirements, SST37VF512/010/020/040 offered 32-pin PLCC, PDIP TSOP packages. Figures pinouts. Device Operation SST37VF512/010/020/040 devices nonvolatile memory solutions that used instead standard flash devices in-system programmability required. functionally (Read) compatible with industry standard flash products.The device supports electrical Erase operation external programmer. Read Read operation SST37VF512/010/020/040 controlled OE#. Both have system obtain data from outputs. Once address stable, address access time equal delay from output (TCE). Data available output after delay from falling edge OE#, assuming been addresses have been stable least TOE. When high, chip deselected standby current only (typical) consumed. output control used gate data from output pins. data high impedance state when either VIH. Refer Figure timing diagram. Byte-Program Operation SST37VF512/010/020/040 programmed using external programmer. programming mode activated asserting (±5%) pin. device programmed using single pulse (WE# low) byte. Using programming algorithm, Byte-Program process continues byte-by-byte until entire chip been programmed. Refer Figure flowchart Figure timing diagram.
2000 Silicon Storage Technology, Inc.The logo SuperFlash registered trademarks Silicon Storage Technology, Inc. trademark Silicon Storage Technology, Inc. 397-03 2/00 These specifications subject change without notice.
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet Chip-Erase Operation only change data from electrical erase that changes every device "1". SST37VF512/010/020/040 electrical ChipErase operation. entire chip erased (WE# low). order activate erase mode, (±5%) applied pins while low. other address data pins "don't care". falling edge will start Chip-Erase operation. Once chip been erased, bytes must verified Refer Figure flowchart Figure timing diagram. Product Identification Mode Product Identification mode identifies devices SST37VF512, SST37VF010, SST37VF020, SST37VF040 manufacturer SST. This mode accessed hardware method. activate this mode, programming equipment must force (12V±5%) address identifier bytes then sequenced from device outputs toggling address line details, Table hardware operation. FUNCTIONAL BLOCK DIAGRAM TABLE PRODUCT IDENTIFICATION TABLE Byte Manufacturer's Code 0000 Device Code SST37VF512 0001 SST37VF010 0001 SST37VF020 0001 SST37VF040 0001
Data
T1.1
Design Considerations SST37VF512/010/020/040 should have 0.1µF ceramic high frequency, inductance capacitor connected between GND. This capacitor should placed close package terminals possible. must remain stable entire duration Erase operation. must remain stable entire duration Program operation.
X-Decoder
EEPROM Cell Array
Memory Address
Address Buffer Y-Decoder
Control Logic
Buffers
B1.0
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512
SST37VF512 SST37VF010 SST37VF020 SST37VF040
F01.0
Standard Pinout View
FIGURE ASSIGNMENTS 32-PIN TSOP
SST37VF040 SST37VF020 SST37VF010 SST37VF512 32-Pin PDIP View
SST37VF512 SST37VF010 SST37VF020 SST37VF040
F02b.0
FIGURE ASSIGNMENTS 32-PIN PDIP
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512
SST37VF512 SST37VF010 SST37VF020 SST37VF040
SST37VF040 SST37VF020 SST37VF010 SST37VF512
32-Pin PLCC View
F02a.1
FIGURE ASSIGNMENTS 32-PIN PLCC TABLE DESCRIPTION Symbol Name Address Inputs AMS-A0 DQ7-DQ0 Data Input/Output
Note:
Chip Enable Write Enable Output Enable Power Supply Ground Connection
Functions provide memory addresses output data during Read cycles receive input data during Program cycle, outputs tri-state when high. activate device when program erase (WE# pulse during Program Erase) gate data output buffers during Read operation when provide 3-volt supply (2.7 3.6V) Unconnected pins
T2.0
Most significant address SST37VF512, SST37VF010, SST37VF020 SST37VF040.
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet TABLE OPERATION MODES SELECTION Mode Read Output Disable Standby Chip-Erase Byte-Program Program/Erase Inhibit Product Identification
Note:
DOUT High High High High High Z/DOUT Manufacturer Code (BF) Device Code
Address AMS(2)-A1 VIL, AMS(2)-A1 VIL,
T3.0
case 12V±5% Device code SST37VF512, SST37VF010, SST37VF020 SST37VF040. Most significant address SST37VF512, SST37VF010, SST37VF020 SST37VF040.
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" cause permanent damage device. This stress rating only functional operation device these conditions conditions greater than those defined operational sections this data sheet implied. Exposure absolute maximum stress rating conditions affect device reliability.) Temperature Under Bias -55°C +125°C Storage Temperature -65°C +150°C Voltage Ground Potential -0.5V VDD+ 0.5V Transient Voltage (<20 Ground Potential -1.0V VDD+ 1.0V Voltage Ground Potential -0.5V 13.2V Package Power Dissipation Capability 25°C) 1.0W Through Hole Lead Soldering Temperature Seconds) 300°C Surface Mount Lead Soldering Temperature Seconds) 240°C Output Short Circuit Current(1)
Note: Outputs shorted more than second. more than output shorted time.
OPERATING RANGE Range Ambient Temp Commercial +70°C Industrial -40°C +85°C
CONDITIONS TEST 3.6V 3.6V Input Rise/Fall Time Output Load Figures
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet TABLE READ MODE OPERATING CHARACTERISTICS 3.6V, 70°C (Commercial) Limits Symbol Parameter Read Current
Units
VIHC
Standby Current Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Input High Voltage VDD-0.3 (CMOS) Output Voltage Output High Voltage VDD-0.2 Supervoltage Current Read-ID
Test Conditions VIL, I/Os open, Address Input VIL/VIH, 1/TRC Min, VIHC VDD, VOUT VDD, 100µA, -100 VIL, Max.
T4.1
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet TABLE PROGRAM/ERASE OPERATING CHARACTERISTICS 3.6V, 25°C Limits Symbol Parameter Units Erase Program Current Input Leakage Current Output Leakage Current Supervoltage 11.4 12.6 Supervoltage Current
Test Conditions VIL, Max, VDD, VOUT VDD,
Max, Max, Max,
T5.0
TABLE RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter TPU-READ Power-up Read Operation TPU-WRITE Power-up Write Operation
Minimum Units
T6.0
T7.0
TABLE CAPACITANCE MHz, other pins open) Parameter Description Test Condition CI/O Capacitance VI/O CIN(1) Input Capacitance
Maximum
Note: (1)This parameter measured only initial qualification after design process change that could affect this parameter.
TABLE RELIABILITY CHARACTERISTICS Symbol Parameter NEND Endurance TDR(1) Data Retention VZAP_HBM Susceptibility Human Body Model VZAP_MM Susceptibility Machine Model ILTH Latch
Note:
Minimum Specification 1000 2000
Units Cycles Years Volts Volts
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard
T8.1
This parameter measured only initial qualification after design process change that could affect this parameter.
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet CHARACTERISTICS TABLE READ CYCLE TIMING PARAMETERS 3.6V, 70°C (Commercial) SST37VF512-70 SST37VF010-70 SST37VF020-70 SST37VF040-70 Symbol Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time TCLZ Active Output Active Output TOLZ TCHZ High High-Z Output TOHZ High High-Z Output Output Hold from Address Change
SST37VF512-90 SST37VF010-90 SST37VF020-90 SST37VF040-90
Units
T9.1
TABLE PROGRAM/ERASE CYCLE TIMING PARAMETERS 3.6V, 25°C Symbol Parameter Program Cycle Time TCES Setup Time TCEH Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time TPRT Rise Time Program Erase TVPS Setup Time Program Erase TVPH Hold Time Program Erase Program Pulse Width Erase Pulse Width OE#/A9 Recovery Time Erase TART Rise Time during Erase TA9S Setup Time during Erase TA9H Hold Time during Erase
Units
T10.0
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
ADDRESS
DATA VALID TCHZ HIGH-Z DATA VALID TOLZ TOHZ
F03.0
DQ7-0
HIGH-Z
TCLZ
FIGURE READ CYCLE TIMING DIAGRAM
ADDRESS (EXCEPT
TCEH
DQ7-0 TART TA9H TCES
F04.0
TVPS TVPH TPRT TA9S
FIGURE CHIP-ERASE TIMING DIAGRAM
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
ADDRESS
ADDRESS VALID
TCEH
DQ7-0
HIGH-Z
DATA VALID
TVPS TPRT
TVPH
TCES
F05.0
FIGURE BYTE-PROGRAM TIMING DIAGRAM
VIHT
INPUT
REFERENCE POINTS
OUTPUT
VILT
F06.1
test inputs driven VIHT (0.9 VDD) logic VILT (0.1 VDD) logic "0". Measurement reference points inputs outputs (0.5 VDD) (0.5 VDD). Inputs rise fall times (10% 90%)
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT Test
FIGURE INPUT/OUTPUT REFERENCE WAVEFORMS
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
TESTER
F07.1
FIGURE TEST LOAD EXAMPLE
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Start
Erase 100ms pulse (WE# VIL)
OE#/A9
Wait Recovery Time
Read Device
Compare bytes
Device Passed
Device Failed
F08.0
FIGURE CHIP-ERASE ALGORITHM
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Start
Figure
Erase
Address First Location; Load Data
Program 10µs pulse (WE# VIL)
Increment Address
Last Address?
Wait
Read Device
Compare bytes original data
Device Passed
Device Failed
F09.0
FIGURE BYTE-PROGRAM ALGORITHM
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet PRODUCT ORDERING INFORMATION Device SST37VFxxx Speed Suffix1 Suffix2 Package Modifier pins Numeric modifier Package Type PDIP PLCC TSOP x14mm Operating Temperature Commercial 70°C Industrial -40° 85°C Minimum Endurance 1000 cycles Read Access Speed Device Density Kilobit Megabit Megabit Megabit SST37VF512 Valid combinations SST37VF512-70-3C-WH SST37VF512-70-3C-NH SST37VF512-90-3C-WH SST37VF512-90-3C-NH SST37VF512-70-3I-WH SST37VF512-70-3I-NH SST37VF512-90-3I-WH SST37VF512-90-3I-NH SST37VF010 Valid combinations SST37VF010-70-3C-WH SST37VF010-70-3C-NH SST37VF010-90-3C-WH SST37VF010-90-3C-NH SST37VF010-70-3I-WH SST37VF010-70-3I-NH SST37VF010-90-3I-WH SST37VF010-90-3I-NH SST37VF020 Valid combinations SST37VF020-70-3C-WH SST37VF020-70-3C-NH SST37VF020-90-3C-WH SST37VF020-90-3C-NH SST37VF020-70-3I-WH SST37VF020-70-3I-NH SST37VF020-90-3I-WH SST37VF020-90-3I-NH SST37VF040 Valid combinations SST37VF040-70-3C-WH SST37VF040-70-3C-NH SST37VF040-90-3C-WH SST37VF040-90-3C-NH SST37VF040-70-3I-WH SST37VF040-70-3I-NH SST37VF040-90-3I-WH SST37VF040-90-3I-NH
SST37VF512-90-3C-PH
SST37VF010-90-3C-PH
SST37VF020-90-3C-PH
SST37VF040-90-3C-PH
Example:Valid combinations those products mass production will mass production. Consult your sales representative confirm availability valid combinations determine availability combinations.
2000 Silicon Storage Technology, Inc.
397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
Data Sheet PACKAGING DIAGRAMS
IDENTIFIER 1.05 0.95
8.10 7.90
.270 .170
12.50 12.30
0.15 0.05
0.70 0.50
14.20 13.80
Note:
Complies with JEDEC publication MO-142 dimensions, although some dimensions more stringent. linear dimensions millimeters (min/max). Coplanarity: (±.05)
32.TSOP-WH-ILL.3
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) PACKAGE CODE:
index
.600 .625 .530 .550
.065 .075
1.645 1.655
PLCS.
Base Plane Seating Plane
.015 .050 .120 .150
.170 .200
.008 .012 .600
.070 .080
.045 .065
.016 .022
.100
Note:
Complies with JEDEC publication MO-015 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .010 inches.
32.pdipPH-ILL.1
32-PIN PLASTIC DUAL-IN-LINE PACKAGE (PDIP) PACKAGE CODE:
2000 Silicon Storage Technology, Inc. 397-03 2/00
Kbit Mbit Mbit Mbit Many-Time Programmable Flash SST37VF512 SST37VF010 SST37VF020 SST37VF040
VIEW
SIDE VIEW
BOTTOM VIEW
Optional Identifier
.485 .495 .447 .453 .042 .048
.106 .112 .020 MAX. .023 .029 .030 .040
.042 .048 .585 .595 .547 .553 .026 .032
.013 .021 .400
.490 .530
.050 BSC. .015 Min. .050 BSC. .125 .140 .075 .095 .026 .032
Note:
Complies with JEDEC publication MS-016 dimensions, although some dimensions more stringent. linear dimensions inches (min/max). Dimensions include mold flash. Maximum allowable mold flash .008 inches.
32.PLCC.NH-ILL.1
32-PIN PLASTIC LEAD CHIP CARRIER (PLCC) PACKAGE CODE:
Silicon Storage Technology, Inc. 1171 Sonora Court Sunnyvale, 94086 Telephone 408-735-9110 408-735-9036 www.SuperFlash.com www.ssti.com Literature FaxBack 888-221-1178, International 732-544-2873
2000 Silicon Storage Technology, Inc.
397-03 2/00
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