/#07#. %*#26'4 +06'44726INTRODUCTION Z8PLUS core allows

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Z8PLUS core allows different interrupts from variety sources: external inputs on-chip peripherals software
Interrupts masked using Interrupt Mask Register. interrupts globally disabled setting master Interrupt Enable, Interrupt Mask Register, with Disable Interrupt (DI) instruction. Interrupts globally enabled setting with Enable Interrupt (EI) instruction. There four interrupt control registers: Interrupt Request Registers (IREQ IREQ2) Interrupt Mask registers (IMASK IMASK2). Figure shows addresses identifiers interrupt control registers. Figure block diagram showing Interrupt Mask Interrupt Priority logic.
0FBH 0FAH 0F9H 0F8H Identifier IMASK IREQ IMASK2 IREQ2
Register Interrupt Mask Interrupt Request Interrupt Mask Interrupt Request
Figure 4-1. Interrupt Control Register Addresses Identifiers
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Z8PLUS family supports both vectored polled interrupt handling. Details vectored polled interrupts found later this chapter.
IRQ7-IRQ14 Register Interrupt Mask Interrupt Request Interrupt Mask Interrupt Request Interrupt Edge Select Identifier
IREQ
IRQ0-IRQ6 IREQ2
0FBH IMASK 0FAH IREQ 0F9H IMASK2 0F8H IREQ2 0DEH PTBEDG Interrupt Request
IMASK2 Global Interrupt Enable
IMASK
Fixed Priority Logic
Vector Select
Figure 4-2. Interrupt Block Diagram NOTE: selected Z8PLUS MCU's product specification exact interrupt sources supported.
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INTERRUPT SOURCES
Table presents interrupt types, sources, vectors available Z8E001. Other processors from Z8PLUS family define interrupts differently.
Table 4-1. Z8E001 Interrupt Types, Sources, Vectors Name IREQ0 IREQ1 IREQ2 IREQ3 IREQ4 IREQ5 IREQ6 IREQ15 Sources Timer0 Time-out High-to-Low Transition Timer1 Time-out High-to-Low Transition Low-to-High Transition Timer2 Time-out Reserved Vector Location Internal External (PB4), Edge Triggered Internal External (PB2), Edge Triggered External (PB4), Edge Triggered Internal Reserved future expansion Comments Fixed Priority (Highest) (Lowest)
External Interrupt Sources
External sources generated transition corresponding Port pin. interrupt detect rising edge, falling edge, both. NOTES: interrupt sources trigger conditions device dependent. device product specification determine available sources (internal external), triggering edge options, exact programming details. Although interrupts edge triggered, minimum interrupt request High times must observed proper operation. device product specification exact timing requirements external interrupt requests (TWIL, TWIH).
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Internal Interrupt Sources
Internal interrupt sources trigger conditions device dependent. On-chip peripherals interrupt under various conditions. Some peripherals always their corresponding IREQ while others must specifically configured device product specification determine available sources, triggering edge options, exact programming details. more details interrupt sources, refer chapters describing timers, comparators, ports, other peripherals.
INTERRUPT REQUEST (IREQ) REGISTER LOGIC TIMING
Z8PLUS core responds interrupts retires each instruction. unmasked interrupt detected instruction being retired, Z8PLUS core does execute instruction during next instruction cycle. Z8PLUS instead selects highest priority outstanding interrupt serviced. program counter flags register pushed stack during next instruction cycle. appropriate IREQ cleared, master enable cleared fetches interrupt vector from program memory. then jumps user's interrupt routine during following cycle (See Figure 4-3).
Inst XTAL
Inst
Inst
Inst
Inst
Figure 4-3. Interrupt Service Sequence NOTES: There outstanding, unmasked interrupts. Interrupt source sets IREQ during this interval. This highest priority, unmasked IREQ, bit-sampled. flags pushed, IREQ cleared, IMASK cleared, vector fetched. JUMP interrupt vector. This portion first instruction user's interrupt service routine.
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Interrupt Mask Register (IMASK) Initialization
IMASK register individually globally enables disables interrupts (see Figure 4-4). When bits through corresponding interrupt requests enabled. IMASK2 register, bits through enable disable IRQ7 through IRQ14, respectively. master enable must before individual interrupt requests recognized. Resetting disables interrupt requests. reset instructions. automatically during interrupt service routine following execution Interrupt Return (IRET) instruction. IMASK registers reset 00H, disabling interrupts. NOTE: good programming practice directly aqssign value master enable bit. value change should always accomplished issuing instructions. Care should taken clear IMASK bits while master enable set.
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Read Write Indeterminate Undefined/Undetermined
Position
Value
Description
Disables Interrupts Enables Interrupts Disables IRQ5 Enables IRQ5 Disables IRQ5 Enables IRQ5 Disables IRQ4 Enables IRQ4 Disables IRQ3 Enables IRQ3 Disables IRQ2 Enables IRQ2 Disables IRQ1 Enables IRQ1 Disables IRQ0 Enables IRQ0
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=L/2* Figure 4-5. Interrupt Mask Register Interrupt Mask Register-IMASK2 (F9H) Reset
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Read Write Indeterminate Undefined/Undetermined
Position
Value
Description
Disables IRQ14 Enables IRQ14 Disables IRQ13 Enables IRQ13 Disables IRQ12 Enables IRQ12 Disables IRQ11 Enables IRQ11 Disables IRQ10 Enables IRQ10 Disables IRQ9 Enables IRQ9 Disables IRQ8 Enables IRQ8 Disables IRQ7 Enables IRQ7
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Interrupt Request (IREQ) Register Initialization
IREQ (see Figure 4-6) register that stores interrupt requests both vectored polled interrupts. When interrupt issued, corresponding position register assigned interrupt requests IREQ0 IREQ5, respectively. Whenever RESET executed, IREQ resister 00H. Figure 4-6. Interrupt Request Register. Interrupt Request Register-IREQ (FAH) Reset
Read Write Indeterminate Undefined/Undetermined
Position
Value
Description
Reserved,must IRQ6 reset IRQ6 IRQ5 reset IRQ5 IRQ4 reset IRQ4 IRQ3 reset IRQ3 IRQ2 reset IRQ2 IRQ1 reset IRQ1 IRQ0 reset IRQ0
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=L/2* Figure 4-7. Interrupt Request Register Interrupt Request Register 2-IREQ2 (F8H) Reset
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Read Write Indeterminate Undefined/Undetermined
Position
Value
Description
IRQ14 reset IRQ14 IRQ13 reset IRQ13 IRQ12 reset IRQ12 IRQ11 reset IRQ11 IRQ10 reset IRQ10 IRQ9 reset IRQ9 IRQ8 reset IRQ8 IRQ7 reset IRQ7
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IREQ SOFTWARE INTERRUPT GENERATION
IREQ used generate software interrupts specifying IREQ destination instruction referencing Z8PLUS Standard Register File. These software interrupts (SWI) controlled same manner hardware generated requests. other words, IMASK controls enabling each SWI. generate SWI, request IREQ following statement: IREQ,#NUMBER immediate data variable, NUMBER, position corresponding required level SWI. example, must issued when IREQ5 occurs. NUMBER must have value IREQ, #00100000B interrupt system globally enabled, IREQ5 enabled, there higher priority requests pending control transferred service routine pointed IREQ5 vector. NOTE: Note that software modify IREQ register time. Care should taken when using instruction that modifies IREQ register while interrupt sources active. software writeback always takes precedence over hardware. software writeback takes place same cycle interrupt source tries IREQ bit, interrupt lost.
VECTORED PROCESSING
Each Z8PLUS interrupt level vector. When interrupt occurs, control passes service routine pointed interrupt's vector location program memory. sequence events vectored interrupts follows: PUSH Byte Stack PUSH High Byte Stack PUSH FLAGS Stack Disable Global Interrupts (bit IMASK) Fetch High Byte Vector Fetch Byte Vector Branch Service Routine specified Vector
Figure Figure show vectored interrupt operation. 7/<:
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Stack Pointer Stack Before Interrupt
Stack Pointer Stack After Interrupt
Stack
SP-3
Stack Byte HIGH Byte FLAGS
Figure 4-8. Stacks Before After Interrupt
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Program Memory FFFFH
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Interrupt Service Routine
Value
0020H
Vector Selected Priority Logic Interrupt Vector Table 0000H
Figure 4-9. Interrupt Vector Table Location
Nesting Vectored Interrupts
Nesting vectored interrupts allows higher priority requests interrupt lower priority request. initiate vectored interrupt nesting, perform following steps during interrupt service routine: PUSH IMASK stack. Load IMASK with mask disable lower priority interrupts. Execute instruction. Proceed with interrupt processing. Execute instruction after processing complete. Restore IMASK original value POPing previous mask from stack. Execute IRET.
Depending application, some simplification above procedure possible. 7/<:
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POLLED PROCESSING
Polled interrupt processing supported masking IREQ polled. This process accomplished setting corresponding bits IMASK initiate polled processing, check appropriate bits IREQ using Test Under Mask (TM) instruction. call branch service routine. service routine services request, resets Request IREQ, branches returns back main program. example polling routine follows: IREQ,#MASKA;Test request NEXT;If request NEXT CALL SERVICE;If request there,then ;service NEXT: SERVICE:;Process Request IREQ, #MASKB ;Clear Request RET;Return next this example, IREQ2 being polled, MASKA 00000100B MASKB 11111011B.
RESET CONDITIONS
IMASK IREQ registers initialize RESET.
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