3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) Digi

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3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) Digi

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PDU53
3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)
Digitally programmable delay steps Monotonic delay-versus-address variation Precise stable delays Input outputs fully 100K-ECL interfaced buffered Available 16-pin (600 mil) socket
data delay devices, inc.
PACKAGES
PDU53-xx PDU53-xxM Military
PDU53-xxC3 PDU53-xxMC3
FUNCTIONAL DESCRIPTION
PDU53-series device 3-bit digitally programmable delay line. delay, TDA, from input (IN) output (OUT) depends address code (A2-A0) according following formula: TINC
DESCRIPTIONS
Signal Input Signal Output Address Address Address Volts Ground
where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 100ps through 3000ps, inclusively. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 40ps, whichever greater Inherent delay (TD0): 2.2ns typical Address input setup (TAIS): 2.9ns Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VEE: -5VDC 0.7V Power Supply Current: -150ma typical -2V) Minimum pulse width: total delay, whichever greater Minimum period: pulse width, whichever greater
PWIN Figure Timing Diagram
©1997 Data Delay Devices
DASH NUMBER SPECIFICATIONS
Part Number PDU53-100 PDU53-200 PDU53-250 PDU53-400 PDU53-500 PDU53-750 PDU53-1000 PDU53-1200 PDU53-1500 PDU53-2000 PDU53-2500 PDU53-3000 Incremental Delay Step (ps) 1000 1200 1500 2000 2500 3000 Total Delay Change (ns) 0.70 1.40 1.75 2.80 3.50 5.25 7.00 8.40 10.50 14.00 17.50 21.00
A2-A0
TOAX TAIS
NOTE: dash number between 3000 shown also available.
#98003
3/18/98
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU53
APPLICATION NOTES
ADDRESS UPDATE
PDU53 memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended
PACKAGE DIMENSIONS
.580 MAX. .010 ±.002
.600 ±.005
.870±.010 Lead Material: Nickel-Iron alloy PLATE
.380 MAX.
.015 TYP. .018 TYP. .070 MAX. .700±.010 Equal spaces each .100±.010 Non-Accumulative
PDU53-xx (Commercial DIP) PDU53-xxM (Military DIP)
#98003
3/18/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU53
PACKAGE DIMENSIONS (cont'd)
.020 TYP.
.040 TYP.
.010±.002
.710 .590 ±.005 MAX.
.882 ±.005 .007 ±.005
.090 .700 .880±.020
.100
.280 MAX.
.050 ±.010
PDU53-xxC3 (Commercial SMD) PDU53-xxMC3 (Military SMD)
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Address Input Setup Time Output Address Change Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TAIS TOAX PERIN PERIN PERIN PWIN PWIN PWIN UNITS TINC
Text
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -7.0 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
85C) PARAMETER High Level Output Voltage Level Output Voltage High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current SYMBOL -1.025 -1.810 -1.165 -1.810 -0.880 -1.620 -0.880 -1.475 UNITS NOTES MAX,50 MIN,
#98003
3/18/98
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU53
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): -4.5V 0.1V Input Pulse: Standard 100K levels Source Impedance: Max. Rise/Fall Time: Max. (measured between 80%) Pulse Width: PWIN 10ns Period: PERIN 100ns OUTPUT: Load: Cload: Threshold: (VOH VOL) (Rising Falling)
NOTE: above conditions test only restrict operation device.
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG OSCILLOSCOPE
ADDRESS SELECT
Test Setup
PERIN PWIN TRISE INPUT SIGNAL
TFALL
TFALL
TRISE OUTPUT SIGNAL
Timing Diagram Testing
#98003
3/18/98
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53) Digi

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