32M-BIT MASK (16/32-BIT OUTPUT) organization (word mode) (double

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32M-BIT MASK (16/32-BIT OUTPUT) organization (word mode) (double

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MX23C3222
32M-BIT MASK (16/32-BIT OUTPUT)
organization (word mode) (double word mode) Fast access time Random access: 100ns (max.) Page access: 30ns (max.) Page double words page Current Operating:100mA Standby:50uA Supply voltage 5V±10% Package SSOP (500mil)
ORDER INFORMATION
Part Access Page Access Time MX23C3222MC-10 100ns MX23C3222MC-12 120ns Time 30ns 50ns SSOP SSOP Package
DESCRIPTION
Symbol A0~A19 D0~D30 D31/A-1 Word Function Address Inputs Data Outputs (Double Word Mode)/ Address (Word Mode) Chip Enable Input Output Enable Input Double Word/ Word Mode Selection Power Supply Ground Connection
CONFIGURATION
WORD D31/A-1
MODE SELECTION
P/N:PM0358
MX23C3222
Word
D31/A-1 Output Input
D0~D15 High High D0~D15 D0~D15
D16~D31 High High D16~D31 High
Mode Double Word Word
Power Stand-by Active Active Active
REV. 2.3, FEB. 1999
MX23C3222
BLOCK DIAGRAM
A0/(A-1) WORD Address Buffer Memory Array Page Buffer Page Decoder Double Word Output Buffer D31/(D15)
ABSOLUTE MAXIMUM RATINGS
Item Voltage Relative Ambient Operating Temperature Storage Temperature Symbol Topr Tstg Ratings -1.3V VCC+2.0V (Note) -65° 125°
Note: Minimum voltage input pins -0.5V. During voltage transitions, inputs undershoot -1.3V periods 20ns. Maximum voltage input pins VCC+0.5V. During voltage transitions, input overshoot VCC+2.0V periods 20ns.
CHARACTERISTICS 70°C, 5V±10%)
Item Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (cmos) Input Capacitance Output Capacitance Symbol ICC1 ISTB1 ISTB2 COUT MIN. 2.4V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 100mA 50uA 10pF 10pF Conditions -1.0mA 2.1mA
100ns, output open CE>VCC-0.2V 1MHZ 1MHZ
P/N:PM0358
REV. 2.3, FEB. 1999
MX23C3222
CHARACTERISTICS 70°C, 5V±10%)
Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Delay Symbol tACE 23C3222-10 MIN. MAX. 100ns 100ns 100ns 30ns 30ns 20ns 23C3222-12 MIN. MAX. 120ns 120ns 120ns 50ns 50ns 20ns
Note:Output high-impedance delay (tHZ) measured from going high, this parameter guaranteed design over full voltage temperature operating range tested.
Test Conditions
Input Pulse Levels Input Rise Fall Times Input Timing Level Output Timing Level Output Load 0.4V~ 2.4V 10ns 1.5V 0.8V 2.0V Figure
(load)=-1mA DOUT (load)=2.1mA
C<100pF
Note:No output loading present tester load board. Active loading used under software programming control. Output loading capacitance includes load board's stray capacitance.
P/N:PM0358
REV. 2.3, FEB. 1999
MX23C3222
TIMING DIAGRAM
RANDOM READ
tACE
VALLID VALLID
DATA VALLID
PAGE READ
A3-A19
VALID
(A-1),A0,A1,A2
1'st
2'nd VALID VALID
3'rd
DATA
VALID
Note: enable. Page size words 16-bit mode, bytes 8-bit mode.
P/N:PM0358
REV. 2.3, FEB. 1999
MX23C3222
REVISION HISTORY
Revision Description Characteristics: 10ns Page Date FEB/01/1999
P/N:PM0358
REV. 2.3, FEB. 1999
MX23C3222
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32M-BIT MASK (16/32-BIT OUTPUT) organization (word mode) (double

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