SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation Five

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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation Five

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QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
operation Five noise CMOS level outputs <500ps output skew, Q0-Q4 Outputs 3-state reset while OE/RST disable feature frequency testing Internal loop filter network Balanced drive outputs ±36mA 80MHz maximum frequency Available QSOP package
QS5935
DESCRIPTION
QS5935 Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. Five outputs available: Q0-Q4. Careful layout design ensure <500ps skew between Q0-Q QS5935 includes internal filter which provides excellent jitter characteristics eliminates need external components. also disabled PLL_EN signal allow frequency testing. QS5935 designed cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5935 clock driver represents best value small form factor, high-performance clock management products.
FUNCTIONAL BLOCK DIAGRAM
PLL_EN
CLK_IN FEEDBAC
OE/RST
2000 Integrated Device Technology, Inc.
JULY 2000
DSC-5816/-
QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Symbol Rating AVDD, Supply Voltage Ground
Unit
Max. -0.5 -0.5 VDD+0.5 +150
OE/RST FEEDBACK CLK_IN
20-8
PLL_EN
Input Voltage TSTG Maximum Power Dissipation 85°C) Storage Temperature Range
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE 1MHz,
Pins COUT Typ. Max. Unit
QSOP VIEW
NOTE: Capacitance characterized tested.
DESCRIPTION
Name CLK_IN FEEDBACK OE/RST PLL_EN AVDD AGND Reference clock input External feedback provides flexibility different output frequency relationships Clock outputs Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled. When enabled. When disabled output will CLK_IN/2 frequency. This allows CLK_IN input single-stepped system debug. Power supply output buffers Power supply phase lock loop other internal circuitries Ground supply output buffers Ground supply phase lock loop other internal circuitries Description
QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, AVDD/VDD 5.0V
Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Output Voltage Input Hysteresis Output Leakage Current Input Leakage Current Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level -36mA -100µA Min., 36mA Min., 100µA VOUT GND, Max., Outputs Disabled AVDD GND, AVDD Max. Min. 0.75 Typ. Max. 0.45 Unit
POWER SUPPLY CHARACTERISTICS
Symbol IDDQ IDDD Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current Test Conditions Max., OE/RST LOW, CLK_IN LOW, outputs unloaded Max., 3.4V Max., Typ. Max. Unit mA/MHz
NOTE: This value guaranteed tested.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol tSKR tSKF tLOCK tPZH tPZL tPHZ tPLZ tPWC Parameter Output Skew Between Rising Edges, Q0-Q4 (2,3) Output Skew Between Falling Edges, Q0-Q4 (2,3) Pulse Width, Q0-Q4 Cycle-to-Cycle Jitter (2,5) CLK_IN Feedback Delay CLK_IN Phase Lock Output Enable Time, OE/RST HIGH Output Disable Time, OE/RST HIGH (2,4) Output Rise/Fall Times, 0.2VDD 0.8VDD Maximum Rise/Fall Times, 0.8V Input Clock Frequency Input Clock Pulse, HIGH Duty Cycle, CLK_IN
(2,6)
Min. TCYC/2 0.15
Typ.
Max. TCYC/2 +0.15 +500
Unit
NOTES: Test Loads Waveforms test load termination. This parameter guaranteed characterization tested. Skew specifications apply under identical environments (loading, temperature, VDD, device speed grade). Measured open loop mode PLL_EN Jitter characterized using oscilloscope, output 20MHz. Measurement taken cycle after jitter. measured device inputs 1.5V, output 80MHz. Input timing requirements guaranteed design tested. Where pulse width implied less than tPWC limit, tPWC limit applies.
QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TEST LOADS WAVEFORMS
7.0V
TEST CIRCUIT
TEST CIRCUIT
1.0ns
1.0ns 0.8V 0.5V 0.2V
3.0V 2.0V 0.8V
INPUT TEST WAVEFORM
DISA
CMOS OUTPUT WAVEFORM
1.5V NTRO INPU ITCH 0.5V 0.3V ITCH HIGH 0.5V 0.3V 3.5V
ENABLE DISABLE TIMES
TEST CIRCUIT used output enable/disable parameters. TEST CIRCUIT used other timing parameters.
QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
TIMING DIAGRAM
CLK_IN
NOTES: Timing Diagram applies output connected FEEDBACK parameters measured 0.5VDD except tPD, which measured 1.5V
QS5935 SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
XXXX Device Type Package Process
Blank
Industrial (-40°C +85°C)
Quarter Size Outline Package (SO20-8)
5935
Skew CMOS lock Driver with Integrated Loop Filter
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SKEW CMOS CLOCK DRIVER WITH INTEGRATED LOOP FILTER operation Five

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