GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER CMOS outputs Monitor out

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GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER CMOS outputs Monitor out

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QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CMOS outputs Monitor output Rail-to-rail output voltage swing Input hysteresis better noise margin Guaranteed skew: 0.7ns output skew (same bank) 0.8ns output skew (different banks) 1.2ns part-to-part skew Std., speed grades Available QSOP SOIC packages
QS5805/A/B
DESCRIPTION
QS5805 clock buffer/driver circuits used clock buffering schemes where skew parameter. This device offers banks five non-inverting outputs. QS5805 device provides propagation delay buffering with on-chip skew 0.7ns same-transition, same-bank signals. QS5805 characterized operation -40°C +85°C.
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
JULY 2000
DSC-4579/-
QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
GNDQ 20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature Max.
Unit
+150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
QSOP Pins COUT Typ.
+25OC, 1.0MHz,
SOIC Typ. Max. Unit Max.
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names OEA, INA, OAn, Description Output Enable Inputs Clock Inputs Clock Outputs Monitor Outputs (non-disable)
QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 5.0V 10%, 0.2V, 0.2V
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., VIL, -300µA Min., VIL, -15mA Min., VIL, -24mA IOFF Output Voltage Input Leakage Current Output Leakage Current Input Power Leakage Short Circuit Current Input Hysteresis
(2,3)
Min.
Typ.(1) -0.7
Max. -1.2 0.55
Unit
Min., VIL, 300µA Min., VIL, 64mA Max., Max., VOUT Max., VOUT VTLH VTHL Inputs
NOTES: Typical values 5.0V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Supply Current Examples (2,4) Test Conditions Max., Max., 3.4V Max., Outputs Enabled, duty cycle Max., duty cycle, 10MHz Five outputs toggling Max., duty cycle, 2.5MHz outputs toggling Typ. 0.005 3.4V 3.4V Max. 15.5 16.8 11.3 Unit mA/MHz
NOTES: conditions shown Min. Max., appropriate values specified under Electrical Characteristics. Guaranteed design tested. 0pF. Typical values reference only. Conditions 5.0V, 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs Output Frequency Number outputs
QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
QS5805 Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter Skew between outputs, same transition, same bank Skew between outputs banks, same transition Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Min. Max. QS5805A Min. Max. QS5805B Min. Max. Unit
NOTES: Skew parameters guaranteed across temperature range, tested. Skew parameters measured 0.5Vcc. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading, package, speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
QS5805 Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation Delay OAn, Output Enable Time Output Disable Time Output Rise Time Output Fall Time 0.8V 0.2Vcc 0.8Vcc 0.8V 0.2Vcc 0.8Vcc Min. Max. QS5805A Min. Max. QS5805B Min. Max. Unit
NOTES: Minimums guaranteed production tested. Timing parameters measured 0.5Vcc. propagation delay other range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew. This parameter guaranteed production tested.
QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Parameter Tested
Switch Position
tPLZ, tPZL Others Pulse Generator 50pF
Closed Open
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
PROPAGATION DELAY
INPUT tPLH tPHL 2.0V 0.5Vcc 0.8V 1.5V INPUT
PULSE SKEW tSK(P)
1.5V tPLH OUPUT tPHL 0.5Vcc tSK(p) tPLH
OUPUT
OUTPUT SKEW (SAME BANK) tSK(O1)
INPUT tPLH1 tPHL1 OUPUT 0.5Vcc tSK(01) OUPUT tSK(01) 0.5Vcc tPLH2 tPHL2 OUPUT OUPUT 1.5V INPUT
OUPUT SKEW (DIFFERENT BANKS) tSK(O2)
1.5V tPLHA tPHLA 0.5Vcc tSK(02) tSK(02) 0.5Vcc tPLHB tPHLB
tSK(01) tPLH2 tPLH1 tPHL2 tPHL1
tSK(02) tPLHB tPLHA tPHLB tPHLA
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V tPLZ 1.5V 0.3V tPHZ 0.3V PART OUTPUT PART OUTPUT DISABLE 1.5V INPUT
PART-TO-PART SKEW tSK(T)
1.5V tPLH1 tPHL1 0.5Vcc tSK(t) tSK(t) 0.5Vcc tPLH2 tPHL2
tSK(t) PLH2 tPLH1 tPHL2 tPHL1
QS5805/A/B GUARANTEED SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Quarter Size Small Outline Pacakge (SO20-8) Small Outline (SO20-2)
5805 5805A 5805B
Guaranteed Skew CMOS Clock Driver/Buffer
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