GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
JEDEC compatible LVTTL inputs outputs skew clock outputs (inverting) Monitor output Clock inputs tolerant Pinout function compatible with QS5806 Input hysteresis better noise margin Guaranteed skew 0.6ns output skew (same bank) 0.8ns output skew (different banks) 1.5ns part-to-part skew Std. speed grades Available QSOP SOIC packages
QS53806/A
DESCRIPTION
QS53806 clock driver/buffer circuit used clock buffering schemes where skew parameter. QS53806 offers banks five inverting outputs. Designed IDT's proprietary CMOS process, these devices provide propagation delay buffering with onchip skew 0.6ns same-transition, same-bank signals.
FUNCTIONAL BLOCK DIAGRAM
1999 Integrated Device Technology, Inc.
JULY 2000
DSC-5828/-
QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
GNDQ 20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. Vcc+0.5 +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
+25OC, 1.0MHz, VOUT
QSOP Pins COUT Typ. Max. SOIC Typ. Max. Unit
NOTE: This parameter guaranteed production tested.
DESCRIPTION
Names OEA, INA, OAn, Description Output Enable Inputs Clock Inputs Clock Outputs Monitor Outputs (non-disable)
QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 3.3V 0.3V
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., -100µA Min., -8mA Min., 100µA Min., 16mA Min., 24mA IOFF IODH IODL Input Leakage Current Output Leakage Current Input Power Leakage Output HIGH Current Output Current Short Circuit Current
(2,3)
Min. -0.5
Typ.(1) -0.7 -100
Max. -1.2 -200
Unit
Max., Max., VOUT 3.3V, VIL, 1.5V 3.3V, VIL, 1.5V Max., VOUT
NOTES: Typical values 3.3V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples (2,4) Test Conditions Max., Max., Max., Outputs Toggling duty cycle Max., duty cycle, 10MHz five outputs toggling Max., duty cycle, 2.5MHz outputs toggling Typ. 0.01 Max. Unit µA/MHz
NOTES: conditions shown Min. Max., appropriate values specified under Electrical Characteristics. Guaranteed design tested. 0pF. Typical values reference only. Conditions 3.3V, 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs (one two) Output Frequency Number outputs (five ten)
QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 3.3V 0.3V CLOAD 50pF, RLOAD unless otherwise noted.
QS53806 Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter Skew between outputs, same transition, same bank Skew between outputs, same transition, different banks Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Min. Max. QS53806A Min. Max. Unit
NOTES: This parameter guaranteed production tested. Skew parameters apply propagation delays only. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading package, speed grade.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 3.3V 0.3V CLOAD 50pF, RLOAD unless otherwise noted.
QS53806 Symbol tPLH tPHL tPZL tPZH tPLZ tPHZ Parameter Propagation Delay Output Rise Time, 0.8V Output Fall Time, 0.8V Min. Max. QS53806A Min. Max. Unit
Output Enable Time Output Disable Time
NOTES: Minimums guaranteed production tested. propagation delay other range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew. This parameter guaranteed production tested.
QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Parameter Tested
Switch Position
tPLZ tPZL Others Pulse Generator 50pF
Closed Open
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
INPUT tPLH tPHL 2.0V 1.5V 0.8V tPLH OUPUT tPHL 1.5V tSK(p) tPLH 1.5V INPUT 1.5V
OUPUT
PROPAGATION DELAY
PULSE SKEW tSK(P)
INPUT tPLHA tPHLA 1.5V OUPUT 1.5V tSK(02) OUPUT tSK(02) 1.5V tPLHB tPHLB
INPUT tPLH1 tPHL1
1.5V
OUPUT
1.5V tSK(01) tSK(01) 1.5V tPLH2 tPHL2 tSK(01) PLH2 tPLH1 tPHL2 PHL1
OUPUT
tSK(02) tPLHB tPLHA tPHLB tPHLA
OUTPUT SKEW (SAME BANK) tSK(O1)
OUPUT SKEW (DIFFERENT BANKS) tSK(O2)
ENABLE CONTROL INPUT tPZL OUTPUT NORM ALLY SWITCH CLOSED tPZH OUTPUT NORMALLY SWITCH OPEN 1.5V
DISABLE 1.5V tPLZ 1.5V 0.3V tPHZ 0.3V PART UTPUT tSK(t) tSK(t) PART UTPUT INPUT tPLH1 tPHL1 1.5V 1.5V 1.5V tPLH2 tPHL2
tSK(t) PLH2 tPLH1 tPHL2 tPHL1
ENABLE DISABLE TIMES
PART-TO-PART SKEW tSK(T)
QS53806/A GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Quarter Size Outline Pacakge (SO20-8) Outline (SO20-2)
53806 53806A
Guaranteed Skew 3.3V CMOS Clock Driver/Buffer
CORPORATE HEADQUARTERS 2975 Stender Santa Clara, 95054
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GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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