GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
JEDEC compatible LVTTL level inputs outputs output, skew clock signal buffer Monitor output Clock inputs tolerant Pinout function compatible with QS5805T on-chip resistors noise Input hysteresis better noise margin Guaranteed skew: 0.7ns output skew 0.7ns pulse skew part-to-part skew Std., speed grades speed QSOP package only) Available QSOP SOIC packages
QS532805/A/B
DESCRIPTION
QS532805 clock buffer/driver circuits used clock buffering schemes where skew parameter. This device offers banks non-inverting outputs. QS532805 incorporates series termination resistors. This clock buffer product designed high performance workstations, embedded personal computing systems using 3.6V supply voltages. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QS532805 accept input control signals. QS532805 characterized operation -40°C +85°C.
FUNCTIONAL BLOCK DIAGRAM
NOTE: QS532805 series termination resistor each clock output, including monitor.
1999 Integrated Device Technology, Inc.
JULY 2000
DSC-5785/-
QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
CONFIGURATION
GNDQ 20-2 20-8
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) IOUT TSTG Description Supply Voltage Ground Output Voltage VOUT Input Voltage Input Voltage (pulse width 20ns) Output Current Output Current Max. Sink Current/Pin Storage Temperature Junction Temperature
Unit
Max. Vcc+0.5 +150
QSOP/ SOIC VIEW
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Terminals. terminals except Vcc.
CAPACITANCE
+25OC, 1.0MHz, VOUT
Pins COUT Typ. Max. Unit
NOTE: This parameter guaranteed production tested.
RECOMMENDED OPERATING CONDITIONS
Symbol VOUT Description Power Supply Voltage Input Voltage Voltage Applied Outputs Ambient Operating Temperature Min. Unit
DESCRIPTION
Names OEA, INA, OAn, Description Output Enable Clock Inputs Clock Outputs Monitor Outputs (does 3-state)
QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: -40°C +85°C, 3.3V 0.3V
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., -100µA Min., -8mA Min., 100µA Min., Min., IOFF IODH IODL ROUT Input Leakage Current Output Leakage Current Input Power Leakage Output HIGH Current Output Current Short Circuit Current Output Resistance
(2,3)
Min. -0.5
Typ.(1) -0.7 -100
Max. -1.2 -200
Unit
Max., Max., VOUT 3.3V, VIL, 1.5V 3.3V, VIL, 1.5V Max., VOUT
NOTES: Typical values 3.3V, 25°C. more than output should used test this high power condition. Duration less than second. Guaranteed design tested. Output resistance represents total output impedence logic device includes added series termination resistance.
POWER SUPPLY CHARACTERISTICS
Symbol ICCD Parameter Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output Total Power Supply Current Examples (2,4) Test Conditions Max., Max., 0.6V, 0MHz Max., Outputs Toggling duty cycle Max., duty cycle, 10MHz five outputs toggling Max., duty cycle, 2.5MHz outputs toggling Typ. 0.01 Max. Unit µA/MHz
NOTES: conditions shown Min. Max., appropriate values specified under Electrical Characteristics. Guaranteed design tested. 0pF. Typical values reference only. Conditions 3.3V, 25°C. (ICC)(DH)(NI) ICCD (fO)(NO) where: Input Duty Cycle Number HIGH inputs Output Frequency Number outputs
QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
SKEW CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 3.3V 0.3V CLOAD 50pF resistor)
QS532805 Symbol tSK(01) tSK(02) tSK(P) tSK(T) Parameter Skew between outputs, same transition, same bank Skew between outputs, same transition, different banks Pulse Skew; skew between opposite transitions same output (tPHL tPLH) Part-to-part skew Min. Max. QS532805A Min. Max. QS532805B Min. Max. Unit
NOTES: This parameter guaranteed production tested. Skew parameters apply propagation delays only. tSK(T) only applies devices same transition, part type, temperature, power supply voltage, loading package, speed grade. speed grade only available QSOP package.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
-40°C +85°C, 3.3V 0.3V CLOAD 50pF resistor)
QS532805 Symbol tPLH tPHL tPZL tPZH tPLZ tPZH Parameter (1,2) Propagation Delay Output Rise Time, 0.8V Output Fall Time, 0.8V Min. Max. QS532805A Min. Max. QS532805B Min. Max. Unit
Output Enable Time Output Disable Time
NOTES: Minimums guaranteed production tested. propagation delay other range indicated Min. Max. specifications results from process environmental variables. These propagation delays imply limit skew. This parameter guaranteed production tested. speed grade only available QSOP package.
QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
TEST CIRCUITS WAVEFORMS
Parameter Tested
Switch Position
tPLZ tPZL Others Pulse Generator 50pF
Closed Open
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
INPUT tPLH tPHL 2.0V 1.5V 0.8V tPLH OUPUT tPHL 1.5V tSK(p) tPLH 1.5V INPUT 1.5V
OUPUT
PROPAGATION DELAY
PULSE SKEW tSK(P)
INPUT tPLHA tPHLA OUPUT 1.5V tSK(02) OUPUT tSK(02) 1.5V tPLHB tPHLB 1.5V
INPUT tPLH1 tPHL1
1.5V
OUPUT
1.5V tSK(01) tSK(01) 1.5V tPLH2 tPHL2 tSK(01) PLH2 tPLH1 tPHL2 PHL1
OUPUT
tSK(02) tPLHB tPLHA tPHLB tPHLA
OUTPUT SKEW (SAME BANK) tSK(O1)
OUPUT SKEW (DIFFERENT BANKS) tSK(O2)
ENABLE CONTROL INPUT tPZL OUTPUT NORM ALLY SWITCH CLOSED tPZH OUTPUT NORMALLY SWITCH OPEN 1.5V
DISABLE 1.5V tPLZ 1.5V 0.3V tPHZ 0.3V PART UTPUT tSK(t) tSK(t) PART UTPUT INPUT tPLH1 tPHL1 1.5V 1.5V tPLH2 tPHL2 1.5V
tSK(t) PLH2 tPLH1 tPHL2 tPHL1
ENABLE DISABLE TIMES
PART-TO-PART SKEW tSK(T)
QS532805/A/B GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
XXXX Device Type Package
Quarter Size Small Outline Pacakge (SO20-8) Small Outline (SO20-2)
532805 Guaranteed Skew 3.3V CMOS Clock Driver/Buffer 532805A (532805B) (QSOP package only)
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GUARANTEED SKEW 3.3V CMOS CLOCK DRIVER/BUFFER JEDEC compatible LV

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