MH16D64AKQJ-75,-10 1,073,741,824-BIT (16,777,216-WORD 64-BIT) Dou

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MH16D64AKQJ-75,-10 1,073,741,824-BIT (16,777,216-WORD 64-BIT) Dou

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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Utilizes industry standard Synchronous DRAMs TSOP package industry standard EEPROM(SPD) TSSOP package 200pin SO-DIMM Vdd=Vddq=2.5v ±0.2V
DESCRIPTION
MH16D64AKQJ 16777216 word 64-bit Double Data Rate(DDR) nchronous DRAM mounted module. This consists industry standard nchronous DRAMs TSOP with SSTL_2 interf which achiev high speed data rate 133MHz. This socket-ty memory odule suitable main memory computer systems easy interchange modules.
Double data rate architecture; data transf clock Bidirectional, data strobe (DQS) transmitted/receiv with data erential clock inputs (CLK /CLK)
aligns transitions with transition edges
Operating Frequencies
Clock Rate Speed Grade
CL=2 100MHz 100MHz
CL=2.5 133MHz 125MHz
Commands entered each positiv edge Data data mask erenced both edges 4bank operation concontrolled BA0,BA1(Bank Address ,discrete) /CAS latency 2.0/2.5 (programmable) Burst length- 2/4/8 (programmable) Burst sequential/interleav e(programmable) Auto precharge bank precharge controlled 8192 resh /64ms Auto resh Self resh address A0-12 Column address A0-8 SSTL_2 Interf Module 1bank Conf igration
APPLICATION
Main memory unit Note Mobile etc.
Outline
(Front) (Back)
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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
CONFIGURATION
NAME Vref DQS0 DQS1 DQ10 DQ11 /CK0 DQ16 DQ17 DQS2 DQ18 DQ19 DQ24 DQ25 DQS3 DQ26 DQ27 NAME Vref DQ12 DQ13 DQ14 DQ15 DQ20 DQ21 DQ22 DQ23 DQ28 DQ29 DQ30 DQ31 NAME /CK2 CKE1 A10/AP DQ32 DQ33 DQS4 DQ34 DQ35 DQ40 DQ41 DQS5 DQ42 DQ43 DQ48 DQ49 NAME CKE0 /RAS /CAS DQ36 DQ37 DQ38 DQ39 DQ44 DQ45 DQ46 DQ47 /CK1 DQ52 DQ53 Connect NAME DQS6 DQ50 DQ51 DQ56 DQ57 DQS7 DQ58 DQ59 VddSPD VddID NAME DQ54 DQ55 DQ60 DQ61 DQ62 DQ63
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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
DQS0 DQS1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS
UDQS
DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS
UDQS
LDQS
LDQS
UDQS
SERIAL
UDQS
CKE0 /RAS /CAS BA0,BA1,A<12:0> VddSPD Vref VddID
/CK0 /CK1 /CK2
2loads 2loads
0loads
NOTE: wiring differ from that described this drawing; however DQ/DM/DQS relationships maintained shown. strap connections: (for memory device Vdd, VddQ) Strap (open): Vdd=VddQ Strap (closed): Vdd=VddQ
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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION
SYMBOL TYPE DESCRIPTION
Clock: CK0-2 /CK0-2 erential clock inputs. address control input signals sampled crossing positiv edge CK0-2 negativ edge /CK0-2. Output (read) data erenced crossings CK0-2 /CK0-2 (both directions rossing). Clock Enable: CKE0 controls internal clock. When CKE0 low, internal clock ollowing ceased. CKE0 also used select auto self resh. After self resh mode started, CKE0 becomes nchronous input. Self resh maintained long CKE0 low. Chip Select: When high, command means Operation.
CK0-2,/CK0-2
Input
CKE0
Input
/RAS, /CAS,
Input Input
Combination /RAS, /CAS, defines basic commands.
A0-11 specif Column Address conjunction with BA0,1. Address specif A0-12. Column Address specif A0-8. also used indicate precharge option. When high read write command, auto precharge perf ormed. When high precharge command, banks precharged. Bank Address: BA0-1 specif banks SDRAM which command applied. BA0-1 must with ACT, PRE, READ, WRITE commands.
A0-12
Input
BA0-1 0-63 DQS0-7
Input
Input Output Data Input/Output: Data Input Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered write data. Used capture write data.
Input Data Mask: input mask signal write data. Input data masked when DM0-7 sampled HIGH along with that input data during WRITE access. DM0-7 sampled both edges DQS0-7. Although pins input only, DM0-7 loading matches DQ0-63 DQS0-7 loading.
DM0-7 Vdd, Vddspd Vref SA0-2 VddID
Input
Power Supply Power Supply memory array peripheral circuitry. Power Supply Input Power Supply SSTL_2 reference voltage.
This bidirectional used transf data into EEPROM. This signal used clock data into EEPROM. resistor
Input Output resistor must connected pullup.
Input Output connected pullup. Input Output
Address pins used select Serial Presence Detect. identif ication
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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
MH16D64AKQJ provides basic functions, bank (row) activate, burst read write, bank (row) precharge, auto self refresh. Each command defined control signals /RAS, /CAS rising edge. addition signals, ,CKE used chip select, refresh option, precharge option, respectively. know detailed definition commands, please command truth table.
/CK0 /RAS /CAS CKE0
Chip Select L=select, H=deselect Command Command Command resh Option @ref resh command Precharge Option @precharge read/write command basic commands
Activate (ACT) [/RAS /CAS =/WE command activates idle bank indicated Read (READ) [/RAS /CAS READ command starts burst read from active bank indicated First output data appears after /CAS latency. When this command, bank deactivated after burst read (auto-precharge,READA) Write (WRITE) [/RAS /CAS =/WE WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS /CAS command deactivates active bank indicated This command also terminates burst read /write operation. When this command, banks deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =CKE0 REFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
TRUTH TABLE
COMMAND Deselect Operation Address Entry Bank Activate Single Bank Precharge Precharge Banks Column Address Entry Write Column Address Entry Write with Auto-Precharge Column Address Entry Read Column Address Entry Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register MNEMONIC DESEL PREA WRIT /RAS /CAS BA0,1 A0-9, note 11-12
WRITEA
READ
READA REFA REFS REFSX TERM
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: Applies only read bursts with autoprecharge disabled; this command undefined (and should used) read bursts with autoprecharge enabled, write bursts. BA0-BA1 select either Base Extended Mode Register (BA0 selects Mode Register; selects Extended Mode Register; other combinations BA0-BA1 reserved; A0-A12 provide op-code written selected Mode Register.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State IDLE ACTIVE READ (AutoPrecharge Disabled) /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM ILLEGAL Action Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM READ READA WRITE WRITEA PREA REFA DESEL TERM Bank Active, Latch Auto-Refresh Mode Register Begin Read, Latch Determine Auto-Precharge Begin Write, Latch Determine Auto-Precharge Bank Active ILLEGAL Precharge Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) Terminate Burst Terminate Burst, Latch READ READA Begin Read, Determine Auto-Precharge WRITE WRITEA PREA REFA
Op-Code, Mode-Add
ILLEGAL Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State WRIT (AutoPrecharge Disabled) /RAS /CAS Address Command DESEL TERM Action (Continue Burst END) (Continue Burst END) ILLEGAL Terminate Burst, Latch READ READA Begin Read, Determine AutoPrecharge WRITE WRITEA PREA REFA DESEL TERM Terminate Burst, Latch Begin Write, Determine AutoPrecharge Bank Active ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) ILLEGAL Notes
READ with AUTO PRECHARGE WRITE with AUTO PRECHARGE
Op-Code, Mode-Add Op-Code, Mode-Add Op-Code, Mode-Add
READ READA ILLEGAL WRITE WRITEA PREA REFA DESEL TERM ILLEGAL Bank Active ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL (Continue Burst END) (Continue Burst END) ILLEGAL
READ READA ILLEGAL WRITE WRITEA PREA REFA ILLEGAL Bank Active ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State CHARGING ACTIVATING WRITE RECOVERING /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM Action (Idle after tRP) (Idle after tRP) ILLEGAL Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL (Idle after tRP) ILLEGAL ILLEGAL (Row Active after tRCD) (Row Active after tRCD) ILLEGAL
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
READ WRITE ILLEGAL PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING MODE REGISTER SETTING /RAS /CAS Op-Code, Mode-Add Op-Code, Mode-Add Address Command DESEL TERM Action (Idle after tRC) (Idle after tRC) ILLEGAL Notes
READ WRITE ILLEGAL PREA REFA DESEL TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL (Idle after tRSC) (Idle after tRSC) ILLEGAL
READ WRITE ILLEGAL PREA REFA ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: entries assume that High during preceding clock cycle current clock cycle. ILLEGAL bank specified state; function legal bank indicated depending state that bank. Must satisfy contention, turn around, write recovery requirements. bank precharging idle state. precharge bank indicated ILLEGAL bank idle. ILLEGAL Device operation and/or data-integrity guaranteed.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State SELFREFRESH CKE0 CKE0 /RAS /CAS POWER DOWN BANKS IDLE STATE other than listed above ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: High transition will re-enable other inputs asynchronously minimum setup time must satisfied before command other than EXIT. Power-Down Self-Refresh entered only from Banks Idle State. Must legal command. INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL (Maintain Self-Refresh) INVALID Exit Power Down Idle (Maintain Self-Refresh) Refer Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer Current State =Power Down Refer Function Truth Table Begin Suspend Next Cycle Exit Suspend Next Cycle Maintain Suspend Action Notes
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER APPLIED
POWER
PREA
CHARGE
REFS
SELF REFRESH
REFSX REFA
MODE REGISTER
IDLE
AUTO REFRESH
CKEL CKEH
Active Power Down
CKEH
POWER DOWN
CKEL
ACTIVE
WRITE WRITE WRITEA READA READ READ READ
BURST STOP
WRIT
READ
TERM
WRITEA READA
READA
WRITEA
READA
CHARGE Automatic Sequence Command Sequence
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
POWER SEQUENCE
following power sequences necessary guarantee proper operation SDRAM Apply before same time VDDQ Apply VDDQ before same time Vref Maintain stable condition 200us after stable power CLK, apply DSEL Issue precharge command banks device Issue EMRS Issue Mode Register reset Issue more Auto Refresh commands Maintain stable condition cycle After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register (MRS). mode register stores these data until next command, which issued when banks discrete idle state. After tMRD from command, DIMM ready command. /CK0 /RAS /CAS LTMODE A12-A0 /CAS Latency Burst Length
Latency Mode
Burst Type
Sequential Interleaved
Reset
Reserved Future
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
disable enable mode programmed setting extended mode register (EMRS). extended mode register stores these data until next EMRS command, which issued when banks discrete idle state. After tMRD from EMRS command, DIMM ready command.
/CK0 /RAS /CAS
A12-A0
Disable
enable disable
Drive Strength
Normal Weak(Optional)
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
/CLK Command Address
Read
Write
/CAS Latency
Burst Length
Burst Length
Initial Address
Sequential
Column Addressing Interleaved
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE AXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature 25°C Conditions with respect with respect with respect Ratings -0.5 -0.5 Vdd+0.5 -0.5 Vdd+0.5 Unit
OPERATING CONDITIONS
(Ta=0 70°C
Symbol Vref VIH(DC) VIL(DC) VIN(DC)
unless otherwise noted)
Limits Parameter Supply Voltage Input Reference Voltage High-Level Input Voltage Low-Level Input Voltage Input Voltage Level, /CK0 Min. 0.49*Vdd Vref 0.15 -0.3 -0.3 0.36 Vref 0.04 Typ. 0.5*Vdd Max. 0.51*Vdd Vdd+0.3 Vref 0.15 Vref 0.04 Unit Notes
VID(DC) Input Differential Voltage, /CK0 Termination Voltage
CAPACITANCE
(Ta=0 70°C Symbol CI(A) CI(C) CI(K) CI/O VddQ 0.2V, VssQ unless otherwise noted) Parameter Input Capacitance, address Input Capacitance, control Input Capacitance, Input Capacitance, Test Condition
1.25V =100MHz 25mVrm
Limits(max.)
Unit Notes
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from
(Ta=0 70°C
Symbol
VddQ 0.2V, VssQ Output Open, unless otherwise noted)
Limits(max) Parameter/Test Conditions Unit Notes
IDD0
OPERATING CURRENT: Bank(Discrete); Active-Precharge; MIN; MIN; inputs changing twice clock cycle; address control inputs changing once clock cycle OPERATING CURRENT: Bank(Discrete); Active-Read-Precharge; Burst MIN; 2.5; MIN; IOUT= mA;Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: banks idle; power-down mode; (MAX); IDLE STANDBY CURRENT: (MIN); banks idle; (MIN); MIN; Address other control inputs changing once clock cycle ACTIVE POWER-DOWN STANDBY CURRENT: bank active; power-down mode; (MAX); ACTIVE STANDBY CURRENT: (MIN); (MIN); bank; Active-Precharge; MAX; MIN; DQ,DM inputs changing twice clock cycle; address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst;One bank active(Discrete); Address control inputs changing once clock cycle; 2.5; MIN; IOUT OPERATING CURRENT: Burst Writes; Continuous burst; bank active(Discrete); Address control inputs changing once clock cycle; 2.5; AUTO REFRESH CURRENT: (MIN) SELF REFRESH CURRENT: 0.2V OPERATING CURRENT-Four bank Operation: Four interleaving with BL=4 -Refer Notes
IDD1
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD4W IDD5 IDD6 IDD7
1080
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C Symbol VddQ 0.2V, =VssQ= unless otherwise noted) Parameter/Test Conditions Limits Min. Vref 0.31 Vref 0.31 0.5*Vdd-0.2 -16.8 16.8 0.5*Vdd+0.2 Max. Unit Notes
VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) Input Differential Voltage, /CLK VIX(AC) Input Crossing Point Voltage, /CLK Off-state Output Current floating Vo=0~V Input Current VIN=0 VddQ Output High Current (VOUT=VTT+0.84V) Output Current (VOUT=VTT-0.84V)
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TIMING REQUIREMENTS (Component Level)
(Ta=0 70°C VddQ 0.2V, VssQ unless otherwise noted)
Characteristics Parameter Output Valid data delay time CLK//CLK Min. -0.75 -0.75 0.45 0.45 CL=2.5 tDIPW tDQSQ time CL=2 Input Setup time (DQ,DM) Input Hold time(DQ,DM) input pulse width each input) Data-out-high impedance time CLK//CLK Data-out-low impedance time CLK//CLK Valid data delay time tCLmin tCHmin tHP0.75 0.75 0.35 0.35 0.25 1.25 1.75 -0.75 -0.75 +0.75 +0.75 +0.5 tCLmin tCHmin tHP-1.0 0.75 0.35 0.35 0.25 1.25 -0.8 -0.8 +0.8 +0.8 +0.6 Max. +0.75 +0.75 0.55 0.55 Min. -0.8 -0.8 0.45 0.45 Max. +0.8 +0.8 0.55 0.55 Unit Notes
tDQSCK Output Valid data delay time CLK//CLK High width width
Clock half period
tDQSS tDQSH tDQSL tDSS tDSH tMRD
Output alid window Write command irst latching transition input High width input width alling edge setup time alling edge hold time Mode Register command time
tWPRES Write preamble setup time tWPST tWPRE tRPST tRPRE Write postamble Write preamble Input Setup time (address control) Input Hold time (address control) Read postamble Read preamble
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
TIMING REQUIREMENTS(Continues)
(Ta=0 70°C VddQ 0.2V, VssQ unless otherwise noted) Characteristics Symbol tRAS tRFC tRCD tRRD tDAL tXSNR tXSRD tXPNR tXPRD tREFI Active time Cycle time(operation) Auto Ref. Active/Auto Ref. command period Column Delay Precharge time Delay time Write Recovery time Auto Precharge write recovery precharge time Internal Write Read Command Delay Exit Self Ref. non-Read command Exit Self Ref. -Read command Exit Power down command Exit Power down -Read command Average Periodic Refresh interval Parameter Min. Max. 120,000 Min. Max. 120,000 Unit Notes
Output Load Condition
component measurement)
VREF
50ohm Zo=50 30pF
VREF
Output Timing Measurement Reference Point
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Notes
voltages referenced Vss. Tests timing, IDD, electrical, characteristics, conducted nominal reference/supply voltage levels, related specifications device operation guaranteed full voltage range specified. timing tests swing 1.5V test environment, input timing still referenced VREF crossing point CK//CK), parameter specifications guaranteed specified input levels under normal conditions. minimum slew rate input signals 1V/ns range between VIL(AC) VIH(AC). input level specifications defined SSTL_2 Standard (i.e. receiver will effectively switch result signal crossing input level, will remain that state long signal does ring back above (below) input (HIGH) level. VREF expected equal 0.5*VddQ transmitting device, track variations level same. Peak-to-peak noise VREF exceed +/-2% value. applied directly device. system supply signal termination resistors, expected equal VREF, must track variations level VREF. magnitude difference between input level input level /CLK. value expected equal 0.5*VddQ transmitting device must track variations level same. Enables on-chip refresh address counters. specification tested after device properly initialized. This parameter sampled. VddQ +2.5V+/-0.2V, +2.5V+/-0.2V, =100MHz, VOUT(DC)= VddQ/2, VOUT(PEAK PEAK) 25mV, inputs grouped with pins reflecting fact that they matched laoding faciliate trace matching board level). CLK//CLK input reference level (for timing referenced CLK//CLK) point which /CLK cross; input reference level signals other than CLK//CLK, VREF. Inputs recognized valid until VREF stabilized. Exception: during period before VREF stabilizes, CKE=< 0.3VddQ recognized LOW. transitions occur same access time windows valid data transitions. These parameters referenced specific voltage level, specify when device output longer driving (HZ), begins driving (LZ). maximum limit this parameter device limit. device will operate with greater value this parameter, system performance (bus turnaround) will degrade accordingly. specific requirement that valid (HIGH, LOW, some point valid transition) before this edge. valid transition defined monotonic, meeting input slew rate specifications device. When writes were previously progress bus, will transitioning from High-Z logic LOW. previous write progress, could HIGH, LOW, transitioning from HIGH this time, depending tDQSS. maximum eight AUTO REFRESH commands posted given SDRAM device. tXPRD should tCLK condition unstable operation during power down mode. command/address /CLK slew rate >1.0V/ns.
(Notes continued next page)
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
IDD7 Operating current:Four Bank (1)For Bank being interleaved with tRC(min),Burst Mode,Address Control inputs changing. Iout=0mA (2)Timing patterns: -DDR200(-10)(100MHz,CL=2) Read with Autoprecharge Setup:A0 Read:A0 -repeat same timing with random address changing data changing every transfer -DDR266B(-75)(133MHz,CL=2) Read with Autoprecharge Setup:A0 Read:A0 -repeat same timing with random address changing data changing every transfer
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
(Component Level) Read Operation /CLK Add.
tDQSCK tRPRE VREF
Valid Data tRPST
tDQSQ
Write Operation tDQSS=max. /CLK
tDQSS tWPRES tWPRE tDSS tWPST
tDQSL
tDQSH
Write Operation tDQSS=min. /CLK
tDQSS tWPRES tWPRE tDQSL tDQSH tDSH tWPST
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION (Component Level)
BANK ACTIVATE SDRAM four independent banks. Each bank activated command with bank addresses (BA0,1). indicated address A12-0. minimum activation interval between bank other bank tRRD.
PRECHARGE command deactivates bank indicated BA0,1. When multiple banks active, precharge command (PREA,PRE+A10=H) available deactivate them same time. After from precharge, command same bank issued. Bank Activation Precharge (BL=8, CL=2)
/CLK
command tRCmin tRCmin tRAS tRCD BL/2
Command
tRRD
READ
A0-9,11-12
BA0,1
Precharge
precharge command issued BL/2 from read command without data loss.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
READ After tRCD from bank activation, READ command issued. Output data available after /CAS Latency from READ, followed (BL-1) consecutive data (BL:Burst Length) start address specified A8-A0, address sequence burst data defined Burst Type. READ command issued active bank, precharge time (tRP) hidden during continuous burst data interleaving multiple banks. When high READ command, auto-precharge(READA) performed. command(READ,WRITE,PRE,ACT) asserted same bank inhibited till internal precharge completed. internal precharge starts BL/2 time after READA command next command issued after (BL/2+tRP) time from previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK Command A0-9,11-12 BA0,1
tRCD
READ
READ
Burst Length /CAS latency
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2,2.5)
/CLK Command A0-9,11-12 BA0,1 CL=2 CL=2.5
BL/2 tRCD READA BL/2
Internal precharge start erent Bank Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal
Asserted Command READ READA WRITE(CL=2) WRITE(CL=2.5 WRITEA(CL=2)
Legal Legal Legal Legal Legal Legal
Illegal Illegal Illegal Illegal Illegal Legal
Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal
WRITEA(CL=2.5) Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal
Operating description when command asserted.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
WRITE After tRCD from bank activation, WRITE command issued. input data sampled WRITE command with data strobe input, followed (BL-1) data written into Burst Length start address specified A8-A0, address sequence burst data defined Burst Type. WRITE command applied active bank, precharge time (tRP) hidden during continuous input data interleaving multiple banks. write recovery time (tWR) required from last written data next command. When high WRITE command, auto-precharge(WRITEA) performed. command (READ,WRITE,PRE,ACT) asserted same bank inhibited till internal precharge operation completed. next command issued after tDAL from last input data cycle. Multi Bank Interleaving WRITE (BL=8)
/CLK Command A0-9,11-12 BA0,1
WRITE tRCD tRCD
WRITE
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MH16D64AKQJ-75,-10
1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
WRITE with Auto -Precharge (BL=8)
/CLK Command 9,11-12 BA0,1
WRITE tDAL
Asserted Command READ READA WRITE WRITEA
Different Bank Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal
Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Legal Legal Legal
Illegal Illegal Illegal Illegal Illegal Illegal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal Legal
Operating description when command asserted.
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION [Read Interrupted Read] Burst read operation interrupted read bank. Random column access allowed. READ READ interval minimum 1CLK. Read Interrupted Read (BL=8, CL=2)
/CLK Command A0-9,11-12 BA0,1
READ READ READ READ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted precharge] Burst read operation interrupted precharge same bank. READ interval minimum CLK. time between command output disable equal Latency. result, READ interval determines valid data length output. figure below shows examples BL=8.
/CLK Command Command
READ
Read Interrupted Precharge (BL=8)
READ
CL=2.5
Command
READ
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Read Interrupted Precharge (BL=8)
/CLK Command Command
READ
READ
CL=2.0
Command
READ
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[Read Interrupted Burst Stop] Burst read operation interrupted burst stop command(TERM READ TERM interval minimum CLK. TERM command output disable latency equivalent /CAS Latency. result, READ TERM interval determines valid data length output. figure below shows examples BL=8.
Read Interrupted TERM (BL=8)
/CLK Command Command
READ
TERM
READ
TERM
CL=2.5
Command Command Command
READ
READ TERM
READ
TERM
TERM
CL=2.0
Command
READ TERM
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted Write with TERM]
Read Interrupted TERM (BL=8)
/CLK Command
READ
TERM
WRITE
CL=2.5
Command
READ
TERM
WRITE
CL=2.0
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[Write interrupted Write] Burst write operation interrupted write bank. Random column access allowed. WRITE WRITE interval minimum CLK. Write Interrupted Write (BL=8)
/CLK Command A0-9,11-12 BA0,1
WRITE WRITE WRITE WRITE
Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
[Write interrupted Read] Burst write operation interrupted read same other bank. Random column access allowed. Internal WRITE READ command interval(tWTR) minimum CLK. input data interrupting READ cycle "don't care". tWTR referenced from first positive edge after last data input.
/CLK Command A0-9,11-12 BA0,1
Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
Write Interrupted Read (BL=8, CL=2.5)
WRITE
READ
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted Precharge] Burst write operation interrupted precharge same bank. Random column access allowed. referenced from first positive edge after last data input.
Write Interrupted Precharge (BL=8, CL=2.5)
/CLK Command A0-9,11-12 BA0,1
Dai0 Dai1
WRITE
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
[Initialize Mode Register sets]
/CLK
Command A0-9,11-12 BA0,1
EMRS
Code
Code
Code
Code
Code
tMRD
Extended Mode Register
tMRD
tRFC
tRFC
tMRD
Mode Register Set, Reset
[AUTO REFRESH] Auto-refresh cycle initiated with REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. refresh address generated internally. 8192 REFA cycles within 64ms refresh 256M bits memory cells. auto-refresh performed banks concurrently. Before performing auto refresh, banks must idle state. Auto-refresh auto-refresh interval minimum tRFC command must supplied device before tRFC from REFA command. Auto-Refresh
/CLK /RAS /CAS A0-11-12 BA0,1
tRFC DESELECT
Auto Refresh Banks
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
REFRESH] Self -refresh mode entered issuing REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once self-refresh initiated, maintained long kept low. During self-refresh mode, asynchronous only enable input, other inputs including disabled ignored, that power consumption synchronous inputs saved. exit self-refresh, supplying stable inputs, asserting DESEL command then asserting longer than tXSNR/tXSRD.
Self-Refresh
/CLK /RAS /CAS A0-11-12 BA0,1
tXSNR Self Refresh Exit tXSRD
Read
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[Power DOWN] purpose suspend power down. synchronous input except during self-refresh mode. command cycle ignored. From CKE=H normal function, recovery time required condition stable operation during power down mode. Power Down
/CLK Command
Standby Power Down
Valid
Command
Active Power Down
Valid
tXPNR/ tXPRD
CONTROL] defined data mask writes. During writes,DM masks input data word word. write mask latency Function(BL=8,CL=2)
/CLK Command
Write READ
Don't Care
masked DM=H
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table
Byte Function described Number Serial Bytes Written during Production Total bytes memory device Fundamental memory type Addresses this assembly Column Addresses this assembly Module Banks this assembly Data Width this assembly. Data Width continuation Voltage interface standard this assembly
SDRAM Cycletime Max. Supported Latency (CL).
enrty data Bytes SDRAM 1BANK SSTL2.5V 7.5ns 8.0ns +0.75ns +0.8
None-parity,Non-ECC
DATA(hex)
Cycle time CL=2.5 SDRAM Access from Clock CL=2.5 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
7.8uS/SR clock 4bank 2.0,
Differential Clock 0.2V
Burst Lengths Supported Number Device Banks CAS# Latency Latency Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest latency) Cycle time CL=2
SDRAM Access form Clock(2nd highest latency)
10ns 10ns +0.75ns +0.8ns Undefined Undefined Undefined Undefined 20ns 15ns 20ns
CL=2
SDRAM Cycle time(3rd highest latency)
SDRAM Access form Clock(3rd highest latency)
Minimum Precharge Time (tRP) Minimum Active Active Delay (tRRD) Delay Minv (tRCD)
45ns 50ns
Active Precharge (tRAS)
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table
Density each bank module
128MByte
0.9nS 1.1nS 0.9nS 1.1nS 0.5nS 0.6nS 0.5nS 0.6nS
Command Address signal input setup time Command Address signal input hold time
36-61
Data signal input setup time Data signal input hold time Superset Information (may used future) Revision
option Check
Checksum bytes 0-62 Check
64-71
Manufactures Jedec code JEP-108E
MITSUBISHI
1C00000000000000
Manufacturing location
Manufacturing Location
73-90
Manufactures Part Number
MH16D64AKQJ-75 MH16D64AKQJ-10
91-92 93-94 95-98 99-127 128-255
Revision Code Manufacturing date Assembly Serial Number Reserved Open Customer
revision year/week code serial number Undefined Undefined
rrrr yyww ssssssss
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. D.C. Characteristics
Symbol Parameter Supply Voltage Supply Voltage Input High Voltage Input Voltage Output Voltage Min. Vccx0.7 Limits Typ. Max. Vcc+0.5 Vccx0.3 Units
EEPROM A.C.Timing Parameters (Ta=0 70°C
Symbol fSCL TBUF THD:STA TLOW THIGH TSU:STA THD:DAT TSU:DAT TSU:STO Parameter Clock Frequency Noise Supression Time Constant SCL, inputs Data Valid
Time Must Free before Transmission Start
Limits Min. Max.
Units
Start Condition Hold Time Clock Time Clock High Time Start Condition Setup Time Data Hold Time Data Setup Time Rise Time Fall Time Stop Condition Setup Time Data Hold Time Write Cycle Time
time from valid stop condition write sequence EEPROM internal erase/program cycle.
HIGH
SU:STO SU:STA HD:STA HD:DAT SU:DAT
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
OUTLINE
31.75 20.00 4.00 6.00
4.00
0.25Max 2.55 MIT-DS-0457-0.0 Unit.mm 16.Apr.2002
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1,073,741,824-BIT (16,777,216-WORD 64-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first your circuit designs!
Mitsubishi Electric Corporation puts maximum effort into making semiconductor products better more reliable, there always possibility that trouble occur with them. Trouble with semiconductors lead personal injury, fire property damage. Remember give consideration safety when making your circuit designs, with appropriate measures such placement substitutive, auxiliary circuits, (ii) nonflammable material (iii) prevention against malfunction mishap.
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MH16D64AKQJ-75,-10 1,073,741,824-BIT (16,777,216-WORD 64-BIT) Dou

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