3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion
IDT74LVCH16276A
DESCRIPTION
LVCH16276A synchronous exchanger built using advanced dual metal CMOS technology.The LVCH16276A high-speed, bidirectional, 12-bit, registered, multiplexer synchronous memory interleaving applications. registers have common clock clock enable (CExxx) each data register control data sequencing. output enables select (OEA, SEL) also under synchronous control allowing direction changes edge triggered events. tri-port exchanger three 12-bit ports. Data transferred between port either/both ports. clock enable (CE1B, CE2B, CEA1B CEA2B) inputs control data storage. Both ports have common output enable (OEB) synchronously loading registers from port. pins LVCH16276A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH16276A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16276A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features LVCH16276A: High Output Drivers: ±24mA Reduced system switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
Functional Block Diagram
CEA1B
A-1B REGISTER 1B-A REGISTER
1:12
CE1B
1:12
CONTROL REGISTER
CE2B
2B-A REGISTER A-2B REGISTER
CEA2B
1:12
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4230/1
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
CONFIGURATION
EA1B EA2B 56-1 56-2 56-3
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM(2) VTERM(3) TSTG IOUT Description Terminal Voltage with Respect Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each
Unit
Link
Max. +6.5 +6.5 +150 ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
CAPACITANCE +25OC, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
Link
NOTE: applicable device type.
SSOP/ TSSOP/ TVSOP VIEW
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
DESCRIPTION
A(1:12) 1B(1:12) 2B(1:12) CEA1B CEA2B CE1B CE2B Bidirectional Data Port Usually connected CPU's Address/Data bus.(1) Bidirectional Data Port Usually connected even path even bank memory.(1) Bidirectional Data Port Usually connected path bank memory.(1) Clock Input. Clock Enable Input A-1B Register. CEA1B during rising edge CLK, data will clocked into register A-1B (Active LOW). Clock Enable Input A-2B Register. CEA2B during rising edge CLK, data will clocked into register A-2B (Active LOW). Clock Enable Input 1B-A Register. CE1B during rising edge CLK, data will clocked into register 1B-A (Active LOW). Clock Enable Input 2B-A Register. CE2B during rising edge CLK, data will clocked into register 2B-A (Active LOW). Part Selection. When HIGH during rising edge CLK, enables data transfer from Port Port. When during rising edge CLK, enables data transfer from Port Port. Synchronous Output Enable Port (Active LOW). Synchronous Output Enable Port Port (Active LOW).
NOTE: These pins have "Bus-hold". other pins have inputs, outputs, I/Os.
FUNCTION TABLES
Inputs CE1B
Outputs
CE2B
A0(2) A0(2)
Inputs CEA1B CEA2B
Outputs B0(2) B0(2) B0(2) Active B0(2) B0(2) B0(2) Active
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established.
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. 24mA 0.1mA 12mA 2.7V 3.0V 12mA 24mA Max. 0.55
Link
Unit
2.3V 2.3V 2.7V 3.0V 3.0V Output Voltage 2.3V 3.6V 2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance exchanger Outputs enabled Power Dissipation Capacitance exchanger Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
SWITCHING CHARACTERISTICS
Symbol tPLH tPHL tPLH tPHL Parameter Propagation Delay Propagation Delay
2.7V Min. Max. 3.3V±0.3V Min. Max. Unit
Stable CExB Enabled Changing CExB Disabled Changing CExB Enabled
tPZH tPZL tPHZ tPLZ tSK(o)
Output Enable Time 1Bx, Output Disable Time 1Bx, Set-Up Time, HIGH Data Set-Up Time, CLK, Set-Up Time, Set-Up Time, CEA1B CLK, CE1B CE2B CLK, CEA2B Hold Time, Data Hold Time, OEA, OEB, Hold Time, CEA1B, CE1B, CE2B, CEA2B Pulse Width, HIGH Output Skew(2)
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH16276A 3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER BUS-HOLD
ORDERING INFORMATION
Bus-Hold Family XXXX Device Type Package Temp. ange
276A
Shrink Small Outline Package (SO56-1) Thin Shrink Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 12-Bit Synchronous Exchanger Double-Density with Resistors, ±24m
Bus-hold -40°C +85°C
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3.3V CMOS 12-BIT SYNCHRONOUS EXCHANGER WITH BUS-HOLD VOLT TOLERANT

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