IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, VOLT
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IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS, VOLT TOLERANT BUS-HOLD
Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.635mm pitch SSOP, 0.50mm pitch TSSOP 0.40mm pitch TVSOP packages Extended commercial range -40°C +85°C 3.3V ±0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs Volt tolerant Supports insertion
DESCRIPTION:
This 20-bit flip-flop built using advanced dual metal CMOS technology. flip-flops LVCH162721A edge-triggered D-type flip-flops with qualified clock storage. positive transition clock (CLK) input, device provides true data outputs clock-enable (CLKEN) input low. CLKEN high, data stored. buffered output-enable (OE) input places outputs either normal logic state (high low) high-impedance state. highimpedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without need interface pullup components. does affect internal operation flip-flops. data retained data entered while outputs high-impedance state. LVCH162721A series resistors device output structure which will significantly reduce line noise when used with light loads. This driver been designed drive ±12mA designated threshold levels. LVCH162721A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
Drive Features LVCH162721A: Balanced Output Drivers: ±12mA switching noise
APPLICATIONS:
3.3V mixed voltage systems Data communication telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
CLKEN
Other Channels
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4940/-
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
1998 Integrated Device Technology, Inc.
DSC-123456
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40OC +85OC
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, 18mA 3.3V 3.6V 5.5V(2) Quiescent Power Supply Current Variation input 0.6V other inputs
Link
Test Conditions 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 3.6V 5.5V 5.5V
Min.
Typ.(1)
Max.
Unit
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
Link
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 2.3V 3.6V
Test Conditions 2.0V 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max.
Unit
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage Test Conditions(1) 2.3V 3.6V 0.1mA 2.7V 3.0V Output Voltage 2.3V 3.6V 2.3V 2.7V 3.0V 12mA 0.1mA 12mA Min. Max. 0.55 0.55
Link
Unit
2.3V
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C +85°C.
OPERATING CHARACTERISTICS, 25°C
2.5V±0.2V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled 2.5V±0.2V Symbol tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Parameter Propagation Delay Output Enable Time Output Disable Time Set-up Time, data before Set-up Time, CLKEN before Hold Time, data after Hold Time, CLKEN after Pulse Duration, HIGH Output Skew(2) Min. Max. 2.7V Min. Max. 3.3V±0.3V Min. Max. Unit Test Conditions 0pF, 10Mhz Typical 3.3V±0.3V Typical Unit
SWITCHING CHARACTERISTICS
NOTES: test circuits waveforms. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V ±0.3V VCC(1) 2.7V VCC(2)= 2.5V ±0.2V Unit
Link
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION
Link
TEST CIRCUITS OUTPUTS
Pulse Generator D.U.T. LOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT OUTPUT ITCH NORMALLY tPZH OUTPUT ITCH NORMALLY OPEN HIGH LOAD/2 tPHZ DISABLE LOAD/2
Link
Link DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
Link
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other tests Switch VLOAD
Open
Link
OUTPUT SKEW
INPUT tPLH1 PHL1
PULSE WIDTH
-HIGH-LOW PULSE HIGH-LOW -HIGH PULSE
Link
OUTPUT
OUTPUT PLH2 tPHL2
tPLH2 tPLH1 tPHL2
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
Link
IDT74LVCH162721A 3.3V CMOS 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
ORDERING INFORMATION
Bus-H Family Device Type Package Temp. ange
721A
Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) 20-Bit Flip-Flop 3-State Outputs Double-Density with esistors, ±12mA Bus-hold -40°C +85°C
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