High SPEED CMOS SRAM Single +3.3 volt power supply Access times:
|
|
|
Top Searches for this datasheet
LP61L256B Series
High SPEED CMOS SRAM
Single +3.3 volt power supply Access times: (max.) Current: Operating: 100mA (max.) Standby: 10mA (max.) Full static operation, clock refreshing required inputs outputs directly compatible Common using three-state output Data retention voltage: (min.) Available 28-pin TSOP packages
General Description
LP61L256B high-speed, low-power 262,144-bit static random access memory organized 32,768 words bits that operates single 3.3V power supply. Input three-state outputs compatible allow direct interfacing with common system structures. Minimum standby power drawn this device when high level, independent other input levels. Data retention guaranteed power supply voltage
Configurations
TSOP
I/O1 I/O2 I/O3
LP61L256BV
I/O8 I/O7 I/O6 I/O5 I/O4
LP61L256B
Name Name
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Block Diagram
DECODER 1024 MEMORY ARRAY
I/O1 COLUMN INPUT DATA CIRCUIT COLUMN DECODER I/O8
CONTROL CIRCUIT
Descriptions -SOJ
Symbol I/O1 I/O8 Description Address Inputs Data Inputs/Outputs Ground Chip Enable Output Enable Write Enable
Description TSOP
Symbol I/O1 I/O8 Description Output Enable Address Inputs Write Enable Power Supply Data Inputs/Outputs Ground Chip Enable
Power Supply (+3.3V)
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Recommended Operating Conditions
70°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Output Load Min. -0.3 Typ. Max. Unit
Absolute Maximum Ratings*
-0.5V +4.6V IN/OUT Volt -0.3V +0.3V Operating Temperature, Topr +70°C Storage Temperature, Tstg -55°C +125°C Power Dissipation, 1.0W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics 70°C, 3.3V 10%,
LP61L256B-12 Symbol ICC1 Standby Power Supply Current Parameter Min. Input Leakage Current Output Leakage Current Dynamic Operating Current Max. VI/O VIL, II/O 0.2V 0.2V 0.2V Unit Conditions
ISB1
Output Voltage Output High Voltage
Notes: ICC1 dependent output loading, cycle rates, Read/Write patterns.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Truth Table
Mode Standby Output Disable Read Write Operation High High DOUT Supply Current ISB, ISB1 ICC1 ICC1 ICC1
Capacitance 25°C, MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
Characteristics 70°C, 3.3V 10%)
LP61L256B-12 Symbol Parameter Min. Read Cycle tACE tCLZ tOLZ tCHZ tOHZ Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Output Valid Chip Enable Output Output Enable Output Chip Disable Output High Output Disable Output High Output Hold from Address Change Max. Unit
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Characteristics (continued)
LP61L256B-12 Symbol Parameter Min. Write Cycle tWHZ Write Cycle Time Chip Enable Write Address Setup Time Write Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Max. Unit
Notes: tCHZ, tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levels.
Timing Waveforms
Read Cycle
Address
DOUT
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Timing Waveforms (continued)
Read Cycle
tACE tCLZ
tCHZ
DOUT
Read Cycle
Address
tOLZ tACE tCLZ DOUT
tOHZ tCHZ
Note:
high Read cycle. Device continuously enabled, VIL. Address valid prior coincident with transition low. VIL. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tCW5 tAS1 tWP2
tWR3
tWHZ tOW7 DOUT
Write Cycle (Chip Enable Controlled)
Address tAS1 tCW5 tWR3
tWP2
tWHZ DOUT
Notes:
measured from address valid beginning Write. Write occurs during overlap (tWP) measured from going high Write cycle. transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from going Write. continuously VIL). Transition measured ±200mV from steady state. This parameter sampled 100% tested.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Test Conditions
Input Pulse Levels Input Rise Fall Times Input Current Timing Reference Levels Output Load 1.5V Figures
+3.3V 30pF*
+3.3V OUTPUT ZO=50 5pF* VT=1.5V RL=50
Including scope jig.
Including scope jig.
Figure Output Load
Figure Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ,
Figure Output Load
Data Retention Characteristics 70°C)
Symbol Parameter Data Retention Min. Max. Unit Conditions 0.2V 0.2V 0.2V 0.2V Retention Waveform
ICCDR
Data Retention Current
tCDR
Chip Disable Data Retention Time Operation Recovery Time
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Data Retention Waveform
DATA RETENTION MODE 3.3V tCDR 3.3V
0.2V
Ordering Information
Part LP61L256BS-12 LP61L256BV-12 Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package TSOP
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Package Information Outline Dimensions
unit: inches/mm
Seating Plane
Symbol
Dimensions inches 0.140 Max. 0.027 Min. 0.100±0.005 0.028 Typ. 0.018 Typ. 0.010 Typ. 0.710 Typ. (0.730 Max.) 0.300±0.005 0.050 Typ. 0.265±0.010 0.337±0.008 0.087±0.10 0.045 Max. 0.004 Max.
Dimensions 3.56 Max. 0.69 Min. 2.54±0.13 0.71 Typ. 0.46 Typ. 0.25 Typ. 18.03 Typ. (18.54 Max.) 7.62±0.13 1.27 Typ. 6.73±0.25 8.56±0.20 2.21±0.25 1.14 Max. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
LP61L256B Series
Package Information TSOP TYPE 13.4mm) Outline Dimensions
unit: inches/mm
12.0°
GAUGE PLANE
0.25
Detail
Detail
Symbol
Dimensions inches 0.049 Max. 0.002 Min. 0.039±0.002 0.0079±0.0012 0.006±0.0003 0.465±0.004 0.315±0.004 0.0217 TYP. 0.528±0.008 0.02±0.008 0.0266 TYP. 0.0167 TYP. 0.004 Max.
Dimensions 1.25 Max. 0.05 Min. 1.00±0.05 0.20±0.03 0.15±0.008 11.80±0.10 8.00±0.10 0.55 TYP. 13.40±0.20 0.50±0.20 0.675 TYP. 0.425 TYP. 0.10 Max.
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
(August, 2001, Version 1.0)
AMIC Technology, Inc.
Other recent searches
Ur100Vdc - Ur100Vdc Ur100Vdc Datasheet
TP0610L - TP0610L TP0610L Datasheet
VP0610L - VP0610L VP0610L Datasheet
BS250 - BS250 BS250 Datasheet
SiE854DF - SiE854DF SiE854DF Datasheet
L1010-QT - L1010-QT L1010-QT Datasheet
KDR367 - KDR367 KDR367 Datasheet
DPS-180KB-4 - DPS-180KB-4 DPS-180KB-4 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
