Document Title HIGH SPEED CMOS SRAM Revision History HIGH SPEED C

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Document Title HIGH SPEED CMOS SRAM Revision History HIGH SPEED C

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LP61L256C
Document Title HIGH SPEED CMOS SRAM Revision History
HIGH SPEED CMOS SRAM
History
Initial issue
Issue Date
November 2001
Remark
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C
Features
Single +3.3V power supply Access times: 12/15 (max.) Current: Operating: 120mA (max.) Standby: (max.) Full static operation, clock refreshing required inputs outputs directly compatible Common using three-state output Data retention voltage: (min.) Available 28-pin package
HIGH SPEED CMOS SRAM
General Description
LP61L256C high-speed, low-power 262,144-bit static random access memory organized 32,768 words bits operates single 3.3V power supply. built using high performance CMOS process. Inputs three-state outputs compatible allow direct interfacing with common system structures. Minimum standby power drawn this device when high level, independent other input levels. Data retention guaranteed power supply voltage
Configurations
I/O7 I/O6 I/O5 I/O4 I/O3
I/O0 I/O1 I/O2
LP61L256C
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Block Diagram
DECODER 1024 MEMORY ARRAY
I/O0 COLUMN INPUT DATA CIRCUIT COLUMN DECODER I/O7
CONTROL CIRCUIT
Descriptions
Symbol I/O0 I/O7 Description Address Inputs Data Inputs/Outputs Ground Power Supply Chip Enable Output Enable Write Enable
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Recommended Operating Conditions
70°C) Symbol Parameter Supply Voltage Ground Input High Voltage Input Voltage Output Load Min. -0.5 Typ. Max. +0.8 Unit
Absolute Maximum Ratings*
-0.5V +4.6V IN/OUT Volt -0.5V +0.5V Operating Temperature, Topr +70°C Storage Temperature, Tstg -55°C +125°C Temperature Under Bias, Tbias -10°C +85°C Power Dissipation, 1.0W
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections this specification implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Electrical Characteristics
Symbol Parameter
70°C, 3.3V 10%, LP61L256C-12/15 Min. Max. VI/O VIL, II/O Min. Cycle, Duty 100% 0.2V -0.2V 0.2V Unit Conditions
Input Leakage Output Leakage
ICC1
Dynamic Operating Current
ISB1
Standby Power Supply Current
Output Voltage Output High Voltage
Notes: -3.0V pulses less than ICC1 dependent output loading, cycle rates, Read/Write patterns.
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Truth Table
Mode Standby Output Disable Read Write Note: Operation High High DOUT Supply Current ISB, ISB1 ICC1 ICC1 ICC1
Capacitance 25°C, 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. Unit Conditions VI/O
These parameters sampled 100% tested.
Characteristics +70°C, 3.3V 10%)
Symbol Parameter LP61L256C-12 Min. Read Cycle tACE tCLZ tOLZ tCHZ tOHZ Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Output Valid Chip Enable Output Output Enable Output Chip Disable Output High Output Disable Output High Output Hold from Address Change Max. LP61L256C-15 Min. Max. Unit
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Characteristics (continued)
Symbol Parameter LP61L256C-12 Min. Write Cycle tWHZ Write Cycle Time Chip Enable Write Address Setup Time Write Address Valid Write Write Pulse Width Write Recovery Time Write Output High Data Write Time Overlap Data Hold from Write Time Output Active from Write Max. LP61L256C-15 Min. Unit
Notes: tCHZ, tOHZ tWHZ defined time which outputs achieve open circuit condition referred output voltage levles.
Timing Waveforms
Read Cycle
Address
tOLZ5 tACE tCLZ5 DOUT
tOHZ5 tCHZ5
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Timing Waveforms (continued)
Read Cycle
Address
DOUT
Read Cycle
tACE tCLZ
tCHZ
DOUT
Notes:
high Read Cycle. Device continuously enabled, VIL. Address valid prior coincident with transition low. VIL. Transition measured ±200mV from steady state. This parameter sampled 100% tested.
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Timing Waveforms (continued)
Write Cycle (Write Enable Controlled)
Address tCW5 tAS1
tWHZ7 DOUT
Write Cycle (Chip Enable Controlled)
Address tAS1 tCW5
tWHZ7 DOUT
Notes:
measured from address valid beginning Write. Write occurs during overlap (tWP) measured from earliest going high Write cycle transition occurs simultaneously with transition after transition, outputs remain high impedance state. measured from later going Write. continuously low. VIL) Transition measured ±200mV from steady state. This parameter sampled 100% tested.
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Test Conditions
Input Pulse Levels Input Rise Fall Time Input Output Timing Reference Levels Output Load 3.0V 1.5V Figures
+3.3V OUTPUT ZO=50 RL=50 VT=1.5V Including scope jig. 5pF*
Figure Output Load
Figure Output Load tCLZ, tOLZ, tCHZ, tOHZ, tWHZ,
Data Retention Characteristics 70°C)
Symbol Parameter Data Retention Min. Max. Unit Conditions 0.2V 2.0V 0.2V 0.2V 0.2V
ICCDR
Data Retention Current
tCDR
Chip Disable Data Retention Time Operation Recovery Time
tRC*
Retention Waveform
Read Cycle Time
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Data Retention Waveform
DATA RETENTION MODE 3.0V tCDR 2.0V 3.0V
0.2V
Ordering Information
Part LP61L256CS-12 LP61L256CS-15 Access Time (ns) Operating Current Max. (mA) Standby Current Max. (mA) Package
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.
LP61L256C Series
Package Information Outline Dimensions
unit: inches/mm
Seating Plane
Symbol
Dimensions inches 0.027 0.095 0.100 0.028 0.018 0.010 0.295 0.255 0.329 0.077 0.710 0.300 0.050 0.265 0.337 0.087 0.275 0.345 0.097 0.045 0.004 0.730 0.305 0.140 0.105
Dimensions 0.69 2.41 2.54 0.71 0.46 0.25 7.49 6.48 8.36 1.96 18.03 7.62 1.27 6.73 8.56 2.21 6.99 8.76 2.46 1.14 0.10 18.54 7.75 3.56 2.67
Notes: maximum value dimension includes flash. Dimension does include resin fins. Dimension Board surface mount pitch design reference only. Dimension includes flash.
PRELIMINARY
(November, 2001, Version 0.0)
AMIC Technology, Inc.

Document Title HIGH SPEED CMOS SRAM Revision History HIGH SPEED C

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