Document Title 3-Level Outputs Gate Driver Revision History 3-Lev
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AD120 Preliminary
Document Title 3-Level Outputs Gate Driver Revision History
3-Level Outputs Gate Driver
History
Initial issue
Issue Date
August 2001
Remark
Preliminary
Important Notice: AMIC reserves right make changes products discontinue integrated circuit product service without notice. AMIC integrated circuit products designed, intended, authorized, warranted suitable life-support applications, devices systems other critical applications. AMIC products such applications understood fully risk customer.
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology, Inc.
AD120 Preliminary
Features
gate driver 3-level outputs max. each output -15V min. each output 2.7V~3.6V logic input/output level Bi-directional data shift control Output waveform control available
3-Level Outputs Gate Driver
AD120 gate driver panel. There outputs chip. Three-level output allows voltage correction better switching noise rejection. used SXGA panels.
Block Diagram
ST1X
Shift Register
ST2X
XOFF
Decoder
VOFF
Output
OUT0 OUT1 OUT2
OUT255 OUT256 OUT257
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Pinout
OUT0 OUT1 OUT2 OUT3 OUT4
VOFF XOFF ST2X ST1X VOFF
AD120
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
OUT253 OUT254 OUT255 OUT256 OUT257
AD120
Input/Output Function
Symbol Description Clock pulse Right left direction control shift register When LOW, data shifted right, output257.
output0
output1
When HIGH, data shifted left, ST1X ST2X output256 output0.
output257
XOFF
ST1, ST2, ST1X, ST2X
force outputs voltage. synchronous XOFF force outputs VOFF voltage.
synchronous Output Gate pulse Width select output_waveform format. When LOW, defined inputs while ST1X ST2X defined outputs synchronized signals placed ST1X ST2X after pulses. When HIGH, ST1X ST2X defined inputs, while ST1/ST2 defined outputs. synchronized ST1X ST2X signals placed after pulses. Output drivers These outputs synchronized pulses. output format voltage level controlled OGW, XOFF ST2, ST1X ST2X correspondingly shown diagram. Reference voltage Supply voltage logic operation voltage levels input output logic signals High voltage output drivers voltage output drivers voltage output drivers
4,5, 13,14
OUT0~ OUT257
VOFF
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Description
Operation Output signals OUT0~OUT257 used control gates panel. bi-directional shift register implemented sequentially output signals OUT0~OUT257. clock pulse applied bi-directional shift register direction register controlled signal. When either starting signal goes HIGH, shift register starts shifting from OUT0 OUT257. voltages corresponding outputs switch VOFF depending starting signals shown diagram. outputs starting signals ST1X ST2X switch accordingly after pulses following start shift register which allows expansion outputs cascading more devices. When HIGH either starting signal ST1X ST2X goes HIGH, shift register starts shifting from OUT257 OUT0. voltages corresponding outputs switch VOFF depending starting signals shown diagram. outputs starting signals ST1/ST2 switch accordingly after pulses following start shift register which allows expansion outputs cascading more devices. 3-Level Output 40V(max.) VOFF 0~10V 17~28V
Level
VOFF
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Operation Diagram
OUT0 VOFF OUT1 VOFF VOFF OUT3 VOFF OUT256 VOFF OUT257 VOFF ST1X
ST2X
OUT2
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Operation Diagram
XOFF OUT0 VOFF OUT1 VOFF OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Table Function XOFF
XOFF
OUT0~OUT257 VOFF Table2
outputs asynchronous
Table Control OUT1~OUT256 XOFF
ST1X ST2X outputs synchronous "L") "H") VOFF OUT1~OUT256
Table Control OUT0 OUT257 XOFF
ST1X outputs synchronous ST2X OUT0 OUT257 VOFF
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Absolute Maximum Ratings Over Operating Free-air Temperature Range
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Input Voltage Storage Temperature Symbol VOFF Tstg Ratings -0.3 +7.0 -0.3 42.0 -20.0 +0.3 VL-0.3 VL+11.0 -0.3 42.0 -0.3 VDD+0.3 Unit
Power_on Sequence Voltage Levels
Out0~Out257 VOFF
Logic Signal
Operating Voltage Range
Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Voltage Clock Frequency Operating Free-air Temperature Symbol VOFF Min. Typ. Max. 10.0 Unit
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Charactertics
(VDD 2.7~3.6V, -20~75°C) Parameter Level Input Voltage High Level Input Voltage Level Output Voltage High Level Output Voltage Output Resistance Output Resistance Output Resistance Input Current Operating Current Operating Current Notes: 25V, VOFF -10V 50KHz Symbol ROFF 40µA 40µA VOUT VOUT VOFF VOUT -5.0 Condition Min. -0.4 Max. 1000 1000 1000 +5.0 1500 Unit Applicable input pins input pins ST1, ST2, ST1X, ST2X OUT0~OUT257 OUT0~OUT257 OUT0~OUT257 input pins Note
Charactertics
(VDD 2.7~3.6V, -20~75°C) Parameter Clock Frequency High Pulse Width Pulse Width Input Rise Time Input Fall Time Gate Time Data Setup Time Data Hold Time Delay Time Delay Time Delay Time Delay Time Delay Time Symbol tCPH tCPL tWOFF tpd1 tpd2 tpd3 tpd4 tpd5 20pF 300pF 300pF 300pF 300pF 1000 1000 1000 1000 Condition Min. Max. Unit
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Timing Waveform
tCPH tCPL
ST1,
Input
tpd1
tpd1
STX1, STX2
Output
tpd2 tpd2
OUT0~OUT257
-(OGW
tpd2 tpd2 tpd2
tpd2
tpd2
OUT0~257
VOFF
tpd2
-(OGW
tpd2
tpd2
tpd2
tpd2
tpd2
OUT0~OUT257
VOFF
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Timing Waveform (continued)
XOFF
twOFF tpd3 tpd3
VOFF
OUT0~OUT257
tpd4 tpd4
OUT0~OUT257
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
AD120
Ordering Information
Part AD120T Package
PRELIMINARY
(August, 2001, Version 0.0)
AMIC Technology,
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