ORCA Series Clocking Features Hardware Architecture Figure b

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ORCA Series Clocking Features Hardware Architecture Figure b

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ORCA® Series Clocking Overview
ORCA Series Clocking Features
Hardware Architecture
Figure block diagram Series FPGA architecture. Series includes significant embedded functionality including embedded block RAMs, integrated system bus, microprocessor interface, eight PLLs. eight PLLs dedicated broadband applications. targets T1/E1 rates, STS-3/STM-1 running 155.52 MHz. remaining general purpose operate from MHz. clocked registers device found following blocks: programmable logic cells (PLC), programmable cells (PICs), embedded block (EBR), system bus. Each contains circuitry four programmable I/Os (PIOs).
Abundant clock routing resources Primary, secondary, edge clock resources least edge clocks each four device edges (top, bottom, left, right). skew across entire FPGA Single-ended differential clock inputs Branch shut-off primary clock power savings Ability drive high fanout nets Phase-locked loop (PLL) friendly Cycle stealing increased internal performance. Automatically routed software
Introduction
ORCA Series revolutionary family highspeed FPGAs from Lattice Semiconductor Corporation. Series been designed delivery networking with improved performance decreased time-to-market mind. facilitate feature-rich, high-speed architecture Series flexible clocking scheme been developed.
ORCA Series Clocking Overview
Hardware Architecture (continued)
EMBEDDED BLOCK CLOCK PINS PLLs
H-SPINE
PRIMARY CLOCK CORE
BRANCHES
SYSTEM
LOGIC
HIGH-SPEED 0722(F)
Figure Series FPGA Architecture Block Diagram
Clock Types
There abundance clocking resources Series FPGA/FPSC. These resources categorized into three types clocks; primary, secondary, edge clocks. They differ based clocks distributed across array.
primary clocks low-skew clock tree resource called H-spine (refer Figure H-spine will provide lowest skew three clock types clocks that distributed globally across entire FPGA array (<400 skew across largest Series FPGA).
Primary Clocks
primary clock globally distributed clock, which there eight each Series FPGA/FPSC device. primary clock used clock design; however, when more than eight clocks present, used most heavily loaded, highest-frequency clocks. primary clock obtain source from external package configured input FPGA, derived from logic generated internal FPGA, from PLLs. Note that there cannot more than four primary clocks residing same side FPGA.
Lattice Semiconductor
ORCA Series Clocking Overview
user alter this resolution preference file. preference this called PRIMARY <net name>. This will force software <netname> primary clock resource ahead other clocks. using PRIMARY preference, order resolution selecting primary clocks software follows:
Clock Types (continued)
There recommended pins used primary clocks. Please refer package tables Series data sheet these locations (their functions listed PxCKxx). They positioned center each side package. These pins should used achieve lowest delay reaching Hspine routing resource. Software will automatically select these pins user does manually locate clock pins. Also, note that user select external pins clock other than these recommended pins still able route H-spines; however, path H-spine will slower. primary clock placed primary none being available (this happen user locates other signals primary locations), warning will issued software primary clock will placed different pin. internally generated primary clocks, source these clocks best placed close center FPGA optimal performance. Software will handle this automatically. Differential clock inputs supported Series series FPGAs. This accomplished instantiation differential clock buffer library elements into design. location these differential clock pairs handled same single-ended clocks. clock originates from PLL, those clocks will considered primary routed H-spine routing resources. Clocks originating from embedded ASIC block field-programmable system chip (FPSC) connect FPGA clock routing automatically. ORCA Foundry software will assign clock primary software detects more clock loads. following order resolution software:
User-specified primary clocks primary resources first. generated clocks remaining primary clock resources. Clock signals with greater than equal loads then assigned primary clock resources.
Secondary Clocks
Secondary clocks used clock control signals. (Example: control signals Series LSR, SEL.) clocking functions that take much logic (such function that contained within single quadrant FPGA, lower-frequency clocks when eight primary clock resources being used), secondary clocking used. fact, small module placed entirely within area FPGA farther than PLCs from edge array clocked external pin, desirable secondary clock save power primary clocks without skew increases. This also allows same clock used edge clock, will shown later. secondary clock sourced from same resources primary clock, external pin, internally generated from PLC, PLL, ASB. case external pin, there unique secondary clock coming into Series FPGA from PIC. Note that software will issue error message detects more than secondary clock from single (one consists four PIOs). There other restrictions selecting secondary clocks.
clocks assigned primary routing resources first. Clock signals with greater than equal component loads PFU, PIO, block equals load) then assigned.
there more than eight clocks design, software will select most heavily loaded clocks primary clock resources after clocks have been selected. remaining clocks will secondary clock routing resources, which explained later.
Lattice Semiconductor
ORCA Series Clocking Overview
FPGA). destinations edge clock PICs primary clock resource that edge clock also used system clock. Edge clock routing resources reside separate mask layers FPGA order interfere with other signals clocking resources design. routes same secondary clock resources that edge clock routes travel PICs (six PICs direction (left PICs other direction (right down), plus that clock comin from, total PICs) with very skew. Once clock goes past PICs direction, passes through buffer, delay about incurred. ORCA Foundry software identifies edge clock clock that connected flip-flop (please refer ORCA Foundry Libraries Manual definitions). fastest clock-to-out using edge clock, output flip-flop should placed that resides within distance source this clock. order lowest input hold times into FPGA, edge clock should used with zero hold latch (refer ORCA Foundry Libraries Manual Series User's Manual details).
Clock Types (continued)
Secondary clock routing resources reside separate mask layers FPGA order interfere with other signals clocking resources design. secondary clock routes bidirectional traces that buffered every PLCs apart. clock contained within this area (meaning PLCs each direction total PLCs) clock will have very skew. Once clock passes through buffer, delay about incurred. ORCA Foundry software will identify signal secondary clock detecting more clock loads. software will also secondary clock resources control signals that have more control type loads. Software will automatically start assigning clocks secondary clock resources when eight primary clock resources used. user modify this decision with SECONDARY <net name> preference. With this preference, user assign clock control signal from source secondary clock routing resources, thereby overriding software decision-making process.
Edge Clocks
Edge clocks clocks that reside perimeter Series FPGA. Edge clocks used very localized clocking elements. Because edge clocks incur significant skew (like secondary clocks), they suited clocking large busses. Although clock Series architecture used clock flip-flops (which reside PICs), edge clock will realize fastest clock-to-out lowest input setup time hold time parameters other than with resources. Note that preferred method getting best performance with PLLs that reside FPGA (refer application note). Series FPGAs allow least different edge clocks side device, improvement over previous FPGA architectures. source edge clock external configured input pin, from PLL. external pin, there edge clock input FPGA PIC. Once edge clock coming into PIC, there rules that must followed selecting other PICs edge clocks. These rules apply edge clocks same side Series FPGAs. source edge clock, there cannot another source edge clock that located multiple PICs away (e.g., PIC7 edge clock, then PICs etc., cannot used source another edge clock that side
Interconnection Secondary Clocks Edge Clocks
secondary clock perimeter device edge clock directly connected together driven same clock pin. This allows very highspeed localized clock networks with reduced power. single clock drive PICs, embedded block RAM, wide deep array PLCs. array extended directions through very fast programmable connections. Edge clocks that originate from external turn corners FPGA. This means that edge clock enters FPGA located less than PICs from corner, edge clock resource will connect reduced number registers that direction.
Lattice Semiconductor
ORCA Series Clocking Overview
with selectable clock delays every register, registerand register. This allows performance increases typical critical paths from 40%. ORCA Foundry 2001 Development System includes software automatically take advantage this capability increase overall system speed. This done after place route completed uses timing driven algorithms based user's preference file. hold time check also performed verify minimum hold time issues have been introduced.
Clock Types (continued)
Edge clocks that originate from turn corners. They span first PICs that adjacent that corner before getting buffered. When source edge clock PLL, first PICs that corner both directions cannot also serve source edge clock.
Clocks Signals
three clock types (primary, secondary, edge) reside clock routing resources. user needs clock input combinatorial logic driven off-chip through output buffer, clock signal will connect signal routing. This same routing also used route control signals, discussed previously.
Summary
Series FPGA FPSC devices offer large number clock routing resources that meet highspeed clocking needs. Although three types clock routing supported, ORCA Foundry software suite automatically takes care clock routing needs.
Cycle Stealing
feature Series FPGAs ability steal time from register-to-register path that time previous path before first register. This done
Lattice Semiconductor
www.latticesemi.com
Copyright 2002 Lattice Semiconductor Rights Reserved Printed U.S.A.
March 2002 AP01-025NCIP (Replaces AP00-073FPGA)

ORCA Series Clocking Features Hardware Architecture Figure b

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