8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F) data delay devices,

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8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F) data delay devices,

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PDU18F
8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F)
data delay devices, inc.
PACKAGES
OUT/
Digitally programmable delay steps Monotonic delay-versus-address variation separate outputs: inverting non-inverting Precise stable delays Input outputs fully interfaced buffered fan-out capability Fits standard 40-pin socket Auto-insertable
PDU18F-xx PDU18F-xxC5 Gull-Wing PDU18F-xxM Military PDU18F-xxMC5 Military Gull-Wing
FUNCTIONAL DESCRIPTION
PDU18F-series device 8-bit digitally programmable delay line. delay, TDA, from input (IN) output pins (OUT, OUT/) depends address code (A7-A0) according following formula: TINC
DESCRIPTIONS
OUT/ A0-A7 Delay Line Input Non-inverted Output Inverted Output Address Bits Output Enable Volts Ground
where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 0.5ns through 10ns, inclusively. enable pins (EN/) held during normal operation. These pins must always same state tied together externally. When these signals brought HIGH, OUT/ forced into HIGH states, respectively. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Programmed delay tolerance: 2ns, whichever greater Inherent delay (TD0): 13ns typical (OUT) 12ns typical (OUT/) Setup time propagation delay: Address input setup (TAIS): 10ns Disable output delay (TDISO): typ. (OUT) Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VCC: 5VDC Supply current: ICCH 65ma ICCL 128ma Minimum pulse width: total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU18F-.5 PDU18F-1 PDU18F-2 PDU18F-3 PDU18F-4 PDU18F-5 PDU18F-6 PDU18F-8 PDU18F-10 Incremental Delay Step (ns) Total Delay Change (ns) 127.5 12.8 25.5 38.3 1,020 51.0 1,275 63.8 1,530 76.5 2,040 102.0 2,550 127.5
NOTE: dash number between shown also available. ©1997 Data Delay Devices
#97006
1/14/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU18F
APPLICATION NOTES
ADDRESS UPDATE
PDU18F memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. similar situation occurs when using signal disable output while active. this case, unit must held disabled state until device able "clear" itself. This achieved holding signal high signal time given TDISH TINC Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TDISH elapsed.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
A7-A0 TAENS TENIS
TOAX TAIS
PWIN
TDISH
PWOUT
TDISO
TSKEW OUT/ Figure Timing Diagram
#97006
1/14/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU18F
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Output Skew Disable Output Delay Address Enable Setup Time Address Input Setup Time Enable Input Setup Time Output Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TSKEW TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN 14.0 UNITS TINC
10.0 Text Text
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER High Level Output Voltage Level Output Voltage High Level Output Current Level Output Current High Level Input Voltage Level Input Voltage Input Clamp Voltage Input Current Maximum Input Voltage High Level Input Current Level Input Current Short-circuit Output Current Output High Fan-out Output Fan-out SYMBOL IIHH 0.35 UNITS Unit Load NOTES MIN, MIN, MIN, MIN,
-1.0 20.0
-1.2 -0.6 -150 12.5
MIN, MAX, 7.0V MAX, 2.7V MAX, 0.5V
#97006
1/14/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU18F
PACKAGE DIMENSIONS
.580 MAX. .010 ±.002
.650 MAX.
2.100 MAX. Lead Material: Nickel-Iron alloy PLATE
.280 MAX.
.015 TYP. .018 TYP. .100 TYP. .070 MAX.
(PDU18F-xx, PDU18F-xxM)
.020 TYP.
.040 TYP.
.010±.002
.710 .590 ±.005 MAX.
.882 ±.005 .007 ±.005
.090 1.100 2.080±.020
.100
.280 MAX.
.050 ±.010
Gull-Wing (PDU18F-xxC5, PDU18F-xxMC5)
#97006
1/14/97
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU18F
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN Total Delay Period: PERIN Total Delay OUTPUT: Load: Cload: Threshold: FAST-TTL Gate 1.5V (Rising Falling)
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG TIME INTERVAL COUNTER
Test Setup
PERIN PWIN TRISE INPUT SIGNAL
2.4V 1.5V 0.6V
TFALL
2.4V 1.5V 0.6V
TDAF
TDAR OUTPUT SIGNAL
1.5V
1.5V
Timing Diagram Testing
#97006
1/14/97
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

8-BIT PROGRAMMABLE DELAY LINE (SERIES PDU18F) data delay devices,

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