3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-HOLD
MICRON CMOS Technology Typical tSK(0) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 0.40mm pitch TVSOP package Commercial range +70°C 3.3V 0.3V, Normal Range CMOS power levels (0.4µ typ. static) Rail-to-Rail output swing increased noise margin switching noise
IDT74ALVCHG162282
ALVCHG162282 provides synchronous data exchange between ports. Data stored internal registers low-to-high transition clock (CLK) input. data transfer B-to-A direction, select (SEL) input selects data outputs. data transfer A-to-B direction, two-stage pipeline provided path, with single storage register path. Data flow controlled active-low output enable (OE) direction-control (DIR) input. control registered synchronize direction changes with clock. port outputs have equivalent series resistors. port outputs have equivalent series resistors. switching characteristics this spec, based 25pF Port) 80pF Port) loads, production test accomplished with standard 50pF load. ALVCHG162282 "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
APPLICATIONS:
SDRAM Modules Motherboards Workstations
DESCRIPTION:
This 18-bit 36-bit registered exchanger manufactured using advanced dual metal CMOS technology. ALVCHG162282 intended applications which data must transferred from narrow highspeed wide lower-frequency bus.
FUNCTIONAL BLOCK DIAGRAM
Chan nels
1999 Integrated Device Technology, Inc.
JULY 2000
DSC-4558/-
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Unit
NEW16link
Symbol Description VTERM(2) Terminal Voltage with Respect VTERM(3) Terminal Voltage with Respect TSTG Storage Temperature IOUT Output Current Continuous Clamp Current, Continuous Clamp Current, Continuous Current through each
Max. ±100
NOTES: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. terminals. terminals except VCC.
SO80-1
CAPACITANCE +25oC, 1.0MHz)
Symbol Parameter(1) Control Inputs COUT CI/O Output Capacitance Port Capacitance ports) Conditions VOUT VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names Description 3-State Output Enable Input (Active LOW) Register Input Clock Select Input Data Inputs(1) 3-State Outputs Data Inputs(1) 3-State Outputs Direction Control Input
NOTE: These pins have "Bus-Hold." other pins standard inputs, outputs, I/Os.
TVSOP VIEW
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
FUNCTION TABLES(1)
A-TO-B STORAGE
Inputs
OUTPUT ENABLE
Inputs
Outputs
Outputs Active
1Bx,
Active 1B0-2B0(2)
L(3) H(3)
B-TO-A STORAGE
Inputs
Outputs L(4) H(4)
NOTES: HIGH Voltage Level Voltage Level Don't Care High-Impedance LOW-to-HIGH Transition Output level before indicated steady-state input conditions were established. edges needed propagate data. edges needed propagate data. data loaded first register when propagates second register when HIGH.
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(1)
Following Conditions Apply Unless Otherwise Specified: Operating Condition: +70°C Symbol IOZH IOZL ICCL ICCH ICCZ Parameter Input HIGH Voltage Level Input Voltage Level Input Input HIGH Current(2) Current(2) Test Conditions 3.6V 3.6V 3.6V 3.6V 3.6V 3.3V 3.6V input 0.6V, other inputs 3-3.6V Min. Typ.(1) Max. Unit
High Impedance Output Current (excludes bus-hold pins) Input Hysteresis Quiescent Power Supply Current
Quiescent Power Supply Current Variation
NOTES Typical values 3.3V, +25°C ambient. control I/P's only excludes bus-hold current.
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current
3.0V 3.6V
Test Conditions 2.0V 0.8V 3.6V
Min.
Typ.(2)
Max.
Unit
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage port port) port port) Output Voltage port port) port port)
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 70°C.
Test Conditions(1) 3.6V 0.1mA 3.0V 3.0V 3.6V 3.0V 0.1mA
Min.
Max.
Unit
OPERATING CHARACTERISTICS, 25oC
3.3V 0.3V Symbol Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
SWITCHING CHARACTERISTICS, 25pF port), 80pF port)
3.3V 0.3V Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ tPHZ tPLZ fCLOCK
NOTES: test circuits waveforms. +70°C. This parameter warranted production tested.
Parameter Propagation Delay Propagation Delay Output Enable Time Output Enable Time Output Enable Time Output Enable Time Output Disable Time Output Disable Time Output Disable Time Output Disable Time Setup Time, HIGH LOW, data before Setup Time, HIGH LOW, data before Setup Time, HIGH LOW, before Setup Time, HIGH LOW, before Hold Time, HIGH LOW, data after Hold Time, HIGH LOW, data after Hold Time, HIGH LOW, after Hold Time, HIGH LOW, after Pulse Duration, HIGH
Min. 2.3(2)
Max.
Unit
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
TEST CIRCUITS WAVEFORMS TEST CONDITIONS PROPAGATION DELAY
Symbol VLOAD VCC(1)= 3.3V 0.3V 25pF Port), 80pF Port) Unit
OPPOSITE PHASE INPUT TRANSITION SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL
ALVC Link
TEST CIRCUITS OUTPUTS
Pulse Generator
VLOAD Open
ENABLE DISABLE TIMES
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY VLOAD tPZH OUTPUT SWITCH NORMALLY HIGH VLOAD/2 tPHZ tPLZ DISABLE VLOAD/2
D.U.T.
VOUT
ALVC Link
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator.
NOTE: Pulse Generator Pulses: Rate 10MHz; 2.5ns; .5ns
NOTE: ALVC Link Diagram shown input Control Enable-LOW input Control Disable-HIGH.
SET-UP, HOLD, RELEASE TIMES
DATA INPUT
ALVC Link
SWITCH POSITION
Test Disable Enable Disable High Enable High Other tests Switch VLOAD Open
TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL tREM
PULSE WIDTH
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
ALVC Link
IDT74ALVCHG162282 3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER
ORDERING INFORMATION
ALVC Device Type Package Range Bus-Hold
Thin Very Small Outline Package (SO80-1) 18-Bit 36-Bit Registered Exchanger 3-State Outputs
G162 Double-Density with Resistors Bus-Hold +70°C
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3.3V CMOS 18-BIT 36-BIT REGISTERED EXCHANGER WITH 3-STATE OUTPUTS BUS-

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