1:10 Zero-Delay Clock Buffer Features Description Gener

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1:10 Zero-Delay Clock Buffer Features Description Gener

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FS612510-01/-02
1:10 Zero-Delay Clock Buffer
Features
Description
Generates bank clock outputs (1Y0 1Y9) from reference clock input (CLK) Designed meet Component Specifications noted PC133 SDRAM Registered DIMM Design Specification External feedback input (FBIN) synchronize clock outputs reference input Operating frequency 25MHz 140MHz Tight tracking skew (spread-spectrum tolerant) On-chip series damping resistors driving point-to-point loads Output enable enables disables clock outputs Available with auto power-down option that turns forces outputs when reference clock stops (FS612510-02) Packaged 24-pin TSSOP
FS612510 skew, jitter CMOS zero-delay phase-lock loop (PLL) clock buffer designed highspeed motherboard applications, such those using 133MHz SDRAM. buffered clock outputs derived from onboard open-loop PLL. aligns frequency phase output clocks reference input clock CLK, including FBOUT clock that feeds back FBIN close loop. Multiple power ground supplies help reduce effects noise device performance. outputs enabled disabled active-high signal. bypassed test purposes pulling AVDD ground.
Figure Configuration
AGND
AVDD FBIN
Figure Block Diagram
FS612510
FBOUT
AVDD
FBIN
AGND
Zero-Delay
Table Function Table
INPUT AVDD OUTPUT 1Y0-1Y9 FBOUT
FS612510
FBOUT
American Microsystems, Inc. reserves right change detail specifications required permit improvements design products.
ISO9001 QS9000
Bypass
FS612510-01/-02
1:10 Zero-Delay Clock Buffer
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
TYPE
NAME AVDD AGND FBIN FBOUT Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output Clock output
DESCRIPTION
Enabled
Power Supply Test mode enable. This provides power supply internal PLL. When pulled low, bypassed output clocks directly follow input clock supply ground Reference clock input (Note: version pull-down this pin) Feedback clock input; must connected FBOUT complete loop Feedback output clock Output enable stops clocks (1Y0 1Y9) state when this Ground clock outputs Power supply clock outputs
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
Power-Down
Device Operation
FS612510 zero-delay buffer intended buffered PC133 SDRAM DIMMs. FS612510 precisely aligns frequency phase output clocks input on-chip phase-lock loop (PLL). generates lowskew, low-jitter copies CLK, with outputs adjusted duty cycle. FBOUT clock must hardwired FBIN complete loop. actively adjusts output clocks that there phase error between reference clock (CLK) feedback clock (FBIN). Since device uses lock output clocks input clock, there power-up stabilization time that required achieve phase lock. Note that inputs outputs LVCMOS signal levels.
FS612510-02 version provides auto power-down feature that shuts PLL, drives outputs low, places device into current state reference clock stops. power-down circuit level sensitive, detects either high input.
Tracking Skew
PLL-based buffer required follow spreadspectrum modulated reference clock frequencies greater than 66MHz. Spread spectrum modulation limits peak emissions intentionally introducing jitter onto clock signal, effectively spreading peak energy over range frequencies. downstream PLL, contained clock buffer such this one, must carefully track modulated input reference clock. measure closely downstream follows modulated clock called tracking skew. ensure tight tracking skew, loop bandwidth downstream increased loop phase angle reduced over that typical PLL-based clock generators. type modulation profile used impacts tracking skew. maximum frequency change occurs profile limits where modulation changes slew rate polarity. track sudden reversal clock frequency, downstream must have large loop bandwidth. ability downstream catch modulating clock determined loop transfer function phase angle. spread-spectrum reference clock should either triangle-wave non-linear (Lexmark) modulation profile, with modulation frequency 50kHz less.
Bypass
When AVDD pulled low, reference clock signal bypasses muxed directly through outputs. powered down, device acts fanout buffer. Note that AVDD re-established, requires power-up stabilization time lock input clock.
Output Enable/Disable
outputs enabled disabled group enable signal. logic-high input enables clock outputs swing phase with reference clock. logic-low forces clock outputs logic-low state. function table Table shows effect enable signal clock outputs.
ISO9001 QS9000
FS612510-01/-02
1:10 Zero-Delay Clock Buffer
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage, Clock Buffers (VSS ground) Supply Voltage, Core Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL AVDD
MIN.
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage, Core Outputs Ambient Operating Temperature Range Output Load Capacitance Input Frequency Input Duty Cycle Input Rise/Fall Time SYMBOL fCLK CONDITIONS/DESCRIPTION 3.3V MIN. TYP. MAX. UNITS
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V%, load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall Supply Current, Dynamic Supply Current, Static Output Enable Input High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Clock Inputs (CLK, FBIN) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Loading Capacitance Clock Outputs (1Y0:9, FBOUT) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current Short Circuit Sink Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
fCLK 133.33MHz; 3.3V IDDL CL(in) version version pull-down seen external clock driver Outputs low; 3.3V VSS-0.3
VDD+0.3
VSS-0.3
VDD+0.3
IOSH IOSL
2.9V, 2.0V 3.7V, 2.0V 2.9V, 0.8V 3.7V, 0.8V shorted 30s, max. 3.3V; shorted 30s, max.
Table Clock Output Drive (1Y0:4, 2Y0:3, FBOUT)
Voltage Drive Current (mA) High Drive Current (mA)
Output Current (mA)
Output Voltage
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V, load output, ambient temperature 25°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical.
PARAMETER Overall Skew, Output Output Skew, Tracking Static Phase Error Clock Stabilization Time Loop Bandwidth Phase Angle Clock Outputs (1Y0:9, FBOUT) Duty Cycle Jitter, Cycle-Cycle Jitter, Period (peak-peak) Rise Time Fall Time Enable Delay Disable Delay
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
tsk(o)
Measured rising edge 1.65V; 15pF Measured using -0.5% 31.5kHz spread spectrum reference clock 133.33MHz From rising edge rising edge FBIN Time required achieve phase lock calculation Tracking Skew calculation Tracking Skew -120
-0.031
tj(CC) tj(P) tDLH tDHL
Ratio high pulse width clock period, measured 1.65V Adjacent cycles 1.65V From rising edge next rising edge 1.65V 0.4V 2.0V; 15pF 2.0V 0.4V; 15pF
Figure Clock Skew Measurement
output clock skew (tsk(o)) output
Figure Phase Error Measurement
phase error FBIN
Figure Timing Measurement Points
3.3V 2.4V
Figure Output Enable Measurement
Output Enable
0.4V
Output
tDLZ
tDZL
tDHZ
tDHZ
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
Package Information
Table 24-pin TSSOP Package Dimensions
DIMENSIONS INCHES MIN. 0.002 0.0315 0.0075 0.0035 0.303 0.169 MAX. 0.047 0.006 0.0413 0.0118 0.0079 0.311 0.177 MILLIMETERS MIN. 0.05 0.80 0.19 0.09 7.70 4.30 MAX. 1.20 0.15 1.05 0.30 0.20 7.90 4.50
AMERICAN MICROSYSTEMS, INC.
0.252 0.0256 0.0177 0.0079 0.0295
6.40 0.65 0.45 0.20 0.75
SEATING PLANE
BASE PLANE
Table 24-pin TSSOP Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Longest lead Longest lead adjacent lead Longest lead adjacent lead Longest lead Longest lead adjacent lead Longest lead adjacent lead TYP. 0.24 0.007 UNITS °C/W
ISO9001 QS9000
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1:10 Zero-Delay Clock Buffer
Ordering Information
Table Device Ordering Codes
DEVICE NUMBER FS612510-01 FS612510-02 ORDERING CODE PACKAGE TYPE 24-pin TSSOP (Thin Shrink Small Outline Package) 24-pin TSSOP (Thin Shrink Small Outline Package) OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) SHIPPING CONFIGURATION Tape Reel Tape Reel
12055-102 12055-103
Copyright 2000 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
ISO9001 QS9000

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