Implementing GTLP Drivers Mb/s Backplanes Introduction Background

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Implementing GTLP Drivers Mb/s Backplanes Introduction Background

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MSAN-188
Implementing GTLP Drivers Mb/s Backplanes
Introduction Background Information Implementation Output Control Using BCSTo Signals Hardware 3.2.1 CPLD/FPGA 3.2.2 Termination Voltage 3.2.3 Impedance Matching 3.2.4 Example Schematic Conclusions References
AN5647 ISSUE March 2002
externally while receiver differential input which referenced Vref (GTLP Vref =1V). Figure shows typical input output configuration port. GTLP (Gunning Transceiver Logic Plus) modification where signal swing been widened. comparison GTLP levels seen Table Parameter VREF 1.2V 0.85V 0.8V 0.75V 0.4V GTLP 1.5V 1.2V 1.0V 0.8V 0.6V
Appendix Verilog Code GTLP Backplane Information
Table GTLP Switching Levels
Implementation
Introduction
data rates serial streams increase, standard LVTTL (Low Voltage TTL) most suitable long backplane buses reflected signals. Therefore, with high density digital switches with high speed backplane running 32MB/s, necessary convert LVTTL inputs outputs faster technology such GTLP (Gunning Transceiver Logic Plus). This application note describes simple circuit that used connect 32Mb/s streams from Zarlink's high-density switches such MT90869 (16K 16K) MT90870 (12K 12K) backplane through LVTTL-GTLP level converter. circuit presented implements interface bi-directional per-channel basis) 32Mb/s backplane.
Most GTLP drivers designed parallel applications (groups GTLP transceivers with individual output enable controls difficult find. Since some control circuitry required, most efficient implement LVTTL GTLP interface CPLD/FPGA with GTLP drivers receivers. following section outlines design implementation LVTTL GTLP interface.
Bias Voltage Vref
Background Information
Input Structure Logic Signal
Bias Voltage VOUT
(Gunning Transceiver Logic) technology introduced William Gunning Xerox Corporation. This low-swing input/output driver technology developed facilitate high-speed data transfer backplane. transmitter consists differential open-drain transistor which pulled-high
SEMICMF.020
Output Structure
Figure Typical Input Output Structures
MSAN-188
Output Control Using BCSTo Signals
help implement tri-state GTLP buffer, high bandwidth digital switches designed with external high impedance buffer control streams (BCSTo). These streams, conjunction with frame pulse system clock, allow designers control GTLP buffers through software digital switch. BCSTo0-3 signals digital switch BORS must held low. setting BORS LOW, digital switch configures output streams (BSTo0-31), transmit bi-state channel data with per-channel high-impedance determined external circuits under control BCSTo0-3 outputs. data (channel control bit) transmitted BCSTo0-3 replicates Backplane Output Enable (BE) Backplane Connection Memory, with state indicating that channel High Impedance. BCSTo outputs transmit serial data (channel control bits) 16.384Mb/s, with each representing per-channel high impedance state specific streams. Four output streams allocated each control line follows: BCSTo0 BCSTo1 BCSTo2 BCSTo3 outputs outputs outputs outputs channel channel channel channel control control control control bits bits bits bits streams streams streams streams BSTo0, BSTo1, BSTo2, BSTo3,
SEMICMF.020
SEMICMF.020
BSTo0 (32Mb/s)
BSTo3 (32Mb/s)
BSTo2 (32Mb/s)
BSTo1 (32Mb/s)
BCSTo3
BSTo3 BSTo7 BSTo11 Channel bits Channel bits Channel bits BSTo15 BSTo3 BSTo7 BSTo11 BSTo15 BSTo3 BSTo7 BSTo6 BSTo5 BSTo4 BSTo2 BSTo1 BSTo0 BSTo14 BSTo13 BSTo12 BSTo10 BSTo9 BSTo8 Channel bits Channel bits Channel bits Channel bits BSTo6 BSTo5 BSTo4 BSTo2 BSTo1 BSTo0 BSTo14 BSTo13 BSTo12 BSTo10 BSTo9 BSTo8 Channel bits BSTo6 BSTo5 BSTo4 BSTo2 BSTo1 BSTo0 BSTo11 BSTo15 BSTo3 BSTo7 BSTo11 BSTo15 BSTo3 BSTo7 BSTo11 BSTo15 BSTo6 BSTo10 BSTo14 BSTo2 BSTo6 BSTo10 BSTo14 BSTo2 BSTo14 BSTo10 BSTo9 BSTo13 BSTo1 BSTo5 BSTo9 BSTo13 BSTo1 BSTo5 BSTo9 BSTo13 BSTo8 BSTo12 BSTo0 BSTo4 BSTo8 BSTo12 BSTo0 BSTo4 BSTo8 BSTo12 Channel bits Channel bits Channel bits Channel bits Channel bits Channel bits Channel bits Channel bits
BCSTo2
BCSTo1
BCSTo0
FP8o
cycle
Figure shows channel alignment BSTo referenced appropriate BCSTo signal.
Figure BCSTo Signals MT90869 Mbps Mode)
MSAN-188
MSAN-188
Hardware
This section explains reference design shown figure outlines recommended devices PLD, voltage regulator impedance matching.
3.2.1
CPLD/FPGA
implementation this design targeted toward device (CPLD FPGA) which GTLP port. list suitable devices (available time this application note published) presented Table Devices FPGA Manufacturer Xilinx Part Virtex Virtex-E Virtex-II Spartan-II Altera Max7000B APEX20KE, APEX20KC CPLD Cypress Delta39K Internal Logic 2.5V 1.8V 1.5V 2.5V 2.5V 1.8V 3.3V
Table CPLD FPGA Devices Implementation Design
3.2.2
Termination Voltage
Since output section GTLP driver open drain transistor, must tied 1.5V termination voltage (VTT). pull resistor should equal termination resistance most applications this would From this determined that each GTLP output port must able sink 30mA.
3.2.3
Impedance Matching
terminating resistors (RT) chosen match impedance backplane load order minimize signal reflection. model backplane depicted Figure where capacitance each board backplane trace capacitance capacitance unit length) with length
Figure Transmission Line Model
SEMICMF.020
MSAN-188
terminating resistor should chosen match effective impedance backplane this case 50). Depending load backplane well capacitance trace, optimal terminating resistor value different different backplanes. Note that since there termination resistors both ends backplane bus, resistors effect parallel each other. Therefore, resistor value should double value effective impedance (for example characteristic impedance would require termination resistor each backplane).
3.2.4
Example Schematic
example schematic presented Figure Xilinx XCV50E (CS144 package) Virtex-E family used implement LVTTL-GTLP conversion. designed according manufacturer's suggestions assumes that FPGA will programmed Master-serial Slave-serial mode. design should changed accordingly other modes used programming FPGA. Verilog code presented appendix been designed monitor BSCTo streams extract proper control signals either activate GTLP drivers tri-state them. align serial control bits appropriate stream channel, number system clock cycles between BCSTo control frame pulse counted. Given information section 3.1, alignment determined GTLP drivers activated into high impedance.
SEMICMF.020
MSAN-188
Summary
data rate backplanes increases this case 32Mb/s) accommodate higher bandwidths, designers need concerned about backplane design signal conditioning reduce backplane reflection. solution open designers GTLP drivers. Since these drivers designed primarily applications, difficult find discrete GTLP drivers with individual high impedance control; therefore implement GTLP drivers backplane, more cost effective with integrated GTLP drivers. When designing GTLP backplane, traces should properly terminated reduce reflections. Zarlink flexible architecture switches provide control streams that, conjunction with frame pulse system clock, used control individual GTLP drivers.
References
Johnson, Howard Graham, Martin. High-speed digital design: handbook black magic. Jersey: Prentice Hall PTR, 1993. Balasubramaniam, Shankar, Ammar, Ranzi, Cox, Ernest, Texas Instruments Inc. High-Performance Backplane Design With GTL+. Texas Instruments, October 1999. Literature Number SCEA011A.
SEMICMF.020
Appendix Verilog Code GTLP Backplane Implementation
MSAN-188
//-// GTLP_IO_Control Module This module provides Control Signals GTLP Backplane using input signals nRESET, nC16, nFP16, BCSTo Temporary Registers used store BCSTo values each stream Channel BCSTo values stored channels (i.e. bits) with counter Created: June 2001 Copyright 2001, Zarlink Semiconductor rights reserved. Redistribution source binary forms, with without modification, permitted. Neither name Zarlink Semiconductor names contributors used endorse promote products derived from this software without specific prior written permission. THIS SOFTWARE PROVIDED COPYRIGHT HOLDERS CONTRIBUTORS EXPRESS IMPLIED WARRANTIES, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE DISCLAIMED. EVENT SHALL REGENTS CONTRIBUTORS LIABLE DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, CONSEQUENTIAL DAMAGES (INCLUDING, LIMITED PROCUREMENT SUBSTITUTE GOODS SERVICES; LOSS USE, DATA, PROFITS; BUSINESS INTERRUPTION) HOWEVER CAUSED THEORY LIABILITY, WHETHER CONTRACT, STRICT LIABILITY, TORT (INCLUDING NEGLIGENCE OTHERWISE) ARISING THIS SOFTWARE, EVEN ADVISED POSSIBILITY SUCH DAMAGE.
SEMICMF.020
MSAN-188
module GTLP_IO_Control (nRESET, nC16, nFP16, BCSTo, BSTi, BSTo, GTLP_BSTio); input input input output input inout integer nRESET; nC16, nFP16; [3:0] BCSTo; [15:0] BSTi; [15:0] BSTo; [15:0] GTLP_BSTio; Input Reset Signal 16MHz clock 8kHz frame pulse BCSTo Control Signals Output MT90869 Input from MT90869 GTLP Backplane Signal
[31:0] Stored_BCSTo; Temporary Registers BCSTo signals [15:0] GTLP_Control; Control GTLP Buffers [2:0] counter; Counter_Valid; [15:0] GTLP_BSTio; [15:0] BSTi;
always @(negedge nC16 negedge nRESET) begin (!nRESET) Reset registers Counter valid begin counter 3'b110; Counter_Valid 1'b0; else begin (!nFP16) begin Reset counter counter 3'b110; (!Counter_Valid) Counter valid after nFP16 goes Counter_Valid 1'b1; else (Counter_Valid) Increment counter counter (counter==3'b111)? 3'b0 counter+1; (i=0; i<16; i=i+1) begin Clock GTLP_BSTio BSTi data GTLP_BSTio[i] GTLP_Control[i]? BSTo[i]: 1'bz; BSTi[i] GTLP_Control[i]? 1'b0: GTLP_BSTio[i];
SEMICMF.020
always @(posedge nC16 negedge nRESET) begin (!nRESET) begin Clear GTLP_Control Temporary registers GTLP_Control <=32'h0; Stored_BCSTo[31:0] <=32'h0; else (Counter_Valid) case (counter) Store BCSTo values Clock GTLP_Control Signals 3'b000: Stored_BCSTo[3:0] BCSTo; 3'b001: begin Stored_BCSTo[7:4] BCSTo; GTLP_Control Stored_BCSTo[31:16]; 3'b010: Stored_BCSTo[11:8] BCSTo; 3'b011: Stored_BCSTo[15:12] BCSTo; 3'b100: Stored_BCSTo[19:16] BCSTo; 3'b101: begin Stored_BCSTo[23:20] BCSTo; GTLP_Control Stored_BCSTo[15:0]; 3'b110: Stored_BCSTo[27:24] BCSTo; 3'b111: Stored_BCSTo[31:28] BCSTo; endcase endmodule
MSAN-188
SEMICMF.020
+3.3V +1.8V +1.5V
value decoupling capacitors determined designer.
LSTo[31.0]
LSTi[31.0]
MT90869
Local Data
termination resistance dependent effective impedance.
RESISTOR 8PACK
RESISTOR 8PACK
GTLP_BSTio[15.0]
VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCO VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT
MT90869
XCV50E_CS144
Backplane
LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31 +3.3V BSTo16 BSTo17 BSTo18 BSTo19 BSTo20 BSTo21 BSTo22 BSTo23 BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 BSTo0 BSTo1 BSTo2 BSTo3 BSTo4 BSTo5 BSTo6 BSTo7 BSTo8 BSTo9 BSTo10 BSTo11 BSTo12 BSTo13 BSTo14 BSTo15 GTLP_BSTio0 GTLP_BSTio1 GTLP_BSTio2 GTLP_BSTio3 GTLP_BSTio4 GTLP_BSTio5 GTLP_BSTio6 GTLP_BSTio7 GTLP_BSTio8 GTLP_BSTio9 GTLP_BSTio10 GTLP_BSTio11 GTLP_BSTio12 GTLP_BSTio13 GTLP_BSTio14 GTLP_BSTio15 GTLP_BSTio0 GTLP_BSTio1 GTLP_BSTio2 GTLP_BSTio3 GTLP_BSTio4 GTLP_BSTio5 GTLP_BSTio6 GTLP_BSTio7 GTLP_BSTio8 GTLP_BSTio9 GTLP_BSTio10 GTLP_BSTio11 GTLP_BSTio12 GTLP_BSTio13 GTLP_BSTio14 GTLP_BSTio15
LCSTo0 LCSTo1 LCSTo2 LCSTo3 VREF VREF VREF VREF
LSTi0 LSTi1 LSTi2 LSTi3 LSTi4 LSTi5 LSTi6 LSTi7 LSTi8 LSTi9 LSTi10 LSTi11 LSTi12 LSTi13 LSTi14 LSTi15 LSTi16 LSTi17 LSTi18 LSTi19 LSTi20 LSTi21 LSTi22 LSTi23 LSTi24 LSTi25 LSTi26 LSTi27 LSTi28 LSTi29 LSTi30 LSTi31
LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31
LSTo0 LSTo1 LSTo2 LSTo3 LSTo4 LSTo5 LSTo6 LSTo7 LSTo8 LSTo9 LSTo10 LSTo11 LSTo12 LSTo13 LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 LSTo30 LSTo31
LCSTo0 LCSTo1 LCSTo2 LCSTo3
LCSTo[3.0]
D[15.0]
10Kohm BSTi16 BSTi17 BSTi18 BSTi19 BSTi20 BSTi21 BSTi22 BSTi23 BSTi24 BSTi25 BSTi26 BSTi27 BSTi28 BSTi29 BSTi30 BSTi31 BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi9 BSTi10 BSTi11 BSTi12 BSTi13 BSTi14 BSTi15 10Kohm Resistor Pack BCSTo0 BCSTo1 BCSTo2 BCSTo3 BCSTo0 BCSTo1 BCSTo2 BCSTo3 RESET nC16 nFP16 +3.3V C16o FP16o FP8o DIP-3 RESET BORS LORS FP8i CLKBYPS HEADER MT90869
Resistor Pack
MT90869
A[14.0]
Microprocessor
4.7Kohm
Programming FPGA
nDTA
DONE INIT PROGRAM DOUT/BUSY DIN/DO CCLK
DONE INIT PROGRAM DOUT/BUSY DIN/D0 CCLK
nFP8i nC8i VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_CORE VDD_PLL VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO MT90869
+1.8V
+3.3V
MT90869
+3.3V 100uF 100uF LT1585A-1.5 VOUT 100uF 100uF 100uF 100uF 75ohm
nRESET BORS LORS
+1.5V
nTRST
TRST
Generation Termination Voltage (+1.5V) Reference Voltage (+1V)
150ohm
0.1uF
Title GTLP Backplane Implementation Size Date:
Document Number <Doc> Friday, June 2001
Sheet
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Implementing GTLP Drivers Mb/s Backplanes Introduction Background

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