SYNCBURSTSRAM Fast clock access times Single +3.3V +0.3V/-0.165V
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4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
SYNCBURSTSRAM
Fast clock access times Single +3.3V +0.3V/-0.165V power supply (VDD) Separate +3.3V isolated output buffer supply (VDDQ) SNOOZE MODE reduced-power standby Common data inputs data outputs Individual BYTE WRITE control GLOBAL WRITE Three chip enables simple depth expansion address pipelining Clock-controlled registered addresses, data I/Os control signals Internally self-timed WRITE cycle Burst control (interleaved linear burst) Automatic power-down portable applications 165-pin FBGA package 100-pin TQFP package capacitive loading x18, x32, versions available
MT58L256L18D1, MT58L128L32D1, MT58L128L36D1
3.3V VDD, 3.3V I/O, Pipelined, DoubleCycle Deselect
100-Pin TQFP1
165-Pin FBGA
OPTIONS
Timing (Access/Cycle/MHz) 3.5ns/6ns/166 4.0ns/7.5ns/133 5ns/10ns/100 Configurations 256K 128K 128K Packages 100-pin TQFP 165-pin FBGA Operating Temperature Range Commercial (0°C +70°C) Industrial (-40°C +85°C)**
Part Number Example:
MARKING
-7.5
NOTE: JEDEC-standard MS-026 (LQFP).
MT58L256L18D1 MT58L128L32D1 MT58L128L36D1 None
GENERAL DESCRIPTION
Micron® SyncBurstSRAM family employs high-speed, low-power CMOS designs that fabricated using advanced CMOS process. Micron's SyncBurst SRAMs integrate 256K 128K 128K SRAM core with advanced synchronous peripheral circuitry 2-bit burst counter. synchronous inputs pass through registers controlled positive-edge-triggered single clock input (CLK). synchronous inputs include addresses, data inputs, active chip enable (CE#), additional chip enables easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) global write (GW#).
MT58L256L18D1T-6
Part Marking Guide FBGA devices found Micron's Industrial temperature range offered specific speed grades configurations. Contact factory more information.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM 256K
SA0, SA1, MODE ADV# ADDRESS REGISTER
SA0-SA1 SA1'
BINARY COUNTER LOGIC
SA0'
ADSC# ADSP# BYTE WRITE REGISTER BYTE WRITE DRIVER 512K MEMORY ARRAY SENSE AMPS
BWb#
OUTPUT REGISTERS
OUTPUT BUFFERS
BWa# BWE# CE2#
BYTE WRITE REGISTER
BYTE WRITE DRIVER
DQPa DQPb
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
FUNCTIONAL BLOCK DIAGRAM 128K 32/36
SA0, SA1,
ADDRESS REGISTER
SA0-SA1
MODE ADV# BINARY COUNTER SA0'
SA1'
ADSC# ADSP# BWd# BYTE WRITE REGISTER BYTE WRITE REGISTER
BYTE WRITE DRIVER BYTE WRITE DRIVER BYTE WRITE DRIVER BYTE WRITE DRIVER
BWc#
256K (x32) 256K (x36) SENSE AMPS
OUTPUT REGISTERS
BWb#
BYTE WRITE REGISTER
MEMORY ARRAY
OUTPUT BUFFERS
DQPa
DQPd
BWa# BWE# CE2#
BYTE WRITE REGISTER
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
NOTE: Functional block diagrams illustrate simplified device operation. truth tables, descriptions, timing diagrams detailed information.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
Asynchronous inputs include output enable (OE#), clock (CLK) snooze enable (ZZ). There also burst mode input (MODE) that selects between interleaved linear burst modes. data-out (Q), enabled OE#, also asynchronous. WRITE cycles from bytes wide (x18) from four bytes wide (x32/x36), controlled write control inputs. Burst operation initiated with either address status processor (ADSP#) address status controller (ADSC#) inputs. Subsequent burst addresses internally generated controlled burst advance input (ADV#). Address write control registered on-chip simplify WRITE cycles. This allows self-timed write cycles. Individual byte enables allow individual bytes written. During WRITE cycles device, BWa# controls pins DQPa; BWb# controls pins DQPb. During WRITE cycles devices, BWa# controls pins DQPa; BWb# controls pins DQPb; BWc# controls pins DQPc; BWd# controls pins DQPd. causes bytes written. Parity bits only available versions. This device incorporates additional pipelined enable register which delays turning output buffer additional cycle when deselect executed. This feature allows depth expansion without penalizing system performance. Micron's SyncBurst SRAMs operate from +3.3V power supply, inputs outputs TTL-compatible. device ideally suited Pentium® PowerPC pipelined systems systems that benefit from very wide, high-speed data bus. device also ideal generic 16-, 18-, 32-, 36-, 64-, 72-bit-wide applications. Please refer Micron's site (www.micron.com/ sramds) latest data sheet.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TQFP ASSIGNMENT TABLE
x32/x36 NC/DQPc* VDDQ VDDQ VDDQ DQPb x32/x36 VDDQ NC/DQPd* MODE NF** NF** x32/x36 NC/DQPa* VDDQ VDDQ VDDQ DQPa x32/x36 VDDQ NC/DQPb* ADV# ADSP# ADSC# BWE# CE2# BWa# BWb# BWc# BWd#
Connect (NC) used version. Parity (DQPx) used version. **Pins reserved address expansion, 16Mb respectively.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
ASSIGNMENT (TOP VIEW) 100-PIN TQFP
VDDQ DQPa VDDQ VDDQ VDDQ
ADV# ADSP# ADSC# BWE# CE2# BWa# BWb#
NF** NF** MODE
ADV# ADSP# ADSC# BWE# CE2# BWa# BWb# BWc# BWd#
NC/DQPb* VDDQ VDDQ VDDQ VDDQ NC/DQPa*
VDDQ VDDQ VDDQ DQPb VDDQ
x32/x36
NF** NF** MODE
Connect (NC) used version. Parity (DQPx) used version. **Pins reserved address expansion, 16Mb respectively.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
NC/DQPc* VDDQ VDDQ VDDQ VDDQ NC/DQPd*
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TQFP DESCRIPTIONS
x32/x36 SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK. 32-35, 44-50, 32-35, 44-50, 80-82,
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls pins DQPa; BWb# controls pins DQPb. versions, BWa# controls pins DQPa; BWb# controls pins DQPb; BWc# controls pins DQPc; BWd# controls pins DQPd. Parity only available versions. Byte Write Enable: This active input permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Global Write: This active input allows full 18-, 36-bit WRITE occur independent BWE# BWx# lines must meet setup hold times around rising edge CLK. Clock: This signal registers address, data, chip enable, byte write enables burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device conditions internal ADSP#. sampled only when external address loaded. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. Output Enable: This active LOW, asynchronous input enables data output drivers. Synchronous Address Advance: This active input used advance internal burst counter, controlling burst access after external address loaded. HIGH this effectively causes wait states generated address advance). ensure correct address during WRITE cycle, ADV# must HIGH rising edge first clock after ADSP# cycle initiated.
BWE#
Input
Input
Input
Input
CE2#
Input
Input
Input
ADV#
Input Input
(continued next page)
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TQFP DESCRIPTIONS (continued)
x32/x36 SYMBOL ADSP# TYPE Input DESCRIPTION Synchronous Address Status Processor: This active input interrupts ongoing burst, causing external address registered. READ performed using address, independent byte write enables ADSC#, dependent upon CE#, CE2#. ADSP# ignored HIGH. Powerdown state entered CE2# HIGH. Synchronous Address Status Controller: This active input interrupts ongoing burst, causing external address registered. READ WRITE performed using address LOW. ADSC# also used place chip into power-down state when HIGH. Mode: This input selects burst sequence. this selects "linear burst." HIGH this selects "interleaved burst." alter input state while device operating.
ADSC#
Input
MODE
Input
56-59, 72-75, 6-9, 22-25,
Input/ SRAM Data I/Os: version, Byte pins; Byte Output pins. versions, Byte pins; Byte pins; Byte pins; Byte pins. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDDQ Connect/Parity Data I/Os: version, these pins Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
1-3, 28-30, 51-53,
Supply Power Supply: Electrical Characteristics Operating Conditions range. Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range. Supply Ground: GND.
Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation.
Function: These pins internally connected will have capacitance input pins. allowable leave these pins unconnected driven signals. Reserved address expansion, becomes density becomes 16Mb density.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
LAYOUT (TOP VIEW) 165-PIN FBGA
x32/x36
DQPb MODE (LBO#) VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQPa BWa# (G#) ADSP# BWb# CE2# BWE# ADSC# ADV#
BWc# BWb# CE2# BWE# ADSC# ADV#
BWd# BWa# (G#) ADSP#
NC/DQPc
VDDQ VDDQ
NC/DQPb
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
VDDQ VDDQ
NC/DQPd
VDDQ VDDQ
NC/DQPa
MODE (LBO#)
VIEW
VIEW
Connect (NC) used version. Parity (DQPx) used version. NOTE: Pins 11P, reserved address expansion; 8Mb, 16Mb respectively.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
FBGA DESCRIPTIONS
x32/x36 SYMBOL TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs registered must meet setup hold times around rising edge CLK. 10A, 10B, 10P, 10A, 10B, 10R, 11A, 10P, 10R,
BWa# BWb# BWc# BWd#
Input
Synchronous Byte Write Enables: These active inputs allow individual bytes written must meet setup hold times around rising edge CLK. byte write enable WRITE cycle HIGH READ cycle. version, BWa# controls DQas DQPa; BWb# controls DQbs DQPb. versions, BWa# controls DQas DQPa; BWb# controls DQbs DQPb; BWc# controls DQcs DQPc; BWd# controls DQds DQPd. Parity only available versions. Byte Write Enable: This active input permits BYTE WRITE operations must meet setup hold times around rising edge CLK. Global Write: This active input allows full 18-, 32-, 36-bit WRITE occur independent BWE# BWx# lines must meet setup hold times around rising edge CLK. Clock: This signal registers address, data, chip enable, byte write enables, burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Synchronous Chip Enable: This active input used enable device conditions internal ADSP#. sampled only when external address loaded. Synchronous Chip Enable: This active input used enable device sampled only when external address loaded. Snooze Enable: This active HIGH, asynchronous input causes device enter low-power standby mode which data memory array retained. When active, other inputs ignored. Synchronous Chip Enable: This active HIGH input used enable device sampled only when external address loaded. Output Enable: This active LOW, asynchronous input enables data output drivers. Synchronous Address Advance: This active input used advance internal burst counter, controlling burst access after external address loaded. HIGH ADV# effectively causes wait states generated address advance). ensure correct address during WRITE cycle, ADV# must HIGH rising edge first clock after ADSP# cycle initiated.
BWE#
Input
Input
Input
Input
CE2#
Input
Input
Input
OE#(G#) ADV#
Input Input
(continued next page)
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
FBGA DESCRIPTIONS (continued)
x32/x36 SYMBOL ADSP# TYPE Input DESCRIPTION Synchronous Address Status Processor: This active input interrupts ongoing burst, causing external address registered. READ performed using address, independent byte write enables ADSC#, dependent upon CE#, CE2#. ADSP# ignored HIGH. Powerdown state entered CE2# HIGH. Synchronous Address Status Controller: This active input interrupts ongoing burst, causing external address registered. READ WRITE performed using address LOW. ADSC# also used place chip into power-down state when HIGH. Mode: This input selects burst sequence. this input selects "linear burst." HIGH this input selects "interleaved burst." alter input state while device operating.
ADSC#
Input
MODE (LB0#)
Input
10J, 10K, 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11K, 11L, 10D, 10E, 10F, 10G, 11D, 11E, 11F,
Input/ SRAM Data I/Os: version, Byte associated DQas; Output Byte associated with DQbs. versions, Byte associated with DQas; Byte associated with DQbs; Byte associated with DQcs; Byte associated with DQds. Input data must meet setup hold times around rising edge CLK.
NC/DQPa NC/DQPb NC/DQPc NC/DQPd
Connect/Parity Data I/Os: version, these Connect (NC). version, Byte parity DQPa; Byte parity DQPb. version, Byte parity DQPa; Byte parity DQPb; Byte parity DQPc; Byte parity DQPd.
Supply Power Supply: Electrical Characteristics Operating Conditions range.
VDDQ
Supply Isolated Output Buffer Supply: Electrical Characteristics Operating Conditions range.
(continued next page)
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
FBGA DESCRIPTIONS (continued)
x32/x36 SYMBOL TYPE Supply Ground: GND. DESCRIPTION 10C, 10H, 10N, 11A, 11B, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N,
Use: These signals either unconnected wired improve package heat dissipation. Connect: These signals internally connected connected ground improve package heat dissipation. Pins 11P, reserved address expansion; 8Mb, 16Mb respectively.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X.X00 X.X01 X.X10 X.X11 X.X01 X.X00 X.X11 X.X10 X.X10 X.X11 X.X00 X.X01 X.X11 X.X10 X.X01 X.X00
LINEAR BURST ADDRESS TABLE (MODE LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X.X00 X.X01 X.X10 X.X11 X.X01 X.X10 X.X11 X.X00 X.X10 X.X11 X.X00 X.X01 X.X11 X.X00 X.X01 X.X10
PARTIAL TRUTH TABLE WRITE COMMANDS (x18)
FUNCTION READ READ WRITE Byte WRITE Byte WRITE Bytes WRITE Bytes BWE# BWa# BWb#
PARTIAL TRUTH TABLE WRITE COMMANDS (x32/x36)
FUNCTION READ READ WRITE Byte WRITE Bytes WRITE Bytes BWE# BWa# BWb# BWc# BWd#
NOTE: Using BWE# BWa# through BWd#, more bytes written.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TRUTH TABLE
ADDRESS USED CE2# DESELECTE Cycle, Power-Down None DESELECTE Cycle, Power-Down None DESELECTE Cycle, Power-Down None DESELECTE Cycle, Power-Down DESELECTE Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current OPERATION ADSP# ADSC# ADV# WRITE# High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
NOTE: means "Don't Care." means active LOW. means logic HIGH. means logic LOW. WRITE#, means more byte write enable signals (BWa#, BWb#, BWc# BWd#) BWE# LOW. WRITE# BWx#, BWE#, HIGH. BWa# enables WRITEs DQas DQPa. BWb# enables WRITEs DQbs DQPb. BWc# enables WRITEs DQcs DQPc. BWd# enables WRITEs DQds DQPd. DQPa DQPb only available versions. DQPc DQPd only available version. inputs except must meet setup hold times around rising edge (LOW HIGH) CLK. Wait states inserted suspending burst. WRITE operation following READ operation, must HIGH before input data setup time held HIGH throughout input data hold time. This device contains circuitry that will ensure outputs will High-Z during power-up. ADSP# always initiates internal READ edge CLK. WRITE performed setting more byte write enable signals BWE# subsequent edge CLK. Refer WRITE timing diagram clarification.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative -0.5V +4.6V Voltage VDDQ Supply Relative -0.5V +4.6V -0.5V VDDQ 0.5V Storage Temperature (plastic) -55°C +150°C Junction Temperature** +150°C Short Circuit Output Current 100mA *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature airflow. Micron Technical Note TN-05-14 more information.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS
(0°C +70°C; VDD, VDDQ +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS SYMBOL VDDQ -0.3 -1.0 -1.0 3.135 3.135 UNITS NOTES
Output(s) disabled, -4.0mA 8.0mA
NOTE: voltages referenced (GND). Overshoot: +4.6V tKC/2 20mA Undershoot: -0.7V tKC/2 20mA Power-up: +3.6V 3.135V 200ms MODE internal pull-up, input leakage ±10µA. load used VOH, testing shown Figure load current higher than stated values. curves available upon request. VDDQ should never exceed VDD. VDDQ connected together.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TQFP CAPACITANCE
DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS 25°C; MHz; 3.3V SYMBOL UNITS NOTES
FBGA CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Output Capacitance Clock Capacitance
NOTE: This parameter sampled. Preliminary package data.
CONDITIONS 25°C;
SYMBOL
UNITS
NOTES
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
OPERATING CONDITIONS MAXIMUM LIMITS
(0°C +70°C; VDD, VDDQ +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; inputs VIH; Cycle time (MIN); MAX; Outputs open Device selected; MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; inputs 0.2; Cycle time (MIN) Device deselected; MAX; inputs 0.2; inputs static; frequency Device deselected; MAX; inputs VIH; inputs static; frequency Device deselected; MAX; ADSC#, ADSP#, GW#, BWx#, ADV# VIH; inputs 0.2; Cycle time (MIN) -7.5 NOTES
IDD1
CMOS Standby
ISB2
Standby
ISB3
Clock Running
ISB4
NOTE: specified with output current increases with faster cycle times. IDDQ increases with faster cycle times greater output loading. "Device deselected" means device power-down mode defined truth table. "Device selected" means device active (not power-down mode). Typical values measured 3.3V, 25°C 10ns cycle time.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION Thermal Resistance (Junction Ambient) Thermal Resistance (Junction Case) CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51. SYMBOL UNITS NOTES °C/W °C/W
FBGA THERMAL RESISTANCE
DESCRIPTION Junction Ambient (Airflow 1m/s) Junction Case (Top) Junction Pins (Bottom)
NOTE: This parameter sampled. Preliminary package data.
CONDITIONS Test conditions follow standard test methods procedures measuring thermal impedance, EIA/JESD51.
SYMBOL
UNITS NOTES °C/W °C/W °C/W
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
(Note (0°C +70°C; VDD, VDDQ +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock time Output Times Clock output valid Clock output invalid Clock output Low-Z Clock output High-Z output valid output Low-Z output High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) NOTE: SYMBOL
tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tADSS tAAS tCES tADSH tAAH tCEH
-7.5
UNITS NOTES
Test conditions specified with output loading shown Figure unless otherwise noted. Measured HIGH above below VIL. This parameter measured with output loading shown Figure unless otherwise noted. This parameter sampled. Transition measured ±500mV from steady state voltage. Refer Technical Note TN-58-09, "Synchronous SRAM Contention Design Considerations," more thorough discussion these parameters. "Don't Care" when byte write enable sampled LOW. WRITE cycle defined least byte write enable ADSP# HIGH required setup hold times. READ cycle defined byte write enables HIGH ADSC# ADV# ADSP# required setup hold times. This synchronous device. addresses must meet specified setup hold times rising edges when either ADSP# ADSC# chip enabled. other synchronous inputs must meet setup hold times with stable logic levels rising edges clock (CLK) when chip enabled. Chip enable must valid each rising edge when either ADSP# ADSC# remain enabled.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
TEST CONDITIONS
Input pulse levels (VDD/2.2) 1.5V (VDD/2.2) 1.5V Input rise fall times Input timing reference levels VDD/2.2 Output reference levels VDDQ/2.2 Output load Figures
Output Load Equivalents
1.5V
Figure
+3.3V
LOAD DERATING CURVES
Micron 256K 128K 128K SyncBurst SRAM timing dependent upon capacitive loading outputs. Consult factory copies current versus voltage curves.
Figure
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
SNOOZE MODE
SNOOZE MODE low-current, "power-down" mode which device deselected current reduced ISB2Z. duration SNOOZE MODE dictated length time HIGH state. After device enters SNOOZE MODE, inputs except become gated inputs ignored. asynchronous, active HIGH input that causes device enter SNOOZE MODE. When becomes logic HIGH, ISB2Z guaranteed after setup time met. READ WRITE operation pending when device enters SNOOZE MODE guaranteed complete successfully. Therefore, SNOOZE MODE must initiated until valid pending operations completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION Current during SNOOZE MODE active input ignored inactive input sampled active snooze current inactive exit snooze current
NOTE: This parameter sampled.
CONDITIONS
SYMBOL ISB2Z
tRZZ tZZI tRZZI
2(tKC)
UNITS
NOTES
2(tKC) 2(tKC)
SNOOZE MODE WAVEFORM
SUPPLY ISB2Z RZZI DESELECT READ Only
INPUTS (except
Outputs
High-Z
DON'T CARE
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
READ TIMING3
tADSS tADSH
ADSP#
tADSS tADSH
ADSC#
ADDRESS
Burst continued with base address.
GW#, BWE#, BWa#-BWd#
tCES tCEH
Deselect (NOTE cycle.
(NOTE ADV#
tAAS
tAAH
ADV# suspends burst. (NOTE
KQLZ OEHZ tOEQ OELZ tKQX KQHZ
High-Z
Q(A1)
Q(A2) (NOTE
Q(A2
Q(A2
Q(A2
Q(A2)
Q(A2
Q(A3)
Single READ
BURST READ
Burst wraps around initial state.
DON'T CARE
UNDEFINED
READ TIMING PARAMETERS
SYMBOL
tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ
-7.5
UNITS SYMBOL
tADSS tAAS tCES tADSH tAAH tCEH
-7.5
UNITS
NOTE: Q(A2) refers output from address Q(A2 refers output from next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. Timing shown assuming that device enabled before entering into this sequence. does cause driven until after following clock rising edge. Outputs disabled within clock cycles after deselect.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
WRITE TIMING
tADSS tADSH
ADSP#
tADSS tADSH
ADSC# extends burst.
tADSS tADSH
ADSC#
ADDRESS
Byte write signals ignored first cycle when ADSP# initiates burst.
BWE#, BWa#-BWd# (NOTE
tCES tCEH
(NOTE ADV# (NOTE (NOTE
tAAS tAAH
ADV# suspends burst.
High-Z
tOEHZ
D(A1)
D(A2)
D(A2 (NOTE
D(A2
D(A2
D(A2
D(A3)
D(A3
D(A3
BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON'T CARE UNDEFINED
WRITE TIMING PARAMETERS
SYMBOL
tOEHZ tADSS tAAS
-7.5
UNITS SYMBOL
tCES tADSH tAAH tCEH
-7.5
UNITS
NOTE: D(A2) refers input address D(A2 refers input next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. must HIGH before input data setup held HIGH throughout data hold time. This prevents input/ output data contention time period prior byte write enable inputs being sampled. ADV# must HIGH permit WRITE loaded address. Full-width WRITE initiated LOW; HIGH, BWE# BWa#-BWb# device; HIGH, BWE# BWa#-BWd# devices.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
READ/WRITE TIMING6
tADSS tADSH
ADSP#
ADSC#
ADDRESS BWE#, BWa#-BWd# (NOTE (NOTE ADV#
tCES
tCEH
tOELZ
High-Z
tKQLZ
tOEHZ
D(A3) (NOTE Q(A4) Single WRITE Q(A4+1) BURST READ Q(A4+2) Q(A4+3)
D(A5)
D(A6)
High-Z
Q(A1) Back-to-Back READs (NOTE
Q(A2)
Back-to-Back WRITEs DON'T CARE UNDEFINED
WRITE TIMING PARAMETERS
SYMBOL
tKQLZ tOELZ tOEHZ
-7.5
UNITS SYMBOL
tADSS tCES tADSH tCEH
-7.5
UNITS
NOTE: Q(A4) refers output from address Q(A4 refers output from next internal burst address following CE2# have timing identical CE#. this diagram, when LOW, CE2# HIGH. When HIGH, CE2# HIGH LOW. data remains High-Z following WRITE cycle unless ADSP#, ADSC# ADV# cycle performed. HIGH. Back-to-back READs controlled either ADSP# ADSC#. Timing shown assuming that device enabled before entering into this sequence.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
0.15
+0.03 -0.02
0.32
+0.06 -0.10
22.10
+0.10 -0.15
0.65
20.10 ±0.10 DETAIL
0.62 14.00 ±0.10 +0.20 -0.05 GAGE PLANE
1.50 ±0.10 0.10
16.00
0.25
0.10
+0.10 -0.05
1.00 (TYP) 0.60 ±0.15 DETAIL
1.40 ±0.05
NOTE: dimensions millimeters typical where noted. Package width length include mold protrusion; allowable mold protrusion 0.25mm side.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
165-PIN FBGA
0.85 ±0.075 0.12
SEATING PLANE
BALL 165X 0.45 SOLDER BALL DIAMETER REFERS POST REFLOW CONDITION. PRE-REFLOW DIAMETER 0.40 10.00 1.00 BALL 1.20
7.50 ±0.05
15.00 ±0.10
14.00
7.00 ±0.05 1.00
6.50 ±0.05 5.00 ±0.05 13.00 ±0.10
MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC SOLDER BALL PAD: .33mm
NOTE: dimensions millimeters typical where noted.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron registered trademark SyncBurst trademark Micron Technology, Inc. Pentium registered trademark Intel Corporation.
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
4Mb: 256K 128K 32/36 3.3V PIPELINED, SYNCBURST SRAM
REVISION HISTORY
Removed "Preliminary Package Data" from front page February 22/02 Removed 119-pin PBGA package references February 14/02 Removed note "Not Recommended Designs," Rev. 6/01 June 7/01 Added Industrial Temperature note reference, Rev. 3/01, FINAL March 6/01 Added 119-pin PBGA package, Rev. 1/01, FINAL January 10/01 Removed FBGA Part Marking Guide, 8/00-A, FINAL August 22/00 Changed FBGA capacitance values, 8/00, FINAL August 7/00 2.5pF from 4pF; MAX. 3.5pF from from 6pF; MAX. from CCK; 2.5pF from 5pF; MAX. 3.5pF from Added FBGA Part Marking Guide, Rev. 7/00, Preliminary July 18/00 Added revision history Added FBGA Part Marking References Removed 119-Pin PBGA package references Removed industrial temperature references Added 165-pin FBGA package, Rev. 6/00, Preliminary 23/00
4Mb: 256K 128K 32/36 3.3V Pipelined, SyncBurst SRAM MT58L256L18D1_E.p65 Rev. 2/02
Micron Technology, Inc., reserves right change products specifications without notice. ©2002, Micron Technology, Inc.
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