SMALL-OUTLINE SDRAM MODULE JEDEC-standard, PC100/PC133, 144-pin,
|
|
|
Top Searches for this datasheet
64MB 128MB 256MB (x64) SDRAM SODIMM
SMALL-OUTLINE SDRAM MODULE
JEDEC-standard, PC100/PC133, 144-pin, smalloutline, dual in-line memory module (SODIMM) Unbuffered 64MB 64), 128MB 256MB Single +3.3V ±0.3V power supply Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths: full page Auto Precharge Auto Refresh Modes Self Refresh Mode: Standard Power 64MB 128MB: 64ms, 4,096-cycle refresh; 256MB: 64ms, 8,192-cycle refresh LVTTL-compatible inputs outputs Serial Presence-Detect (SPD)
MT8LSDT864(L)H 64MB MT8LSDT1664(L)H 128MB MT8LSDT3264(L)H 256MB
latest data sheet, please refer Micron site: www.micron.com/datasheets
144-Pin Small-Outline DIMM MO-190
TIMING PARAMETERS
MODULE MARKING -13E -133 -10E PC133 tRCD tRP) 2-2-2 3-3-3 PC100 tRCD tRP) 2-2-2 2-2-2 2-2-2
OPTIONS
Self Refresh Current Standard Power Package 144-pin SODIMM (gold) Frequency/CAS Latency MHz/CL MHz/CL MHz/CL Profile
MARKING
None
PART NUMBERS
PART NUMBER CONFIGURATION SYSTEM SPEED MT8LSDT864HG-13E_ MT8LSDT864HG-133_ MT8LSDT864HG-10E_ MT8LSDT864LHG-13E_ MT8LSDT864LHG-133_ MT8LSDT864LHG-10E_ MT8LSDT1664HG-13E_ MT8LSDT1664HG-133_ 16Meg MT8LSDT1664HG-10E_ MT8LSDT1664LHG-13E_ MT8LSDT1664LHG-133_ MT8LSDT1664LHG-10E_ MT8LSDT3264HG-13E_ MT8LSDT3264HG-133_ 32Meg MT8LSDT3264HG-10E_ MT8LSDT3264LHG-13E_ MT8LSDT3264LHG-133_ MT8LSDT3264LHG-10E_ NOTE: designators component revision last characters each part number. Consult factory current revision codes. Example: MT8LSDT1664HG-133B1.
-13E -133 -10E Standard
ADDRESS TABLE
64MB Module Refresh Count Device Banks (BA0, BA1) Device Configuration Addressing (A0-A11) Column Addressing (A0-A7) Module Banks (S0, 128MB Module (BA0, BA1) (A0-A11) (A0-A8) (S0, 256MB Module (BA0, BA1) (A0-A12) (A0-A8) (S0,
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
PRELIMINARY
64MB 128MB 256MB (x64) 144-PIN SDRAM SODIMM
ASSIGNMENT (144-PIN SODIMM Front)
SYMBOL SYMBOL DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB0 DQMB1 RAS# SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 SYMBOL DQMB2 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
ASSIGNMENT (144-Pin SODIMM Back)
SYMBOL SYMBOL DQ40 DQ32 DQ41 DQ33 DQ42 DQ34 DQ43 DQ35 DQ44 DQ36 DQ45 DQ37 DQ46 DQ38 DQ47 DQ39 DQMB4 DQMB5 CKE0 CAS# CKE1 NC/A12* SYMBOL DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 SYMBOL DQMB6 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
*Pin Connect 64MB 128MB moduled, 256MB module.
Front View
(all pins)
Back View
(all even pins)
SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
©2001, Micron Technology, Inc.
PRODUCTS SPECIFICATIONS DISCUSSED HEREIN EVALUATION REFERENCE PURPOSES ONLY SUBJECT CHANGE MICRON WITHOUT NOTICE. PRODUCTS ONLY WARRANTED MICRON MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
64MB 128MB 256MB (x64) SDRAM SODIMM
DESCRIPTIONS
NUMBERS SYMBOL RAS#, CAS#, CK0, TYPE Input Input DESCRIPTION Command Inputs RAS#, CAS#, (along with S1#) define command being entered. Clock: driven system clock. SDRAM input signals sampled positive edge also increments internal burst counter controls output registers. Clock Enable: CKE0 CKE1 activate (HIGH) deactivate (LOW) CK0-CK1 signals. Deactivating clock provides POWER-DOWN SELF REFRESH operation (all device banks idle) CLOCK SUSPEND operation (burst access progress). CKE0 CKE1 synchronous except after device enters power-down self refresh modes, where CKE0 CKE1 become asynchronous until after exiting same mode. input buffers, including CK0-CK1, disabled during power-down self refresh modes, providing standby power. Chip Select: enable (registered LOW) disable (registered HIGH) command decoder. commands masked when registered HIGH. considered part command code. Input Mask: DQMB input mask signal write accesses. Input data masked when DQMB sampled HIGH during WRITE cycle. output buffers placed High-Z state (after two-clock latency) when DQMB sampled HIGH during READ cycle. Bank Address: define which internal device bank ACTIVE, READ, WRITE, PRECHARGE command being applied. also used program twelfth Mode Register. Address Inputs: A0-A11(64/128MB), A0-A12(256MB) sampled during ACTIVE command (row-address A0-A11/A12) READ/ WRITE command (column-address A0-A7 64MB, A0-A8 128/256MB); with defining auto precharge) select location memory array respective device bank. sampled during PRECHARGE command determine device banks precharged (A10 HIGH) device bank selected (LOW). address inputs also provide op-code during LOAD MODE REGISTER command. Serial Clock Presence-Detect: used synchronize presence-detect data transfer from module.
CKE0, CKE1
Input
S0#,
Input
115, 116,
DQMB0- DQMB7
Input
106,
BA0,
Input
103, A0-A11 105, 109, 111, 64/128MB 70(256MB), A0-A12 104, 256MB
Input
Input
NOTE: numbers correlate with symbols. Refer Assignment Tables number symbol information.
(continued next page)
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
DESCRIPTIONS (continued)
NUMBERS SYMBOL TYPE Input/ Output Data I/Os: Data bus. DESCRIPTION DQ0-DQ63 51,53, 115, 117, 121, 123, 125, 127, 131, 133, 135, 137, 96,98, 100, 122, 124, 126, 128, 132, 134, 136,
Input/ Output Supply
Serial Presence-Detect Data: bidirectional used transfer addresses data into data presencedetect portion module. Power Supply: +3.3V ±0.3V.
101, 113, 129, 114, 130, 107, 119, 139, 108, 120, 70(64/128MB)
Supply
Ground.
Use: These pins connected these modules, assigned pins other modules this product family. Connect: These pins should left unconnected.
NOTE: numbers correlate with symbols. Refer Assignment Tables number symbol information.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
FUNCTIONAL BLOCK DIAGRAM MODULES
DQMB0 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQML DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQMB1 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 RAS# CAS# CKE0 CKE1 A0-A11 (64MB/128MB) A0-A12 (256MB) BA0-1 DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML DQML DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML DQML DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQML DQML DQMH DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
RAS#: SDRAMs U2-U9 CAS#: SDRAMs U2-U9 CKE: SDRAMs U2-U5 CKE: SDRAMs U6-U9 WE#: SDRAMs U2-U9 A0-A11: SDRAMs U2-U9 A0-A12: SDRAMs U2-U9 BA0-1: SDRAMs U2-U9 SDRAMs U2-U9, SDRAMs U2-U9, U2-U9 MT48LC4M16A2TG SDRAMs 64MB module U2-U9 MT48LC8M16A2TG SDRAMs 128MB module U2-U9 MT48LC16M16A2TG SDRAMs 256MB module SERIAL U2-U5 U6-U9 U2-U5 U6-U9
NOTE:
resistor values ohms unless otherwise specified.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
GENERAL DESCRIPTION
Micron® MT8LSDT864(L)H, MT8LSDT1664(L)H, MT8LSDT3264(L)H high-speed CMOS, dynamic random-access, 64MB, 128MB, 265MB memory modules organized configuration. These module SDRAM devices which internally configured quad-bank DRAMs with synchronous interface (all signals registered positive edge clock signals CK0-CK1). four banks configured devices used these modules configured 4,096 bit-rows bit-columns, input/output bits 64MB module; 4,096 bit-rows bit-columns input/output bits 128MB module; 8,192 bit-rows bit-columns input/output bits 256MB module. Read write accesses SDRAM module burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select device bank accessed (BA0, select device bank, A0-A11 64MB/128MB; A0-A12 256MB select device row). address bits registered coincident with READ WRITE command(A0-A7 64MB; A0-A8 128/256MB) used select starting device column location burst access. These modules provide programmable READ WRITE burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. These modules uses internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve highspeed, fully random access. Precharging device bank while accessing other three device banks will hide PRECHARGE cycles provide seamless, high-speed, random access operation. These modules designed operate 3.3V, lowpower memory systems. auto refresh mode provided, along with power-saving, power-down mode. inputs, outputs, clocks LVTTL-compatible. SDRAM modules offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks order hide precharge time, capability randomly change column addresses each clock cycle during burst access. more information regarding SDRAM operation, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
SERIAL PRESENCE-DETECT OPERATION
These modules incorporate serial presence-detect (SPD). function implemented using 2,048bit EEPROM. This nonvolatile storage device contains bytes. first bytes programmed Micron identify module type various SDRAM organizations timing parameters. remaining bytes storage available customer. System READ/WRITE operations between master (system logic) slave EEPROM device (DIMM) occur standard using DIMM's (clock) (data) signals.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. Once power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands should applied. Once 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. device banks must then precharged, thereby placing device banks idle state. Once idle state, AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, should loaded prior applying operational command. mode register. mode register must loaded when device banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Burst Length Read write accesses SDRAM burst oriented, with burst length being programmable, shown Mode Register Definition Diagram. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached, shown Burst Definition Table. block uniquely selected A1-A9 when burst length two; A2-A9 when burst length four; A3-A9 when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached, shown Burst
Register Definition
MODE REGISTER mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, latency, operating mode write burst mode, shown Mode Register Definition Diagram. mode register programmed LOAD MODE REGISTER command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), M4-M6 specify latency, specify operating mode, specifies write burst mode, reserved future use. 256MB module, Address (M12) undefined should driven during loading
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown Burst Definition Table.
64MB Module 128MB Module
Address
Burst Definition Table
Burst Length Starting Column Order Accesses Within Burst Address Type Sequential Type Interleaved A0-Ai* (location 0-y) 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported
Mode Register (Mx) Reserved* Mode *Should program ensure compatibility with future devices. Latency Burst Length
256MB Module
Address
Mode Register (Mx)
Reserved*
Mode
Latency
Burst Length
*Should program M12, M11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Full Page
64MB module; 128MB 256MB modules NOTE: full-page accesses: (64MB); (128MB/256MB). burst length two, A1-Ai select blockof-two burst; selects starting column within block. burst length four, A2-Ai select blockof-four burst; A0-A1 select starting column within block. burst length eight, A3-Ai select blockof-eight burst; A0-A2 select starting column within block. full-page burst, full selected A0-Ai select starting column. Whenever boundary block reached within given sequence above, following access wraps within block. burst length one, A0-Ai select unique column accessed, mode register ignored.
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
M6-M0 Defined
Operating Mode Standard Operation other states reserved
Write Burst Mode Programmed Burst Length Single Location Access
Mode Register Definition Diagram
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
Definition Table. Latency latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Latency Diagram. Latency Table indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result. Operating Mode normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result. Write Burst Mode When burst length programmed M0M2 applies both READ WRITE bursts; when programmed burst length applies READ bursts, write accesses single-location (nonburst) accesses.
Latency Table
ALLOWABLE OPERATING FREQUENCY (MHz) SPEED LATENCY LATENCY
Latency Diagram
COMMAND
-13E -133 -10E
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
COMMANDS
following Truth Table provides general reference available commands. more detailed description commands operations, refer 64Mb, 128Mb, 256Mb SDRAM component data sheets.
TRUTH TABLE SDRAM COMMANDS DQMB OPERATION
Note: notes appear below table NAME (FUNCTION) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z RAS# CAS# DQMB ADDR L/H8 L/H8 Bank/Row Bank/Col Bank/Col Code Op-Code NOTES Valid Active Active High-Z
NOTE: HIGH commands shown except SELF REFRESH. A0-A11 define op-code written mode register, 256MB module, should driven LOW. A0-A11 (64MB/128MB) A0-A12 (256MB) provide device address, BA0, determine which device bank made active. A0-A7 (64MB) A0-A8 (128MB/256MB) provide device column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which device bank being read from written LOW: BA0, determine device bank being precharged. HIGH: device banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls device addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
ABSOLUTE MAXIMUM RATINGS*
Voltage VDD, VDDQ Supply Relative +4.6V Voltage Inputs, Pins Relative +4.6V Operating Temperature, (commercial) +70°C Storage Temperature (plastic) -55°C +150°C Power Dissipation *Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS OPERATING CONDITIONS (ALL MODULES)
Notes: notes appear following parameter tables; (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs INPUT LEAKAGE CURRENT: input (All other pins under test OUTPUT LEAKAGE CURRENT: disabled; VOUT VDDQ OUTPUT LEVELS: Output High Voltage (IOUT -4mA) Output Voltage (IOUT 4mA) SYMBOL VDD, VDDQ -0.3 UNITS NOTES
SPECIFICATIONS CONDITIONS* (64MB MODULE)
Notes: notes appear following parameter tables; (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL -13E -133 -10E UNITS NOTES IDD1a IDD2b IDD3a
IDD4a IDD5b IDD6b IDD7b IDD7b
tRFC (MIN) 15.625
1,840 1,680 1,520
Standard power
*DRAM components only. Value calculated module bank this operating condition, other module banks power-down mode. Value calculated reflect module banks this operating condition.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
SPECIFICATIONS CONDITIONS* (128MB MODULE)
Notes: notes appear following parameter tables; (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL -13E -133 -10E UNITS NOTES IDD1a IDD2b IDD3a
IDD4a IDD5b IDD6b IDD7b IDD7b
tRFC (MIN) 12.625
2,640 2,480 2,160
Standard power
*DRAM components only. Value calculated module bank this operating condition, other module banks power-down mode. Value calculated reflect module banks this operating condition.
SPECIFICATIONS CONDITIONS* (256MB MODULE)
Notes: notes appear following parameter tables; (VDD, VDDQ +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst READ WRITE; (MIN) STANDBY CURRENT: Power-Down Mode; banks idle; STANDBY CURRENT: Active Mode; HIGH; HIGH; banks active after tRCD met; accesses progress OPERATING CURRENT: Burst Mode; Continuous burst; READ WRITE; banks active AUTO REFRESH CURRENT HIGH; HIGH SELF REFRESH CURRENT: 0.2V
tRFC tRFC
SYMBOL -13E -133 -10E UNITS NOTES IDD1a IDD2b IDD3a
IDD4a IDD5b
DD6b
tRFC (MIN) 7.81
2,280 2,160 2,160
Standard power
IDD7b IDD7b
*DRAM components only. Value calculated module bank this operating condition, other module banks power-down mode. Value calculated reflect module banks this operating condition.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
CAPACITANCE
Note: notes appear following parameter tables PARAMETER Input Capacitance: Input Capacitance: other input-only pins Input/Output Capacitance: SYMBOL 30.4 UNITS
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
Notes: notes appear following parameter tables; (VDD, VDDQ +3.3V ±0.3V)
CHARACTERISTICS PARAMETER Access time from (pos. edge) Address hold time Address setup time high-level width low-level width Clock cycle time -13E -133 -10E 120,000 120,000 120,000 7.5ns
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out high-impedance time Data-out low-impedance time Data-out hold time (load) Data-out hold time load) ACTIVE PRECHARGE command ACTIVE ACTIVE command period ACTIVE READ WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
SYMBOL tAC(3) tAC(2) tCK(3) tCK(2) tCKH tCKS tCMH tCMS tHZ(3) tHZ(2) tRAS tRCD tREF tRFC tRRD
UNITS
NOTES
Exit SELF REFRESH ACTIVE command
tXSR
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
FUNCTIONAL CHARACTERISTICS
Notes: notes appear following parameter tables (0°C +70°C)
PARAMETER READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH(3) tROH(2) -13E -133 -10E UNITS NOTES
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
NOTES:
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz, 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range ensured (0°C +70°C commercial). initial pause 100µs required after powerup, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load: Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 10ns -10E; 7.5ns -133 -13E. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -13E; 7.5ns -133; -10E after first clock delay, after last WRITE executed. exceed limit precharge mode. Precharge mode only. JEDEC PC100 specify three clocks. -133/-13E with load 4.6ns guaranteed design. Parameter guaranteed design. -13E, 7.5ns; -133, 7.5ns; -10E, CL=2 10ns HIGH during refresh command period tRFC (MIN) else LOW. IDD6 limit actually nominal value does result fail value. Refer device data sheet timing waveforms. Device supports 37ns. BIOS issues, Byte (-13E) 45ns. Leakage number reflects worst case leakage possible through module pin, what each memory device contributes.
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than then timing referenced (MAX) (MIN) longer crossover point. Refer Micron Technical Note, TN-48-09, additional information SDRAM timing Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
CLOCK DATA CONVENTIONS Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions indicated Figures START CONDITION commands preceded start condition, which HIGH-to-LOW transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. STOP CONDITION communications terminated stop condition, which LOW-to-HIGH transition when HIGH. stop condition also used place device into standby power mode. ACKNOWLEDGE Acknowledge software convention used indicate successful data transfers. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data indicated Figure device will always respond with acknowledge after recognition start condition slave address. both device WRITE operation have been selected, device will respond with acknowledge after receipt each subsequent eight-bit word. read mode device will transmit eight bits data, release line monitor line acknowledge. acknowledge detected stop condition generated master, slave will continue transmit data. acknowledge detected, slave will terminate further data transmissions await stop condition return standby power mode.
Figure Data Validity
Figure Definition Start Stop
DATA STABLE DATA CHANGE DATA STABLE
START
STOP
Figure Acknowledge Response From Receiver
from Master
Data Output from Transmitter
Data Output from Receiver Acknowledge
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
EEPROM DEVICE SELECT CODE
most significant (b7) sent first DEVICE TYPE IDENTIFIER Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE
EEPROM OPERATING MODES
MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write
NOTE: VIL.
BYTES
INITIAL SEQUENCE START, Device Select, START, Device Select, `0', Address reSTART, Device Select, Similar Current Random Address Read START, Device Select, START, Device Select,
EEPROM TIMING DIAGRAM
HIGH
SU:STA HD:STA HD:DAT SU:DAT SU:STO
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS
SYMBOL
tBUF tHD:DAT tHD:STA
UNITS
SYMBOL tHIGH
tLOW tSU:DAT tSU:STA tSU:STO
UNITS
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
Note: (VDD +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic inputs INPUT VOLTAGE: Logic inputs OUTPUT VOLTAGE: IOUT INPUT LEAKAGE CURRENT: OUTPUT LEAKAGE CURRENT: VOUT STANDBY CURRENT: 0.3V; other inputs 3.3V +10% POWER SUPPLY CURRENT: clock frequency SYMBOL UNITS
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
Note: (VDD +3.3V ±0.3V)
PARAMETER/CONDITION data-out valid Time must free before transition start Data-out hold time fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant SCL, inputs Clock period rise time clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time NOTE: voltages referenced VSS. voltages referenced VSS. Timing actually specified tWR. SYMBOL tBUF tHD:DAT tHD:STA tHIGH tLOW tSCL tSU:DAT tSU:STA tSU:STO tWRC UNITS NOTES
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT MATRIX
(Note:
BYTE DESCRIPTION NUMBER BYTES USED MICRON TOTAL NUMBER MEMORY BYTES MEMORY TYPE NUMBER ADDRESSES NUMBER COLUMN ADDRESSES NUMBER BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLOCK, (CAS LATENCY MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MIN. CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES, tCCD BURST LENGTHS SUPPORTED NUMBER BANKS SDRAM DEVICE LATENCIES SUPPORTED LATENCY LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY SDRAM CYCLE TIME, (CAS LATENCY SDRAM ACCESS FROM CLK, (CAS LATENCY MINIMUM PRECHARGE TIME, MINIMUM ACTIVE ACTIVE,
tRRD
ENTRY (VERSION) MT8LSDT864(L)H SDRAM LVTTL (-13E) (-133) (-10E) (-13E/-133) (-10E) None 15.6/7.81µs/SELF PAGE Unbuffered (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133/-10E) (-13E) (-133) (-10E) (-13E) (-133/-10E)
MT8LSDT1664(L)H MT8LSDT3264(L)H
MINIMUM RAS# CAS# DELAY, tRCD
NOTE: "1"/"0": Serial Data, "driven HIGH"/"driven LOW."
(continued next page)
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
SERIAL PRESENCE-DETECT MATRIX (continued)
(Note:
BYTE ENTRY (VERSION) MT8LSDT864(L)H MT8LSDT1664(L)H MT8LSDT3264(L)H (-13E) (-133) (-10E) MODULE BANK DENSITY 32MB/64MB/128MB COMMAND ADDRESS SETUP TIME, (-13E/-133) tAS, tCMS (-10E) COMMAND ADDRESS HOLD TIME, (-13E/133) tAH, tCMH (-10E) (-13E/-133) DATA SIGNAL INPUT SETUP TIME, (-10E) (-13E/-133) DATA SIGNAL INPUT HOLD TIME, (-10E) RESERVED REVISION REV. CHECKSUM BYTES 0-62 -13E -133 -10E MANUFACTURER'S JEDEC CODE MICRON MANUFACTURER'S JEDEC CODE (CONT.) MANUFACTURING LOCATION MODULE PART NUMBER (ASCII) IDENTIFICATION CODE IDENTIFICATION CODE (CONT.) YEAR MANUFACTURE WEEK MANUFACTURE MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY 100/133 SDRAM COMPONENT CLOCK DETAIL DESCRIPTION MINIMUM RAS# PULSE WIDTH, tRAS (Note:
36-61
65-71
73-90
95-98 99-125
NOTE: "1"/"0": Serial Data, "driven HIGH"/"driven LOW." Variable Data. value tRAS used -13E module calculated from tRP. Actual device spec. value 37ns.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01
Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
64MB 128MB 256MB (x64) SDRAM SODIMM
144-PIN SODIMM
FRONT VIEW
2.666 (67.72) 2.656 (67.45) .150 (3.80)
.079 (2.00) (2X)
.071 (1.80) (2X)
1.255 (31.88) 1.245 (31.62) .787 (20.00)
.236 (6.00) .100 (2.55) .157 (4.00)
.079 (2.00) (3.30)
.059 (1.50) .024 (.60) 2.386 (60.60) 2.504 (63.60)
.0315 (.80)
BACK VIEW
NOTE: dimensions inches (millimeters) typical where noted.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron registered trademark Micron logo logo trademarks Micron Technology, Inc.
8,16, SDRAM SODIMM SD8C8_16_32X64HG_A.p65 Rev. Pub. 12/01 Micron Technology, Inc., reserves right change products specifications without notice. ©2001, Micron Technology, Inc.
Other recent searches
XTR108 - XTR108 XTR108 Datasheet
SN74ALVCH16903 - SN74ALVCH16903 SN74ALVCH16903 Datasheet
RN262CS - RN262CS RN262CS Datasheet
PDB-V114 - PDB-V114 PDB-V114 Datasheet
FTLF8519P2xCL - FTLF8519P2xCL FTLF8519P2xCL Datasheet
DK86060-3 - DK86060-3 DK86060-3 Datasheet
BLV91 - BLV91 BLV91 Datasheet
AT10GC - AT10GC AT10GC Datasheet
2SK3572 - 2SK3572 2SK3572 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
