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KS86C6308/P6308
SAM88RCRI PRODUCT FAMILY
Samsung's SAM88RCRI family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. dual address/data architecture large number bit- nibble-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations. Many SAM88RCRI microcontrollers have external interface that provides access external memory other peripheral devices.
KS86C6308/P6308 MICROCONTROLLER
KS86C6308/P6308 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM88RCRI core. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C6308 bytes program memory on-chip. Using SAM88RCRI design approach, following peripherals were integrated with SAM88RCRI core: Five configurable ports pins) bit-programmable pins external interrupts 8-bit timer/counter 16-bit timwe/counter with three operating modes Full speed speed function KS86C6308/P6308 versatile microcontroller that used wide range full/low speed support general purpose applications. especially suitable keyboard with controller available 64-pin SDIP 64-pin package.
KS86C6308 microcontroller also available (One Time Programmable) version, KS86P6308. KS86P6308 microcontroller on-chip 8-Kbyte one-time-programmable EPROM instead masked ROM. KS86P6308 comparable KS86C6308, both function configuration.
KS86C6308/P6308 (Preliminary Spec)
FEATURES
SAM88RCRI core Timer 8-bit basic timer watchdog function programmable oscillation stabilization programmable 8-bit timer internal generation function interval, capture, mode match/capture overflow interrupt
Memory 8-KB Internal program memory(ROM) 256-byte internal register file (160-byte:General Purpose) Instruction instructions IDLE STOP instructions added powerdown modes
Timer Programmable 16-bit timer interval generation function interval, capture, mode match/capture overflow interrupt
Universal Serial with upstream port downstream port embedded function each port supports separated enable builtin voltage regulator
Instruction Execution Time 332ns fOSC
Interrupts interrupt sources with vector, each source pending bits level, vector interrupt structure
USB/GPIO Function Upstream port
Operation Temperature Range
Oscillation Frequency crystal/ceramic oscillator External clock source
Operation Voltage Range
General programmable five ports pins total)
Package Types 64-pin SDIP 64-pin
KS86C6308/P6308 (Preliminary Spec)
BLOCK DIAGRAM
Transceiver Voltage Regulator Module
DP0/GPIO, DM0/GPIO DP1, DP2, DP3, DP4, VOUT
PWREN1 PWREN2 PWREN3 PWREN4 OCDET1 OCDET2 OCDET3 OCDET4
SAM88RCRI CORE
Device Control
VSS1 TEST
RESET
LEDON0 LEDON1 LEDON2 LEDON3 LEDON4 GANGED
Port P0.0/INT2 P0.7/INT2
Byte
Port
P1.0 P1.7
TMOD
Timer Bit)
Port Timer Bit) Port Basic Timer
P2.0/INT0 P2.7/INT0 P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.1/TACAP/TBOUT P4.0/INT1 P4.1/INT
Port
Figure 1-1. Block Diagram
KS86C6308/P6308 (Preliminary Spec)
ASSIGNMENTS
LEDON4 P1.4 P1.5 P1.6 P1.7 P4.0/INT1 P4.1/INT1 P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
TMODE DP0/GPIO DM0/GPIO
LEDON3 LEDPN2 LEDON1 LEDON0
OCDET4 PWREN4
P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN
Figure 1-2. Assignment Diagram (64-Pin SDIP Package)
KS86C6308/P6308
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT VSS1/VSS
OCDET2 PWREN2 ECDET1 PWREN
3.3VOUT
KS86C6308/P6308 (Preliminary Spec)
P41/INT1 P40/INT1 LEDON4 LEDON3 LEDON2 LEDON1 LEDON0
P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 SDAT /P2.6/INT0 SCLK /P2.7/INT0 VDD/VDD VSS/VSS XI/XI TEST /TEST VSS/VSSA
RESET/RESET
OCDET4 PWREN4
TMODE DP0/GPIO DM0/GPIO
KS86C6308 (KS86P6308)
P1.3 P1.2 P1.1 P1.0 P0.7/INT2 P0.6/INT2 P0.5/INT2 P0.4/INT2 P0.3/INT2 P0.2/INT2 P0.1/INT2 P0.0/INT2
OCDET3 PWREN3
P3.3/TACLK/CLO P3.2/TBCLK/USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT GANGED
3.3VOUT
Figure 1-3. Assignment Diagram (64-Pin Package)
PWREN1 OCDET1 PWREN2 OCDET2
KS86C6308/P6308 (Preliminary Spec)
DESCRIPTIONS
Table 1-1. KS86C6308/P6308 Descriptions Names P0.0-P0.7 Description Bit-programmable port Schmitt trigger input open-drain output. Port individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Port also individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input, opendrain output push-pull output. Port designed drive directly. P3.3 used system clock output(CLO) pin. P3.2 clock Block. Bit-programmable port Schmitt trigger input open-drain output push-pull output. Port4 also individually configured external interrupt inputs. output mode, pull-up resistors assignable software. input mode, pull-up resistors fixed. output from internal voltage regulator System clock input output (crystal/ceramic oscillator, external clock source) External interrupt bit-programmable port0, port2 port4 pins when input mode. RESET signal input with Pass Filter Test signal input (for factory only; must connected VSS) Test signal input (for factory only, must connected VSS) Power input VSS1 ground power core. VSS2 ground power block. Type Share Pins INT2
P1.0-P1.7
P2.0-P2.7
INT0
P3.0-P3.3
P3.3/TACLK/CLO P3.2/TBCLK/ USB_CLK P3.1/TBCAP/TAOUT P3.0/TACAP/TBOUT
P4.0-P4.
VOUT XOUT INT0 INT1 INT2 RESET TEST TMODE
P2.0-P2.7 P4.0/P4.1 P0.0/P0.7
KS86C6308/P6308 (Preliminary Spec)
Table 1-1. KS86C6308/P6308 Descriptions (Continued) Names DP1, DP2, DP3, DP4, DP0/GPIO DM0/GPIO LEDON0 Description These pins Downstream pins. Type Share Pins
LEDON1-4
OCDET1-4
PWREN1-4
GANGED
These pins Upstream pin, programmable port interface General purpose interface. Root port enable. N-channel open-drain output. Turn Suspend Turn OFF. Reset, Suspend, Transfer progress Four downstream port enable. N-channel opendrain output. Turn Port Enable Suspend Turn OFF. Reset, Suspend, Transfer progress Four downstream power sense Over Current Detected Power Okay Power on/off control signals. PWREN1 PWREN4 active low, N-CH open-drain outputs. GANGED mode, output swithed together. Gang Individual Power Control downstream ports Individual Gang
KS86C6308/P6308 (Preliminary Spec)
CIRCUIT DIAGRAMS
Pull-up Resistor Noise Filter
Output Data Open Drain Output DIsable
Input Data
Figure 1-4. Circuit Type (RESET)
Figure 1-6. Circuit Type (Port
Pull-up Resistor Pull-up Enable Output Data Output Disable Open Data Open Drain Output DIsable Pull-up Enable Pull-up Resistor
Input Data
Input Data
Figure 1-5. Circuit Type (Port Figure 1-7. Circuit Type (Port
KS86C6308/P6308 (Preliminary Spec)
Pull-up Resistor
Figure 1-8. Circuit Type
<3.6 Only Upstream Ports Equivalent RXDP RXDM TXDP Speed (Only Downstream Ports) TXDM
Only Downstream Ports
Figure 1-9. Circuit Type
KS86C6308/P6308 (Preliminary Spec)
Output
Data
Figure 1-10. Circuit Type
1-10
KS86C6308/P6308 (Preliminary Spec)
APPLICATION CITCUIT
KS86C6308 (P6308)
Upstream Port Downstream Ports GANGED
Keyboard Matrix
P2.0-P2.7 P0.0-P0.7 P1.0-P1.7
P3.2 P3.1 P3.0 PWREN1 PWREN2 LEDON0 LEDON1 OCDET1 LEDON2 LEDON3 LEDON4 OCDET2 OCDET3 OCDET4
PWREN3 PWREN4 Power Switch
NOTES: recommand Power Switch, MIC2525 MICREL Semiconductor). proper operation PLL, external filter consisting series network resistor capacitor must connected from Port3 direct drive. Upstream GPIO interface (see GPIOCONINT)
Figure 1-11. Bus-Powered, Gang Port (64-SDIP, 64-QFP)
KS86C6308/P6308 (Preliminary Spec)
KS86C6308 (P6308)
Upstream Port Downstream Ports GANGED
Keyboard Matrix
P2.0-P2.7 P0.0-P0.7 P1.0-P1.7
P3.2 P3.1 PWREN1 P3.0 OCDETEN
LEDON0 LEDON1 LEDON2 LEDON3 LEDON4
PWREN2 OCDET2
PWREN3 OCDET3
PWREN4 OCDET4
Power Switching
NOTES: recommand Power Switch, MIC2525 MICREL Semiconductor). proper operation PLL, external filter consisting series network resistor capacitor must connected from Port3 direct drive. Upstream GPIO interface (see GPIOCONINT)
Figure 1-12. Bus-Powered, Individual Port (64-SDIP, 64-QFP)
1-12
KS86C6308/P6308 (Preliminary Spec)
ADDRESS SPACES
OVERVIEW
ADDRESS SPACES
KS86C6308/P6308 microcontroller kinds address space: Program memory (ROM), internal Internal register file 13-bit address supports both program memory. separate 8-bit register carries addresses data between internal register file. KS86C6308 bytes mask-programmable program memory on-chip. There program memory configuration option: Internal mode, which only 8-Kbyte internal program memory used. KS86C6308/P6308 microcontroller general-purpose registers internal register file. Twentyseven bytes register file mapped system peripheral control functions.
ADDRESS SAPCES
KS86C6308/P6308 (Preliminary Spec)
PROGRAM MEMORY (ROM) Normal Operating Mode (Internal ROM) KS86C6308/P6308 bytes (locations 0H-1FFFH) internal mask-programmable program memory. first bytes (0000H-0001H) interrupt vector address. program reset address 0100H.
(DECIMAL) 8,19
(HEX) 1FFFH
8-Kbyte Internal Program Memory Area
Program Start
0100H
Interrupt Vector
0200H 0001H 0000H
Figure 2-1. Program Memory Address Space
KS86C6308/P6308 (Preliminary Spec)
ADDRESS SPACES
REGISTER ARCHITECTURE upper bytes KS86C6308/P6308's internal register file addressed working registers, system control registers peripheral control registers. lower bytes internal register file (00H-8FH) called general purpose register space. total addressable register space thereby bytes. available general-purpose use. many SAM88RCRI microcontrollers, addressable area internal register file further expanded additional more register pages general purpose register space (00H-8FH). This register file expansion implemented KS86C6308/P6308. specific register types area bytes) that they occupy internal register file summarized Table 2-1. Table 2-1. Register Type Summary Register Type system control registers Peripheral, I/O, clock control data registers General-purpose registers (including 16-bit common working register area) Total Addressable Bytes Number Bytes
ADDRESS SAPCES
KS86C6308/P6308 (Preliminary Spec)
Control System Register, Peripheral Register Working Register Area Control System Register, Peripheral Register
Bytes Common Area
Port Registers
Gerneral Purpose Register File
Bytes
Page
Figure 2-2. Register Architecture
KS86C6308/P6308 (Preliminary Spec)
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH) SAM88RCRI register architecture provides efficient method working register addressing that takes full advantage shorter instruction formats reduce execution time. This 16-byte address range called common area. That locations this area used working registers operations that address location page register file. Typically, these working registers serve temporary buffers data operations between different pages. However, because KS86C6308/P6308 uses only page common area internal data operation. Register addressing mode used access this area Registers addressed either single 8-bit register paired 16-bit register. 16-bit register pairs, address first 8-bit register always even number address next register number. most significant byte 16-bit data always stored even-numbered register; least significant byte always stored next odd-numbered register.
EVEN ADDRESS
Figure 2-3. 16-Bit Register Pairs
PROGRAMMING Addressing Common Working Register Area
following examples show, should access working registers common area, locations C0H-CFH, using working register addressing mode only. Examples: 0C2H,40H Invalid addressing mode! working register addressing instead: R2,40H (C2H) value location
0C3H,#45H Invalid addressing mode! working register addressing instead: R3,#45H (C3H)
ADDRESS SAPCES
KS86C6308/P6308 (Preliminary Spec)
SYSTEM STACK KS86-series microcontrollers system stack subroutine calls returns store data. PUSH instructions used control system stack operations. KS86C6308/P6308 architecture supports stack operations internal register file. Stack Operations Return addresses procedure calls interrupts data stored stack. contents saved stack CALL instruction restored instruction. When interrupt occurs, contents FLAGS register pushed stack. IRET instruction then pops these values back their original locations. stack address always decremented before push operation incremented after operation. stack pointer (SP) always points stack frame stored stack, shown Figure 2-4.
HIGH ADDRESS
STACK STACK FLAGS STACK CONTENTS AFTER INTERRUPT
STACK CONTENTS AFTER CALL INSTRUCTION
ADDRESS
Figure 2-4. Stack Operations Stack Pointer (SP) Register location contains 8-bit stack pointer (SP) that used system stack operations. After reset, value undetermined. Because only internal memory space implemented KS86C6308/P6308, must initialized 8-bit value range 00H-8FH.
NOTE: case Stack Pointer initialized 00H, decreased when stack operation starts. This means that Stack Pointer access invalid stack area.
KS86C6308/P6308 (Preliminary Spec)
ADDRESS SPACES
PROGRAMMING Standard Stack Operations Using PUSH
following example shows perform stack operations internal register file using PUSH instructions:
SP,#0C0H
(Normally, 0C0H initialization routine)
PUSH PUSH PUSH PUSH
CLKCON
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH
CLKCON
CLKCON
Stack address 0BCH Stack address 0BDH CLKCON Stack address 0BEH Stack address 0BFH
ADDRESS SAPCES
KS86C6308/P6308 (Preliminary Spec)
NOTES
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
OVERVIEW
Register
ADDRESSING MODES
Instructions that stored program memory fetched execution using program counter. Instructions indicate operation performed data operated Addressing mode method used determine location data operand. operands specified SAM88RCRI instructions condition codes, immediate data, location register file, program memory, data memory. SAM88RCRI instruction supports explicit addressing modes. these addressing modes available each instruction. addressing modes their symbols follows:
Indirect Register (IR) Indexed Direct Address (DA) Relative Address (RA) Immediate (IM)
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
REGISTER ADDRESSING MODE Register addressing mode, operand content specified register (see Figure 3-1). Working register addressing differs from Register addressing because uses 16-byte working register space register file 4-bit register within that space (see Figure 3-2).
Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
OPCODE
Point Rigister Register File Value used Instruction Execution
OPERAND
Sample Instruction: CNTR Where CNTR label 8-bit register address
Figure 3-1. Register Addressing
Register File
Program Memory 4-Bit Working Register Two-Operand Instruction (Example) Sample Instruction: Where LSBs Point Woking Register
OPERAND
OPCODE
Figure 3-2. Working Register Addressing
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) Indirect Register (IR) addressing mode, content specified register register pair address operand. Depending instruction used, actual address point register register file, program memory (ROM), external memory space (see Figures through 3-6). 8-bit register indirectly address another register. 16-bit register pair used indirectly address another memory location.
Program Memory 8-Bit Register File Address One-Operand Instruction (Example)
Register File
OPCODE
Point Rigister Register File Address Operand used Instruction
ADDRESS
Value used Instruction Execution Sample Instruction: @SHIFT
OPERAND
Where SHIFT label 8-Bit register address
Figure 3-3. Indirect Register Addressing Register File
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR Points Rigister Pair 16-Bit Address Points Program Memory
OPCODE
Program Memory Sample Instructions: CALL @RR2 @RR2
Value used Instruction
OPERAND
Figure 3-4. Indirect Register Addressing Program Memory
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory 4-Bit Working Register Address LSBs Point Woking Register
OPERAND
OPCODE
Sample Instruction:
Value used Instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing Register File
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
Program Memory 4-Bit Working Register Address OPCODE Next 3-Bits Point Working Register Pair Register Pair 16-Bit address points program memory data memory
Example Instruction References either Program Memory Data Memory
Selects
Program Memory Data Memory
Value used Instruction Sample Instructions: R5,@RR2 Program memory access R3,@RR14 External data memory access @RR4, External data memory access
OPERAND
Figure 3-6. Indirect Working Register Addressing Program Data Memory
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
INDEXED ADDRESSING MODE Indexed addressing mode adds offset value base address during instruction execution order calculate effective operand address (see Figure 3-7). Indexed addressing mode access locations internal register file external memory. short offset Indexed addressing mode, 8-bit displacement treated signed integer range -128 +127. This applies external memory accesses only (see Figure 3-8). register file addressing, 8-bit base address provided instruction added 8-bit offset contained working register. external memory accesses, base address stored working register pair designated instruction. 8-bit 16-bit offset given instruction then added base address (see Figure 3-9). only instruction that supports Indexed addressing mode internal register file Load instruction (LD). instructions support Indexed addressing mode internal program memory, external program memory, external data memory, when implemented.
Register File
Value used Instruction
OPERAND
Program Memory Two-Operand Instruction Example (OFFSET) OPCODE LSBs Point Woking Register
INDEX
Sample Instruction: #BASE[R1] Where BASE 8-bit immediate value
Figure 3-7. Indexed Addressing Register File
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
INDEXED ADDRESSING MODE (Continued)
Program Memory 4-Bit Working Register Address (OFFSET) OPCODE NEXT Bits Point Working Register Pair
Register File
Register Pair 16-Bit address added offset
Selects
8-Bits 16-Bits Program Memory Datamemory
16-Bits Sample Instructions:
OPERAND
Value used Instruction
#04H[RR2] values program address (RR2 #04H) loaded into register R4,#04H[RR2] Identical operation example, except that external program memory accessed.
Figure 3-8. Indexed Addressing Program Data Memory with Short Offset
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory (OFFSET) (OFFSET) OPCODE
Register File
4-Bit Working Register Address
NEXT Bits Point Working Register Pair Selects
Register Pair 16-Bit address added offset
16-Bits 16-Bits Program Memory Datamemory
16-Bits Sample Instructions:
OPERAND
Value used Instruction
#1000H[RR2]; values program address (RR2 #1000H) loaded into register R4,#1000H[RR2] Identical operation example, except that external program memory accessed.
Figure 3-9. Indexed Addressing Program Data Memory with Long Offset
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
DIRECT ADDRESS MODE (DA) Direct Address (DA) mode, instruction provides operand's 16-bit memory address. Jump (JP) Call (CALL) instructions this addressing mode specify 16-bit destination address that loaded into whenever CALL instruction executed. instructions Direct Address mode specify source destination address Load operations program memory (LDC) external data memory (LDE), implemented.
Program Data Memory
Program Memory
Memory Address Used
Upper Address Byte Lower Address Byte dst/src OPCODE
Selects Program Memory Data Memory: Program Memory Data Memory
Sample Instructions: R5,1234H R5,1234H values program address (1234H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-10. Direct Addressing Load Instructions
3-10
KS86C6308/P6308 (Preliminary Spec)
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE Program Memory Address Used Upper Address Byte Lower Address Byte OPCODE
Sample Instructions: CALL C,JOB1 Where JOB1 16-Bit immediate address Where DISPLAY 16-Bit immediate address
DISPLAY
Figure 3-11. Direct Addressing Call Jump Instructions
ADDRESSING MODES
KS86C6308/P6308 (Preliminary Spec)
RELATIVE ADDRESS MODE (RA) Relative Address (RA) mode, two's-complement signed displacement between specified instruction. displacement value then added current value. result address next instruction executed. Before this addition occurs, contains address instruction immediately following current instruction. instructions that support addressing
Program Memory
Next OPCODE Program Memory Address Used
Current Instruction
Displacement OPCODE
Current Value Signed Displacement Value
Sample Instructions: ULT,$+OFFSET Where OFFSET value range +127 -128
Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) Immediate (IM) addressing mode, operand value used instruction value supplied operand field itself. Immediate addressing mode useful loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value instruction) Sample Instruction:LD R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
OVERVIEW
CONTROL REGISTERS
this section, detailed descriptions KS86C6308/P6308 control registers presented easy-to-read format. These descriptions will help familiarize with mapped locations register file. also them quick-reference source when writing application programs. System peripheral registers summarized Table 4-1. Figure illustrates important features standard register description format. Control register descriptions arranged alphabetical order according register mnemonic. More information about control registers presented context various peripheral hardware descriptions Part this manual.
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
Table 4-1. System Peripheral control Registers Register Name Timer counter register Timer data register Timer control register Clock control register System flags register Stack pointer Port interrupt pending register Basic timer control register Basic timer counter register System mode register Port data register Port data register Status Change Endpoint Miscellaneous Control Register Suspend/Resume Control Register Port State Port selected PORTSEL register Bit0=VMIN Bit1=VPIN Bit7-Bit2=0 Interface Status Interface Status Full Speed Tranceiver crossover point control Speed Tranceiver crossover point control Interrupt Status register Interrupt Enable register Embebedded Function Change Status register. Similar embedded port register. Refer explanation ablvec Embebedded Function Status register, similar embedded port register this MCU, while embedded port register HOST Mnemonic TACNT TADATA TACON Location mapped. CLKCON FLAGS P0PND Location mapped. BTCON BTCNT Location mapped. STSCHGEP MISCCON SUSRECON PBUSSTE Decimal
Locations D6H-D8H mapped.
HINTFSTS0 HINTFSTS1 FSXCON LSXCON HINTSTS HINTEN EMBFCSTS
EMBFSTS
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
Table 4-1. System Peripheral control Registers (Continued) Register Name Device Status Device Status Endpoint1 Status Endpoint1 Status Endpoint0 Ststus Endpoint0 Status Status register Status register Change status register Change status register Endpoint Byte count register indicates bytes present FIFO Endpoint0 data buffer Endpoint0 control/status register Port select, selects port status transfer downstream port1 downstream port2 downstream port3 downstream port4 Port Status Port Status Port Status Change Port Status Change Lower bits Frame Num. frame number register contains frame number received with last Upper bits Frame Num. Interrupt Pending register Interrupt Mask Register Function endpoint0 Data buffer Function endpoint1 Data buffer Function endpoint2 Data buffer Function Interrupt Status register Function Interrupt Enable register Mnemonic DSTS0 DSTS1 HEP1STS0 HEP1STS1 HEP0STS0 HEP0STS0 HSTS0 HSTS1 HSTS2 HSTS3 HEP0BCNT HEP0BUF HEP0CSR PORTSEL Decimal
PXSTS0 PXSTS1 PXSTS2 PXSTS3 FRAMEL
FRAMEH INTPEND INTMASK FEP0BUF FEP1BUF FEP2BUF FINTSTS FINTEN
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
Table 4-1. System Peripheral control Registers (Concluded) Register Name Function endpoint byte count register, valid transfer Endpoint Control/Status register Endpoint Control/Status register Endpoint Configuration register Endpoint Packet size register Endpoint Select register Function Address register Port0 control register(LOW byte) Port0 control register(HIGH byte) Port1 control register(LOW byte) Port1 control register(HIGH byte) Port2 control register(LOW byte) Port2 control register(HIGH byte) Port0 interrupt control register Port0 interrupt pending register Port2 interrupt control register Port2 interrupt pending register Port3 Control register Port4 Control register Port4 interrupt enable pending register Port2 Data register Port3 Data register Port4 Data register mode select register USB/GPIO mode select register DM0/GPIO,DP0/GPIO Data register (Only GPIO mode GPIO control interrupt pending register Timer counter register High Timer counter register Timer Data register High Timer Data register Timer Control register Mnemonic FEPBCNT FEPINCSR FEPOUTCSR FEPCFG FEPMAXP FEPSEL FADDR P0CONL P0CONH P1CONL P1OCNH P2CONL P2CONH P0INT P0PND P2INT P2PND P3CON P4CON P4INTn P4PNDn mapped 90H-95H USBMODE USBSEL GPIODATA GPIOCONINT TACNTH TACNTL TADATAH TADATAL TACON Decimal
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
Timer interrupt priority pending register
INTPND
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
number(s) that is/are appended register name addressing Register mnemonic Full register name
Name individual function Register address (hexadecimal)
FLAGS- System Flags Register
Identifier
RESET
Value
Read/Write
Carry Flag Operation does generate carry borrow condition Operation generates carry-out borrow into high-order Zero Flag Operation result non-zero value Operation result zero Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Read-only Write-only Read/write used
Description effect specific settings
RESET
number: value notation: used Undetermined value Logic zero Logic
Addressing mode modes modify register values
Figure 4-1. Register Description Format
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
BTCON Basic Timer Control Register
Identifier
RESET Value
Read/Write .7-.4
Watchdog Timer Enable Bits Disable watchdog function Enable watchdog function other value
Basic Timer Input Clock Selection Bits fOSC/4096 fOSC/1024 fOSC/128 Invalid setting
Basic Timer Counter Clear (note) effect Clear BTCNT
Basic Timer Divider Clear (note) effect Clear both dividers
NOTE: When write BTCON.0 BTCON.1), basic timer counter basic timer divider) cleared. then cleared automatically "0".
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
CLKCON System Clock Control Register
Identifier
RESET Value
Read/Write
Oscillator Wake-up Function Enable main system oscillator wake-up power down mode Disable main system oscillator wake-up power down mode
used KS86C6308/P6308 Clock (System Clock) Selection Bits Divide (fOSC/16) Divide (fOSC/8) Divide (fOSC/2) Non-divided clock (fOSC)
.2-.0
used KS86C6308/P6308
NOTES: After reset, slowest clock (divided selected system clock. select faster clock speeds, load appropriate values CLKCON.3 CLKCON.4. fOSC means oscillator frequency.
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
EMBFCSTS- Embedded Function Status Change Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 C_RST effect Reset change interrupt pending (when this read) clear pending (when this written)
used KS86C6308/P6308 C_SUSP effect Reset change interrupt pending (when this read) clear pending (when this written)
used KS86C6308/P6308
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
EMBFSTS Embedded Function Status Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Function RESET Cleared when RESET embedded port register been cleared. host selectively reset function
used KS86C6308/P6308 Function SUSPEND Cleared host when sends remote resume. host selectively suspend embedded function.
Function Enable Function disabled Function enabled
Function Connection Cleared hardware when detecting RESET from host POWER RESET. indicate controller that embedded function present ready
4-10
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FADDR Function Address Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Function Address Bits (Loads address received)
Note: This register should loaded before setting DATAEND clearing OUTPKTRDY EP0CSR.
FEPBCNT Function Endpoint Byte Count Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Byte Count Bits Contains byte count FIFO
Byte Count: Once detects OUT_PKT_RDY CSR, then read this register find number bytes from Endpoint FIFO.
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
FEPCFG Function Endpoint Configuration Register
Identifier
RESET Value
Read/Write
Transfer Direction Out, host endpoint endpoint host
Endpoint Mode Selection Interrupt Bulk
Endpoint Mode Selection Interrupt Bulk
Endpoint Update Mode Status effect When this set, packet written endpoint sent host only after received.
used KS86C6308/P6308
4-12
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FEP0CSR Function Endpoint Control/Status Register
Identifier
RESET Value
BBH,BAH
R/C*
R/C*
Read/Write
Setup Data Clear effect (when write) clear Setup Data Clear
Packet Ready Clear effect (when write) clear Packet Ready Clear
Setup Transfer effect (when write) sets this when control transfer ends before
Setup Data effect (when write) sets this after loading unloading last packet data into FIFO
Stall Signal Receive clears this stall condition sets this control transaction ended protocol violation
Stall Signal Sending effect (when write) send stall signal
Packet Ready clear this once packet been successfully sent host sets this after writing packet data into endpoint FIFO
Packet Ready effect (when write) sets this once valid written FIFO
Note:
FEPSEL register value zero, this register configured above.
4-13
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
FEPINCSR Function Endpoint Register
Identifier
RESET Value
Read/Write
Data toggle Sequence Clear effect (when write) clear DATA1/DATA0 toggle
FIFO Flush Cleared after flush done flush FIFO
Packet Ready Status cleared when data been transferred host When writers this always
used KS86C6308/P6308 Stall Signal Sending effect (when write) send stall signal
FIFO Error clear this FIFO under-run error during
Packet Ready sets this once packet been successfully sent host sets this after writing packet data into endpoint FIFO
4-14
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FEPMAXP Function Endpoint Packet Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Packet Size Contains maximum packet size this Endpoint
Packet Size: maximum size buffer Endpoint bytes, packet size chosen less, packets loaded buffer. This recommended endpoint, since needs constant bandwidth.
4-15
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
FEPOUTCSR Function Endpoint Register
Identifier
RESET Value
Read/Write
Data Toggle Sequence Clear effect (when write) clear DATA1/DATA0 toggle
FIFO Flush Cleared after flush done flush FIFO
DATA ERROR clear this even core CEC/bit stuffing error
Stall Signal Receive clears this stall condition sets this control transaction ended protocol violation
used KS86C6308/P6308 Stall Signal Sending effect(when write) send stall signal
FIFO Error clear this FIFO under-run error during
Packet Ready Packet Ready Clear effect (when write) sets this once valid token written FIFO sets clear Packet Ready
4-16
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FEPSEL Function Endpoint Selection Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Function Endpoint Selection Bits Selects Endpoint0 Selects Endpoint1 Selects Endpoint2
FINTEN Function Endpoint Interrupt Enable Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Endpoint Interrupt Pending Disable ENDPOINT2 interrupt (default) Enable ENDPOINT2 interrupt
Endpoint Interrupt Pending Disable ENDPOINT1 interrupt (default) Enable ENDPOINT1 interrupt
Endpoint Interrupt Pending Disable ENDPOINT0 interrupt (default) Enable ENDPOINT0 interrupt
4-17
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
FINTSTS Function Endpoint Interrupt Pending Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Endpoint Interrupt Status sets this upon: Clearing Packet Ready Setting Packet Ready
Endpoint Interrupt Status sets this upon: Clearing Packet Ready Setting Packet Ready
Endpoint Interrupt Status sets this upon: Setting Packet Ready Clearing Packet Ready Setting Clearing Data
4-18
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FLAGS System Flags Register
Identifier
RESET Value
Read/Write
Carry Flag Operation does generate carry borrow condition
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Overflow Flag Operation result +127 -128 Operation result +127 -128
used KS86C6308/P6308
4-19
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
FRAMEH Frame Number High Byte Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Frame Error effect error detected, flag that ignore frame number internal value wait next this happens SYNCH_FRAME time.
Current Frame Number Bits Upper bits Frame number that contains current number received with last
4-20
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FRAMEL Frame Number Byte Register
Identifier
RESET Value
Read/Write
Current Frame Number Bits Lower bits Frame number that contains current number received with last
HEP0BCNT Endpoint Byte Count Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Endpoint Byte Count Bits number valid bytes Endpoint FIFO
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
HEP0BUF Endpoint Buffer Register
Identifier
RESET Value
Read/Write
Endpoint Data Buffer Bits Indicates Endpoint data byte deep count
4-22
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
HEP0CSR Endpoint Control/Status Register
Identifier
RESET Value
R/C*
R/C*
Read/Write
Setup Data Clear effect (when write) clear Setup Data Clear
Packet Ready Clear effect (when write) clear Packet Ready Clear
Setup Transfer effect (when write) sets this when control transfer ends before
Setup Data effect (when write) sets this after loading unloading last packet data into FIFO
Stall Signal Receive clears this stall condition sets this control transaction ended protocol violation
Stall Signal Sending effect (when write) send stall signal
Packet Ready clear this once packet been successfully sent host sets this after writing packet data into Endpoint FIFO
Packet Ready effect (when write) sets this once valid token written FIFO
4-23
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
HINTEN
Identifier
RESET Value
Interrupt Enable Register
Read/Write
Interrupt Enable Interrupt disable Interrupt enable
Suspend Resume Interrupt Enable Interrupt disable Interrupt enable
Connection Interrupt Enable Interrupt disable Interrupt enable
Function Interrupt Enable Interrupt disable Interrupt enable
used KS86C6308/P6308
4-24
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
HINTSTS
Identifier
RESET Value
Interrupt Pending Register
Read/Write
Interrupt Pending effect Endpoint serviced Write clear pending
Suspend Resume Interrupt Pending effect Suspend Resume signal received Write clear pending
Connection Interrupt Pending effect port connected function Write clear pending
Function Interrupt Pending effect This when Function Status Change register Write clear pending
used KS86C6308/P6308
4-25
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
INTMASK Interrupt Mask Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Start Frame Interrupt (USOFINT) Enable Interrupt disable Interrupt enable
used KS86C6308/P6308
4-26
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
INTPEND Interrupt Pending Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Start Frame Interrupt (USOFINT) Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
used KS86C6308/P6308
4-27
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
MISCCON Miscellaneous Control Register
Identifier
RESET Value
Read/Write
mapped KS86C6308 Handling Commands Enable Command decoder will take exception, instead will execute request return STALL host. Command decoder will take exception, whenever GET_DESCRIPTOR Unknown request from Host decoded
RESET Enable USB_RSTN remains high USB_RSTN asserted when reset detected.
PORTSEL Port Selection
Identifier
RESET Value
Register
Read/Write
used KS86C6308/P6308 Port Selection Status Transfer Bits Selects downstream Port1 Selects downstream Port2 Selects downstream Port3 Selects downstream Port4 Selects embedded port
4-28
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
USRECON
Identifier
RESET Value
Suspend/Resume Control Register
Read/Write
used KS86C6308/P6308 Suspend Status effect SUSPEND_OUT signal generated when enters power suspend mode (2ms after Suspend been set).
Resume Status effect RESUME_IN initiate remote resume
Suspend Status effect This when controller detects activity root excess ready into power suspend mode.
4-29
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
System Mode Register
Identifier
RESET Value
Read/Write .7-.4
used KS86C6308/P6308 Global Interrupt Enable (note) Disable global interrupt processing Enable global interrupt processing
Page Selection Bits Addressing page locations KS86C6308/P6308 Enable global interrupt processing Other values
NOTE: must selected into KS86C6308/P6308.
4-30
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
HEP1STS0 Endpoint Status Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. INT0_Stall endpoint halted, then halt feature reset zero endpoint halted, then halt feature
HEP0STS0 Endpoint Status Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. INT0_Stall endpoint halted, then halt feature reset zero endpoint halted, then halt feature
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
HSTS0 Status Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. Over-current Indicator over-current condition currently exists over-current condition exists
Local Power Source Local power supply good Local power supply lost (inactive)
HSTS2 Status Change Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. Over-Current Indicator Change change occurred Local Power Status Over-Current indicator changed
Local Power Status Change change occurred Over-Current Indicator Over-Current Indicator changed
4-32
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
PXSTS0 Port Status Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. PORT_RESET Reset signaling asserted Reset signaling asserted
PORT_OVER_CURRENT over-current condition exists this port over-current condition exists this port
PORT_SUSPEND suspended Suspended resuming
PORT_ENABLE Port disabled Port enabled
PORT_CONNECTION device present devices present this port
4-33
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
PXSTS1 Port Status High Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. PORT_LOW_SPEED Full-speed device attached this port Low-speed device attached this port
PORT_POWER This port Powered-off state This port Powered-off state
4-34
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
PXSTS2 Port Status Change Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read. C_PORT_RESET change Reset complete
C_PORT_OVER_CURRENT change occurred Over-Current Indicator Over-Current Indicator changed
PORT_SUSPEND change Resume complete
C_PORT_ENABLE change Current Port status changed
C_PORT_CONNECTION change occurred Current Connect status Current Connect status changed
PXSTS3 Port Status Change High Byte Register
Identifier
RESET Value
Read/Write
Reserved. These bits return when read.
4-35
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P0CONH Port Control Register (High Byte)
Identifier
RESET Value
Read/Write
P0.7 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.6 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.5 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.4 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
4-36
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
P0CONL Port Control Register (Low Byte)
Identifier
RESET Value
Read/Write
P0.3 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.2 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.1 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P0.0 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
4-37
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P0INT Port Interrupt Control Register
Identifier
RESET Value
Read/Write
P0.7 Configuration Bits External interrupt disable External interrupt enable
P0.6 Configuration Bits External interrupt disable External interrupt enable
P0.5 Configuration Bits External interrupt disable External interrupt enable
P0.4 Configuration Bits External interrupt disable External interrupt enable
P0.3 Configuration Bits External interrupt disable External interrupt enable
P0.2 Configuration Bits External interrupt disable External interrupt enable
P0.1 Configuration Bits External interrupt disable External interrupt enable
P0.0 Configuration Bits External interrupt disable External interrupt enable
4-38
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
P0PND Port Interrupt Pending Register
Identifier
RESET Value
Read/Write (NOTE)
P0.7 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.6 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.5 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.4 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.3 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.2 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.1 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.0 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-39
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P1CONH Port Control Register (High Byte)
Identifier
RESET Value
Read/Write
P1.7 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.6 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.5 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.4 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
4-40
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
P1CONL Port Control Register (Low Byte)
Identifier
RESET Value
Read/Write
P1.3 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.2 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.1 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P1.0 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P2CONH Port Control Register (High Byte)
Identifier
RESET Value
Read/Write
Port2,P2.7 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P2.6 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P2.5 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
P2.4 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
4-42
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
P2CONL Port Control Register (Low Byte)
Identifier
RESET Value
Read/Write
Port P2.3 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
Port P2.2 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
Port P2.1 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
Port P2.0 Configuration Bits Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edges external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
4-43
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P2INT Port Interrupt Enable Register
Identifier
RESET Value
Read/Write
P2.7 Interrupt Enable External interrupt disable External interrupt enable
P2.6 Interrupt Enable External interrupt disable External interrupt enable
P2.5 Interrupt Enable External interrupt disable External interrupt enable
P2.4 Interrupt Enable External interrupt disable External interrupt enable
P2.3 Interrupt Enable External interrupt disable External interrupt enable
P2.2 Interrupt Enable External interrupt disable External interrupt enable
P2.1 Interrupt Enable External interrupt disable External interrupt enable
P2.0 Interrupt Enable External interrupt disable External interrupt enable
4-44
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P2PND Port Interrupt Pending Register
Identifier
RESET Value
Read/Write (NOTE)
P2.7 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.6 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.5 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.4 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.3 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.2 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.1 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P2.0 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-46
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
NOTE: clear port interrupt pending condition, write corresponding P2PND register location.
P3CON Port Control Register
Identifier
RESET Value
Read/Write
Port P3.3 Configuration Bits Schmitt trigger input, Timer external clock input(TACLK) System clock output(CLO) mode. comes from system clock circuit. Push-pull output N-channel open-drain output mode
Port P3.2 Configuration Bits Schmitt trigger input,Timer1 external clock input(TBCLK) clock output(USBCLK) comes from Push-pull output N-channel open-drain output mode
Port P3.1 Configuration Bits Schmitt trigger input,Timer1 capture input(TBCAP) Timer0 Match output(TAOUT) Push-pull output N-channel open-drain output mode
Port P3.0 Configuration Bits Schmitt trigger input,Timer0 capture input(TACAP) Timer Match output(TAOUT) Push-pull output N-channel open-drain output mode
4-47
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
P4CON Port Control Register
Identifier
RESET Value
Read/Write .7-.4.
mapped KS86C6308/P6308 Port P4.1 Configuration Control Bits Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode with pull-up N-CH open drain output mode Output pull-pull mode
Port P4.0 Configuration Control Bits Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode with pull-up N-CH open drain output mode Output pull-pull mode
4-48
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
P4INTPND Port Interrupt Enable Pending Register
Identifier
RESET Value
Read/Write .7-.4
mapped KS86C6308/P6308 P4.1 Interrupt enable External interrupt disable External interrupt enable
P4.0 Interrupt enable External interrupt disable External interrupt enable
P4.1 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P4.0 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-49
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
GPIOCONINT GPIO Control interrupt pending Register
(GPIO Mode only)
Identifier
RESET Value
Read/Write
DP0/GPIO Configuration Control Bits Schmitt trigger input, falling edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
DM0/GPIO Configuration Control Bits Schmitt trigger input, falling edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
DP0/GPIO Interrupt Enable External interrupt disable External interrupt enable
DM0/GPIO Interrupt Enable External interrupt disable External interrupt enable pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
DP0/GPIO Interrupt Pending
DM0/GPIO Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-50
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
TACON Timer Control Register
Identifier
RESET Value
Read/Write
Counter Input Clock Selection Bits clock/1024 clock/256 clock/64 External clock(TACLK)
Operating Mode Selection Bits Interval timer mode (TAOUT) Capture mode(capture rising edge, counter running, occur) Capture mode(capture falling edge, counter running, occur) mode (OVF interrupt occur)
Counter Clear (TACLR) effect when written Clear Timer counter
Overflow Interrupt Enable (TAOVF) Disable overflow interrupt Enable overflow interrupt
Match/Capture Interrupt Enable (TAINT) Disable match interrupt Enable match interrupt
Match/Capture Interrupt Pending (TAPND) interrupt pending, Clear pending bit(write) Interrupt pending Interrupt pending(when read)/No effect(when write)
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
TBCON Timer Control Register
Identifier
RESET Value
Read/Write
Counter Input Clock Selection Bits fx/1024 fx/256 fx/64 fx/8 fx/1 External clock(TBCLK) Falling edge External clock(TBCLK) Falling edge Counter stop
Operating Mode Selection Bits Interval timer mode (TBOUT) Capture mode(capture rising edge, counter running, occur) Capture mode(capture falling edge, counter running, occur) mode (OVF match interrupt occur)
Counter Clear effect Clear Timer1 counter(when write)
Match/Capture Interrupt Enable Disable interrupt Enable interrupt
Overflow Interrupt Enable Disable overflow interrupt Enable overflow interrupt
4-52
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
USBSEL USB/GPIO Mode select Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Upstream Mode select Upstream port pull-up resister disable(GPIO mode) Upstream port pull-up register enable
Downstream Mode select Downstream port4 disable Downstream port4 enable
Downstream Mode select Downstream port3 disable Downstream port3 enable
Downstream Mode select Downstream port2 disable Downstream port2 enable
Downstream Mode select Downstream port1 disable Downstream port1 enable
USB/GPIO Mode select GPIO mode(GPIO port) global mode(USB port)
4-53
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
USBMODE Mode select Register
Identifier
RESET Value
Read/Write
used KS86C6308/P6308 Self Power Disable self power Enable self power
RESUME_IN Disable remote RESUME_IN Enable remote RESUME_IN
Function Disable function Enable function
4-54
KS86C6308/P6308 (Preliminary Spec)
CONTROL REGISTERS
FSXCON Full Speed Tranceiver Crossover Point Control Register
(This register will used control Tranceiver signal quality) Identifier
RESET Value
Read/Write .7-.6 .5~.0
used KS86C6308/P6308 Signal Crossover Point Control
4-55
CONTROL REGISTERS
KS86C6308/P6308(Preliminary Spec)
LSXCON Speed Tranceiver Crossover Point Control Register
(This register will used control Tranceiver signal quality) Identifier
RESET Value
Read/Write .7-.6 .5-.0
used KS86C6308/P6308 Signal Crossover Point Control Edge delay Control RISE edge FALL edge Delay Value (about) 2.5nsec Delay Unit
4-56
KS86C6308/P6308 (Preliminary Spec)
INTERRUPT STRUCTURE
OVERVIEW
INTERRUPT STRUCTURE
SAM88RCRI interrupt structure basic components: vector, sources. number interrupt sources serviced through interrupt vector which assigned address 0000H-0001H.
VECTOR
SOURCES
0000H 0001H
NOTES: SAM88RCRI interrupt only vector address (0000H-0001H). number value expandable.
Figure 5-1. KS86-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing controlled ways: either globally, specific interrupt level source. system-level control points interrupt structure therefore: Global interrupt enable disable instructions) Interrupt source enable disable settings corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, system mode register, (DFH), used enable disable interrupt processing. SYM.3 enable disable global interrupt processing respectively, modifying SYM.3. Enable Interrupt (EI) instruction must included initialization routine that follows reset operation order enable interrupt processing. Although manipulate SYM.3 directly enable disable interrupts during normal operation, recommend that instructions this purpose.
INTERRUPT STRUCTURE
KS86C6308/P6308 (Preliminary Spec)
INTERRUPT PENDING FUNCTION TYPES When interrupt service routine executed, application program's service routine must clear appropriate pending before return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there interrupt priority register SAM88RCRI, order service determined sequence source which executed interrupt service routine.
"EI" Instruction Execution
RESET
Interrupt Pending Register
Source Interrupts Source Interrupt Enable
Interrpt priority determind software polling method Global Interrupt Control (EI, instruction)
Vector Interrupt Cycle
Figure 5-2. Interrupt Function Diagram
KS86C6308/P6308 (Preliminary Spec)
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE interrupt request polling servicing sequence follows: source generates interrupt request setting interrupt request pending "1". generates interrupt acknowledge signal. service routine starts source's pending flag cleared software. Interrupt priority must determined software polling method. INTERRUPT SERVICE ROUTINES Before interrupt request serviced, following conditions must met: Interrupt processing must enabled (EI, SYM.3 "1") Interrupt must enabled interrupt's source (peripheral control register) above conditions met, interrupt request acknowledged instruction cycle. then initiates interrupt machine cycle that completes following processing sequence: Reset (clear "0") global interrupt enable register (DI, SYM.3 "0") disable subsequent interrupts. Save program counter status flags stack. Branch interrupt vector fetch service routine's address. Pass control interrupt service routine. When interrupt service routine completed, Interrupt Return instruction (IRET) occurs. IRET restores status flags sets SYM.3 "1"(EI), allowing process next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES interrupt vector area contains address interrupt service routine. Vectored interrupt processing follows this sequence: Push program counter's low-byte value stack. Push program counter's high-byte value stack. Push FLAGS register values stack. Fetch service routine's high-byte address from vector address 0000H. Fetch service routine's low-byte address from vector address 0001H. Branch service routine specified 16-bit vector address.
INTERRUPT STRUCTURE
KS86C6308/P6308 (Preliminary Spec)
KS86C6308/P6308 INTERRUPT STRUCTURE KS86C6308/P6308 microcontroller peripheral interrupt sources: Timer match/capture/overflow interrupt Timer match/capture/overflow interrupt Eight external interrupts port P2.0-P2.7 external interrupts port P4.0-P4.1 interrupt GPIO interrupt interrupt function interrupt interrupt
KS86C6308/P6308 (Preliminary Spec)
INTERRUPT STRUCTURE
Vector
Pending Bits TACON.0 TINTP.0 (EI/DI) SYM.3 TINTP.1 TINTP.2 P0PND.X P2PND.X P4INTPND.0 P4INTPND.1 GPIOINTP.1 GPIOINTP.0 INTPEND.2 FINTSTS.0 FINTSTS.1 FINTSTS.2 HINTSTS.4 HITSTS.5 HINTSTS.6 HINTSTS.7
Enable/Disable
Sources Timer Match/Capture Interrupt Timer Overflow Interrupt
0000H
TACON.2 TACON.3 TBCON.1 TBCON.2
Timer Match/Capture Interrupt Timer Overflow Interrupt P0.X External Interrupt
P0INT.X P2.X External Interrupt P2INT.X P4.0 External Interrupt P4INTPND.4 P4.1 External Interrupt P4INTPND.5 DP0/GPIO Interrupt GPIOINTP.3 DM0/GPIO Interrupt GPIOINTP.2 Interrupt INTMASK.2 ENDPNT0 Interrupt FINTEN.0 ENDPNT1 Interrupt FINTEN.1 ENDPNT2 Interrupt FINTEN.2 EMB_Function Interrupt HINTEN.4 CONN_LOST Interrupt HINTEN.5 SUSP_RESM Interrupt HINTEN.6 Interrupt HINTEN.7
NOTE: means bit. Interrupt service priority should managed interrupt service routine. Interrupt: Endpoint, Embedded Function Suspend/Resume Function Interrupt: Function Endpoints interrupt SOF: Start Frame maker interrupt
Figure 5-3. KS86C6308/P6308 Interrupt Structure
INTERRUPT STRUCTURE
KS86C6308/P6308 (Preliminary Spec)
NOTES
Clock Circuit
RESET Power-Down
Ports Basic Timer Timer Timer Universal Serial Electrical Data Mechanical Data KS86P6308 Development Tools
KS86C6308/P6308 (Preliminary Spec)
LOCK CIRCUIT
OVERVIEW
CLOCK CIRCUIT
external crystal ceramic oscillation source provides only clock KS86C6308.The XOUT pins connect oscillation source on-chip clock circuit. External clock crystal/ceramic oscillator circuits shown Figures 7-1.
XOUT
KS86C6308
Figure 7-1. Main Oscillator Circuit (External Crystal/Ceramic Oscillator)
MAIN OSCILLATOR LOGIC increase processing speed reduce clock noise, non-divided logic implemented main oscillator circuit. this reason, very high resolution waveforms (square signal edges) must generated order efficiently process logic operations. CLOCK STATUS DURING POWER-DOWN MODES power-down modes, Stop mode Idle mode, affect clock oscillation follows: Stop mode, main oscillator "freezes," halting peripherals. contents register file current system register values retained. Stop mode released, oscillator started, reset operation external interrupt with RC-delay noise filter (for KS86C6308). Idle mode, internal clock signal gated CPU, interrupt control timer. current status preserved, including stack pointer, program counter, flags. Data register file retained. Idle mode released reset interrupt (external internally-generated).
CLOCK CIRCUIT
S866308/P6308 (Preliminary Spec)
SYSTEM CLOCK CONTROL REGISTER (CLKCON) system clock control register, CLKCON, located location D4H. read/write addressable following functions: Oscillator wake-up function enable/disable (CLKCON.7) Oscillator frequency divide-by value: non-divided, (CLKCON.4 CLKCON.3) CLKCON register controls whether external interrupt used trigger Stop mode release (This called "IRQ wake-up" function). wake-up enable CLKCON.7. After reset, external interrupt oscillator wake-up function enabled, main oscillator activated, fOSC/16 (the slowest clock speed) selected clock. necessary, then increase clock speed fOSC, fOSC/2 fOSC/8.
System Clock Control Register (CLKCON) D4H,
Oscillator wake-up enable bit: Enable main-system oscillator wake-up function Disable main-system oscillator wake-up function
used KS86C6308/P6308 Divide-by selection bits clock frequency: fOSC/16 fOSC/8 fOSC/2 fOSC (non-divided)
used KS86C6308/P6308
Figure 7-2. System Clock Control Register (CLKCON)
KS86C6308/P6308 (Preliminary Spec)
LOCK CIRCUIT
Stop Instruction Oscillator Stop Main Oscillator Wake-up Noise Filter 1/16
CLKCON.3,
P3CON
Clock P3.3/CLO
CLKCON.7
Figure 7-3. System Clock Circuit Diagram
CLOCK CIRCUIT
S866308/P6308 (Preliminary Spec)
NOTES
KS86C6308/P6308 (Preliminary Spec)
RESET POWER-DOWN
OVERVIEW
RESET POWER-DOWN
SYSTEM RESET
During power-on reset, voltage High level RESET forced level. RESET signal input through Schmitt trigger circuit where then synchronized with clock. This brings KS86C6308 into known operating status. RESET must held level minimum time interval after power supply comes within tolerance order allow time internal clock oscillation stabilize. minimum required oscillation stabilization time reset approximately 5.5ms 216/fOSC, fOSC MHz). When reset occurs during normal operation (with both RESET High level), signal RESET forced reset operation starts. system peripheral control registers then their default hardware reset values (see Table 8-1). following sequence events occur during reset operation: interrupts disabled. watchdog function (basic timer) enabled. Ports input mode. Peripheral control data registers disabled reset their initial values. program counter loaded with reset address, 0100H. When programmed oscillation stabilization time interval elapsed, address stored location 0100H (and 0101H) fetched executed. NOTE program duration oscillation stabilization interval, must make appropriate settings basic timer control register, BTCON, before entering Stop mode. Also, want basic timer watchdog function (which causes system reset basic timer counter overflow occurs), disable writing '1010B' upper nibble BTCON.
RESET POWER-DOWN
KS86C6308/P6308 (Preliminary Spec)
POWER-DOWN MODES
STOP MODE Stop mode invoked instruction STOP (OPCODE 7FH). Stop mode, operation peripherals halted. That on-chip main oscillator stops supply current reduced less than system functions halted when clock "freezes," data stored internal register file retained. Stop mode released ways: RESET signal external interrupt. Using RESET Release Stop Mode Stop mode released when RESET signal released returns High level. system peripheral control registers then reset their default values contents data registers retained. RESET operation automatically selects slow clock (1/16) because CLKCON.3 CLKCON.4 cleared '00B'. After oscillation stabilization interval elapsed, executes system initialization routine fetching 16-bit address stored locations 0100H 0101H. Using External Interrupt Release Stop Mode Only external interrupts with RC-delay noise filter circuit used release Stop mode (Clock-related external interrupts cannot used). External interrupts KS86C6308 interrupt structure meet this criteria. Note that when Stop mode released external interrupt, current values system peripheral control registers changed. When interrupt release Stop mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. external interrupt Stop mode release, also program duration oscillation stabilization interval. this, must make appropriate control clock settings before entering Stop mode. external interrupt serviced when Stop mode release occurs. Following IRET from service routine, instruction immediately following that initiated Stop mode executed. NOTE STOP mode using external clock source because input must restricted internally reduce current leakage.
KS86C6308/P6308 (Preliminary Spec)
RESET POWER-DOWN
IDLE MODE Idle mode invoked instruction IDLE (opcode 6FH). Idle mode, operations halted while selected peripherals remain active. During Idle mode, internal clock signal gated CPU, interrupt logic timer/counters. Port pins retain mode (input output) they time Idle mode entered. There ways release Idle mode: Execute RESET. system peripheral control registers reset their default values contents data registers retained. reset automatically selects slow clock (1/16) because CLKCON.3 CLKCON.4 cleared '00B'. interrupts masked, RESET only release Idle mode. Activate enabled interrupt, causing Idle mode released. When interrupt release Idle mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. interrupt then serviced. Following IRET from service routine, instruction immediately following that initiated Idle mode executed. NOTE Only external interrupts that clock-related used release Stop mode. release Idle mode, however, type interrupt (that internal external) used.
RESET POWER-DOWN
KS86C6308/P6308 (Preliminary Spec)
HARDWARE RESET VALUES
Table list reset values system registers, peripheral control registers, peripheral data registers following reset operation normal operating mode. following notation used these tables represent specific reset values: shows RESET value logic logic zero, respectively. means that value undefined following RESET. dash ('-') means that either used mapped. Table 8-1. Register Values After RESET Register Function General Purpose Register File Stack Area Working Register Area Timer Counter Timer Data Timer Control Clock Control System Flags Stack Pointer Basic Timer Control Basic Timer Counter System Mode Port Data Port Data Status Change Endpoint Miscellaneous Control Suspend/Resume Control Port Status Port Selected PORTSEL VMIN, VPIN Bit7 Bit2 TACNT TADATA TACON CLKCON FLAGS BTCON BTCNT STSCHGEP MISCCON SUSRECON PBUSSTE Register Name 00-8F C0-CF Address Values After RESET
Location mapped.
Location mapped.
KS86C6308/P6308 (Preliminary Spec)
RESET POWER-DOWN
Table 8-1. Register Values After RESET (continued) Register Function Interface Status Interface Status Full Speed Tranceiver Crossover Point Control Speed Tranceiver Crossover Point Control Interrupt Status Interrupt Enable Embedded Function Change Status Register. Similar embedded port register. Refer explanation above. Embedded Function Status Register, similar embedded port status register this MCU, while embedded port register Host. Device Status Device Status Endpoint Status Endpoint Status Endpoint Status Endpoint Status Status Register Status Register Change Status Register Change Status Register Endpoint Byte count register, indicates bytes present FIFO Endpoint data buffer Endpoint control/status Port Select, selects port status transfer downstream port downstream port downstream port downstream port embedded port Register Name HINTFSTS0 HINTFSTS1 FSXCON LSXCON HINTSTS HINTEN EMBFCSTS Address Values After RESET
EMBFSTS
DSTS0 DSTS1 HEP1STS0 HEP1STS1 HEP0STS0 HEP0STS1 HSTS0 HSTS1 HSTS2 HSTS3 HEP0BCNT
HEP0BUF HEP0CSR PORTSEL
RESET POWER-DOWN
KS86C6308/P6308 (Preliminary Spec)
Table 8-1. Register Values After RESET (continued) Register Function Port Status Port Status Port Status Change Port Status Change Lower bits Frame Num. Frame Number register contains frame number received with last SOF. Upper bits Frame Interrupt Pending Interrupt Mask Function Endpoint Data Buffer Function Endpoint Data Buffer Function Endpoint Data Buffer Function Interrupt Status Function Interrupt Enable Function Endpoint Byte Count register, Valid Transfers Endpoint Control/Status Endpoint Control/Status Endpoint Configuration Endpoint Max. Packet size Endpoint Select Function Address Port control (LOW byte) Port control (HIGH byte) Port control (LOW byte) Port control (HIGH byte) Port control (LOW byte) Port control (HIGH byte) Port Interrupt Control Port Interrupt Pending Port Interrupt Control Port Interrupt Pending Port Control Port Control Register Name PXSTS0 PXSTS1 PXSTS2 PXSTS3 FRAMEL Address Values After RESET
FRAMEH INTPEND INTMASK FEP0BUF FEP1BUF FEP2BUF FINTSTS FINTEN FEPBCNT FEPINCSR FEPOUTCSR FEPCFG FEPMAXP FEPSEL FADDR P0CONL P0CONH P1CONL P1CONH P2CONL P2CONH P0INT P0PND P2INT P2PND P3CON P4CON
KS86C6308/P6308 (Preliminary Spec)
RESET POWER-DOWN
Table 8-1. Register Values After RESET (concluded) Register Function Port Interrupt Enable Pending Port Data Port Data Port Data Mode select USB/GPIO Mode select DM0/GPIO, DP0/GPIO Data (Only GPIO Mode) GPIO Control Interrupt Pending Timer Counter (HIGH) Timer Counter (LOW) Timer Data (HIGH) Timer Data (LOW) Timer control Timer Interrupt Priority Pending Register Name P4INTn P4PNDn USBMODE USBSEL GPIODATA GPIOCONIN TBCNTH TBCNTL TBDATAH TBDATAL TBCON INTPND Address Values After RESET
Location mapped.
RESET POWER-DOWN
KS86C6308/P6308 (Preliminary Spec)
NOTES
KS86C6308/P6408 (Preliminary Spec)
PORTS
OVERVIEW
PORTS
KS86C6308/P6308 Mode five ports (0-4) with total pins. GPIO mode ports (0-4 DP0/GPIO, DM0/GPIO) with total pins. access these ports directly writing reading port data register addresses. keyboard applications, ports usually configured keyboard matrix input/output. Port configured drive. Port used host communication controlling mouse other external device. Table 9-1. KS86C6308/P6308 Port Configuration Overview Port Function Description Bit-programmable port Schmitt trigger input open-drain output. Port0 individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input open-drain output. Port2 individually configured external interrupt inputs. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input, open-drain pushpull output. P3.3 used system clock output (CLO) timer pin. Bit-programmable port Schmitt trigger input open-drain output push-pull output. Port4 individually configured external interrupt inputs. output mode, pull-up resistors assignable software. input mode, pull-up resistors fixed. Bit-programmable port Schmitt trigger input open-drain output push-pull output. This port individually configured external interrupt inputs. output mode, pull-up resistors assignable software. input mode, pull-up resistors fixed. Programmability
DP0/GPIO DM0/GPIO (GPIO mode Only)
PORTS
KS86C6308/P6408 (Preliminary Spec)
PORT DATA REGISTERS Table gives overview port data register names, locations addressing characteristics. Data registers ports have structure shown Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port data register Port data register Port data register Port data register Port data register Mnemonic Decimal
PORT DATA REGISTER 0-4) Pn.1 Pn.0
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
Note: Because only four lower-nibble pins port port mapped, data register bits P3.4-P3.7, P4.2-P4.7 used.
Figure 9-1. Port Data Register Format
KS86C6308/P6408 (Preliminary Spec)
PORTS
PORT PORT Ports bit-programmable, general-purpose, ports. select Schmitt trigger input mode, N-CH open drain output mode. access ports directly writing reading corresponding port data registers (E0H) (E1H). reset clears port control registers P0CONH, P0CONL, P1CONH P1CONL '00H', configuring port port pins Schmitt trigger inputs. typical keyboard controller applications, sixteen port port pins used check pressed from keyboard matrix generating keystrobe output signals.
Port Control Registers P0CONH, R/W, P0CONL,
P0CONH P0CONL
P0.7/INT2 P0.3/INT2
P0.6/INT2 P0.2/INT2
P0.5/INT2 P0.4/INT2 P0.1/INT2 P0.0/INT2
7,5,3,1 6,4,2,0
Port Mode Selection Schmitt trigger input, rising edge external interrupt mode Schmitt trigger input, falling edge external interrupt mode with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
Figure 9-2. Port Control Registers (P0CONH, P0CONL)
PORTS
KS86C6308/P6408 (Preliminary Spec)
Port Control Registers P1CONH, R/W, P1CONL,
P1CONH P1CONL
P1.7 P1.3
P1.6 P1.2
P1.5
P1.4 P1.0
7,5,3,1 6,4,2,0
Port Mode Selection Schmitt trigger input mode Schmitt trigger input mode with pull-up N-CH open drain output mode N-CH open drain output mode with pull-up
Figure 9-3. Port Control Registers (P1CONH, P1CONL)
KS86C6308/P6408 (Preliminary Spec)
PORTS
PORT Port 8-bit port with individually configurable pins. used general (Schmitt trigger input mode push-pull output mode). port pins external interrupt (INT0) inputs. addition, configure pull-up resistor individual pins using control register settings. port circuits have noise filters. typical keyboard controller applications, port pins programmed receive input data from keyboard matrix. address port bits directly writing reading port data register, (AD). port high-byte low-byte control registers, P2CONH P2CONL, located addresses respectively. additional registers, used interrupt control: P2INT (A8) P2PND (A7). setting bits port interrupt enable register P2INT, configure specific port pins generate interrupt requests when rising falling signal edges detected. application program polls port interrupt pending register, P2PND, detect interrupt requests. When interrupt request acknowledged, corresponding pending must cleared interrupt service routine. case keyboard applications, port pins used read value from matrix.
Port Control Registers P1CONH, R/W, P1CONL,
P2CONH P2CONL
P2.7/INT0 P2.3/INT0
P2.6/INT0 P2.2/INT0
P2.5/INT0 P2.4/INT0 P2.1/INT0 P2.0/INT0
7,5,3,1 6,4,2,0
Port Mode Selection Schmitt trigger input, rising edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain N-CH open drain with pull-up
Figure 9-4. Port Control Registers (P2CONH, P2CONL)
PORTS
KS86C6308/P6408 (Preliminary Spec)
Port Interrupt Enable Register (P2INT)
P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 Port Interrupt Control Settings: P2.6/INT0 Disable interrupt P2.n P2.7/INT0 Enable interrupt P2.n
Figure 9-5. Port Interrupt Enable Register (P2INT)
Port Interrupt Pending Register (P2PND)
P2.0/INT0 P2.1/INT0 P2.2/INT0 P2.3/INT0 P2.4/INT0 P2.5/INT0 Port Interrupt Request Pending Bits: P2.6/INT0 interrupt pending P2.7/INT0 Interrupt request pending
Figure 9-6. Port Interrupt Pending Register (P2PND)
KS86C6308/P6408 (Preliminary Spec)
PORTS
PORT Port 4-bit, bit-configurable, general port. designed high-current functions such drive. reset configures P3.0-P3.3 Schmitt trigger input mode. Using P3CON register (A4), alternatively configure port pins n-channel, open-drain outputs. P3.3 used system clock output (CLO) port Timer Timer port.
Port Control Register (P3CON)
P3.0/TACAP/TBOUT P3.1/TBCAP/TAOUT P3.2/TBCLK P3.3/CLO/TACLK P3.3 Configuration Control Schmitt trigger input, Timer external clock input (TACLK) System Clock Ouput (CLO). comes from System clock circuit. Push-pull output N-CH open drain output P3.2 Configuration Control Schmitt trigger input, Timer external clock input (TBCLK) clock output (USB_CLK) USB_CLK comes from circuit. Push-pull output N-CH open drain output P3.1 Configuration Control Schmitt trigger input, Timer capture input (TBCAP) Timer match output (TAOUT) Push-pull output N-CH open drain output
P3.0 Configuration Control Schmitt trigger input, Timer capture input (TACAP) Timer match output (TBOUT) Push-pull output N-CH open drain output
Figure 9-7. Port Control Register (P3CON)
PORTS
KS86C6308/P6408 (Preliminary Spec)
PORT Port 4-bit port with individually configurable pins. used general (Schmitt trigger, N-CH open drain output mode, push-pull output mode). port pins external interrupt (INT1) inputs. addition, configure pull-up resistor individual pins using control register settings. port pins have noise filters. reset configures P4.0-P4.1 input mode. address port directly writing reading port data register, (AF). port control register, P4CON, located additional registers used interrupt control: P4INTPND (AC). setting bits port interrupt enable pending register P4INTPND.7-P4INTPND.4, configure specific port pins generate interrupt requests when falling signal edges detected. application program polls interrupt pending register, P4INTPND.1P4INTPND.0, detect interrupt requests. When interrupt request acknowledged, corresponding pending must cleared interrupt service routine.
Port Control Register (P4CON)
P4.0/INT1 P4.1/INT1 used KS86C6308/P6308 P4.1 Configuration Control Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output with pull-up register N-CH Open drain output Push-pull output
P4.0 Configuration Control Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output with pull-up register N-CH Open drain output Push-pull output
Figure 9-8. Port Control Register (P4CON)
KS86C6308/P6408 (Preliminary Spec)
PORTS
Port Interrupt Enable Pending Register (P4INTPND)
P4.0/INT1 P4.1/INT1 P4.0/INT1 P4.1/INT1 used KS86C6308/P6308 P4INTPND.3-4: Port Interrupt Control Settings: Disable interrupt P4.n Enable interrupt P4.n P4INTPND.1-0: Port Interrupt Pending Bits: interrupt request pending Interrupt request pending
Figure 9-9. Port Interrupt Enable Pending Register (P4INTPND)
PORTS
KS86C6308/P6408 (Preliminary Spec)
DP0/GPIO, DM0/GPIO
Control Interrupt Pending Register
DM0/GPIOPND DP0/GPIOPND DM0/GPIOPND DP0/GPIOPND DM0/GPIO DP0/GPIO
GPIOCONINT.7-4 Configration Settings: DP0/GPIO, DM0/GPIO Schmitt trigger input, falling edge external interrupt Schmitt trigger input, falling edge external interrupt with pull-up N-CH open drain output N-CH Open drain output with pull-up register
GPIO CONINT.3-2 Interrupt Control Setting Disable interrupt Enable interrupt GPIO CONINT.1-0 Interrupt Pending Setting interrupt request pending Interrupt request pending NOTE Used only GPIO mode.
Figure 9-10. GPIOCONINT Register (GPIOCONINT)
9-10
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
Basic Timer (BT)
BASIC TIMER TIMER TIMER
MODULE OVERVIEW
KS86C6308/P6308 default timers: 8-bit basic timer 8-bit general-purpose timer/counter. 8-bit timer/counter called timer
basic timer (BT) different ways: watchdog timer provide automatic reset mechanism event system malfunction. signal required oscillation stabilization interval after reset Stop mode release. functional components basic timer block are: Clock frequency divider (fOSC divided 4096, 1024, 128) with multiplexer 8-bit basic timer counter, BTCNT (DDH, read-only) Basic timer control register, BTCON (DCH, read/write)
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER CONTROL REGISTER (BTCON) basic timer control register, BTCON, used select input clock frequency, clear basic timer counter frequency dividers, enable disable watchdog timer function. reset clears BTCON '00H'. This enables watchdog function selects basic timer clock frequency fOSC/4096. disable watchdog function, must write signature code '1010B' basic timer register control bits BTCON.7-BTCON.4. 8-bit basic timer counter, BTCNT, cleared time during normal operation writing BTCON.1. clear frequency dividers both basic timer input clock timer clock, write BTCON.0.
Basic Timer Control Register (BTCON) DCH,
Watchdog timer enable bits: 1010B Disable watchdog function Other value Enable watchdog function
Divider clear basic: effect Clear both dividers
Basic timer counter clear bit: effect Clear BTCNT Basic timer input clock selection bits: fOSC/4096 fOSC/1024 fOSC/128 Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function program basic timer overflow signal generate reset setting BTCON.7-BTCON.4 value other than '1010B' (The '1010B' value disables watchdog function). reset clears BTCON '00H', automatically enabling watchdog timer function. reset also selects clock determined current CLKCON register setting) divided 4096 clock. reset whenever basic timer counter overflow occurs. During normal operation, application program must prevent overflow, accompanying reset operation, from occurring. this, BTCNT value must cleared writing BTCON.1) regular intervals. system malfunction occurs circuit noise some other error condition, counter clear operation will executed basic timer overflow will occur, initiating reset. other words, during normal operation, basic timer overflow loop overflow 8-bit basic timer counter, BTCNT) always broken BTCNT clear instruction. malfunction does occur, reset triggered automatically. Oscillation Stabilization Interval Timer Function also basic timer program specific oscillation stabilization interval following reset when Stop mode been released external interrupt. Stop mode, whenever reset external interrupt occurs, oscillator starts. BTCNT value then starts increasing rate fOSC/4096 (for reset), rate preset clock source (for external interrupt). When BTCNT.4 set, signal generated indicate that stabilization interval elapsed gate clock signal that resume normal operation. summary, following events occur when Stop mode released: During Stop mode, power-on reset external interrupt occurs trigger Stop mode release oscillation starts. power-on reset occurred, basic timer counter will increase rate fOSC /4096. external interrupt used release Stop mode, BTCNT value increases rate preset clock source. Clock oscillation stabilization interval begins continues until basic timer counter set. When BTCNT.4 set, normal operation resumes. Figures 10-2 10-3 shows oscillation stabilization time RESET STOP mode release
10-3
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
Oscillation Stabilization
Normal Operating mode
Reset ReleaseVoltage
RESET
trst Internal Reset Release
Oscillator (XOUT) Oscillator Stabilization Time
BTCNT clock BTCNT value 10000B 00000B tWAIT 4096x16x1/fOSC
Basic timer increment operations IDLE mode NOTE: During oscillator stabilization wait time, WAIT, when released Power-on-reset 4096x16/fosc. trst external resister chip capacitor)
Figure 10-2. Oscillation Stabilization Time RESET
10-4
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
Normal Operating Mode STOP Instruction Execution External Interrupt
RESET
STOP Mode
Oscillation Stabilization Time
Normal Operating Mode
STOP Mode Release Signal
STOP Release Signal
Oscillator (XOUT)
BTCNT clock
10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration oscillator stabilzation wait time, tWAIT, released interrupt determined setting basic timer control register, BTCON.
BTCON.3
BTCON.2
tWAIT
(4096 16)/fosc (1024 16)/fosc (128 16)/fosc Invalid setting
tWAIT (When MHz)
10.92 0.34
Figure 10-3. Oscillation Stabilization Time STOP Mode Release
10-5
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
8-BIT TIMER
OVERVIEW 8-bit timer 8-bit general-purpose timer/counter. Timer three operating modes, which select using appropriate TACON setting: Capture input mode with rising falling edge trigger TACAP Interval timer mode (Toggle output TAOUT pin) mode (TAPWM) Timer following functional components: Clock frequency divider divided 1024, 256, with multiplexer External clock input (TACLK) 8-bit counter (TACNT), 8-bit comparator, 8-bit reference data register (TADATA) pins capture input (TACAP) match output (TAPWM, TAOUT) Timer overflow interrupt (IRQ, vector, 00H) match/capture interrupt generation(IRQ,vector,00H) Timer control register, TACON (D2H, r/w)
10-6
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
FUNCTION DESCRIPTION timer module generate interrupts: timer overflow interrupt, timer match/ capture interrupt (TAINT). timer overflow interrupt pending condition automatically cleared hardware when been serviced. timer match/capture interrupt, TAINT pending condition also cleared hardware when been serviced. Interval Timer Function timer module generate interrupt: timer match interrupt (TAINT).When timer measure interrupt occurs serviced CPU, pending condition cleared automatically hardware. interval timer mode, match signal generated TAOUT toggled when counter value identical value written reference data register, TADATA. match signal generates timer match interrupt clears counter. example, write value TADATA TACON, counter will increment until reaches 10H. this point, interrupt request generated, counter value reset, counting resumes. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets program width (duration) pulse that output TAPWM pin. interval timer mode, match signal generated when counter value identical value written timer data register. mode, however, match signal does clear counter. Instead, runs continuously, overflowing FFH, then continues incrementing from 00H. Although match signal generate timer overflow interrupt, interrupts typically used PWM-type applications. Instead, pulse TAPWM held level long reference data value less than equal counter value then pulse held High level long data value greater than counter value. pulse width equal tCLK Capture Mode capture mode, signal edge that detected TACAP opens gate loads current counter value into data register. select rising falling edges trigger this operation. Timer also gives capture input source: signal edge TACAP pin. select capture input setting value timer capture input selection port control register, P3CON. When P3CON.1.0 TACAP input normal input selected. When P3CON.3.2 TAOUT output selected. Both kinds timer interrupts used capture mode: timer overflow interrupt generated whenever counter overflow occurs; timer match/capture interrupt generated whenever counter value loaded into data register. reading captured data value TADATA, assuming specific value timer clock frequency, calculate pulse width (duration) signal that being input TACAP pin.
10-7
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
TIMER CONTROL REGISTER (TACON) timer control register, TACON, Select timer operating mode (interval timer, capture mode, mode) Select timer input clock frequency Clear timer counter, TACNT Enable timer overflow interrupt timer match/capture interrupt Clear timer match/capture interrupt pending conditions TACON located address D2H, read/write addressable using Register addressing mode. reset clears TACON '00H'. This sets timer normal interval timer mode, selects input clock frequency fx/1024, disables timer interrupts. clear timer counter time during normal operation writing TACON.3. timer overflow interrupt (TAOVF) interrupt level vector address 00H. When timer overflow interrupt occurs serviced CPU, pending condition cleared automatically hardware. enable timer match/capture interrupt, must write TACON.1 "1". generate exact time interval, should write TACON.0 which cleared counter interrupt pending bit. program should poll pending bit. When detected, timer match/capture overflow interrupt detect match/capture overflow interrupt pending condition when TAINT TAOVF disabled, application pending. When sub-routine been serviced, pending condition must cleared software writing interrupt pending bit.
Timer Control Register D2H, R/W, Reset:
Timer input clock selection bits: fx/1024 fx/256 fx/64 External clock (T0CLK)
Timer match/capture interrupt pending interrupt pending Clear pending (when write) Interrupt pending Timer match/capture interrupt enable bit: Disable interrupt Enable interrupt Timer overflow interrupt enable bit: Enable overflow interrupt Disable overflow interrupt Timer counter enable bit: effect Clear timer counter (when write)
Timer operation selection bits: Interval mode (T0OUT mode) Capture mode (capture rising edge, counter running occur) Capture mode (capture falling edge, counter running occur) mode (OVF interrupt occur)
Figure 10-4. Timer Control Register (TACON)
10-8
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
Interrupt Pending Register 9FH,
used
Timer overflow interrupt pending interrupt pending Clear pending (when write) Interrupt pending Timer match/capture interrupt pending bit: interrupt pending Clear pending when write Interrupt pending Timer overflow interrup pending bit: interrupt pending Clear pending (when write) Interrupt pending
Figure 10-5. Interrupt Pending Register
TACON.7-.6 fx/1024 fx/256 fx/64 TACLK 8-Bit Compatator TACAP 8-Bit Counter (Read-Only) Clear Match
TACON.2 TAOVF Pending TACON.3
TACON.1 TACON.0 TAINT TAOUT TAPWM TACON.5-.4
Timer Buffer Reg.
TACON.5-.4 Counter Clear Signal Match Timer Data Reg.
Pending located other register
Figure 10-6. Interrupt Pending Register
10-9
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
16-BIT TIMER
OVERVIEW 16-bit timer 16-bit general-purpose timer/counter. Timer three operating modes, which select using appropriate TBCON setting: Interval timer mode(Toggle output TBOUT pin) Capture input mode with rising falling edge trigger TBCAP mode (TBPWM) Timer following functional components: Clock frequency divider (fxx divided 1024,256, with multiplexer External clock input (TBCLK) 16-bit counter (TBCNTH/L), 16-bit comparator, 16-bit reference data register (TBDATAH/L) pins capture input (TBCAP), match output(TBPWM, TBOUT) Timer overflow interrupt match/capture interrupt generation Timer control register, TBCON (set 9EH, read/write)
10-10
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
FUNCTION DESCRIPTION Timer Interrupts. timer module generate interrupts: timer overflow interrupt (TBOVF), timer match/ capture interrupt (TBINT). TBOVF interrupt level IRQ, vector 00H. TBINT also belongs interrupt level IRQ. timer overflow interrupt pending condition automatically cleared hardware when been serviced. timer match/capture interrupt, TBINT pending condition also cleared hardware when been serviced. Interval Timer Function timer module generate interrupt: timer match interrupt (TBINT). TBINT assigned vector address, 00H. When timer measure interrupt occurs serviced CPU, pending condition cleared automatically hardware. interval timer mode, match signal generated TBOUT toggled when counter value identical value written timer reference data register, TBDATAH/L. match signal generates timer match interrupt clears counter. example, write value 00B0H TBDATAH/L TBCON, counter will increment until reaches 00B0H. this point, interrupt request generated, counter value reset, counting resumes. Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets program width (duration) pulse that output TBPWM pin. interval timer mode, match signal generated when counter value identical value written timer data register. mode, however, match signal does clear counter generate match interrupt. counter runs continuously, overflowing FFFFH, then repeat incrementing from 0000H. Whenever overflow occurred, overflow(OVF) interrupt generated. Although match overflow interrupt mode, interrupts typically used PWMtype applications. Instead, pulse TBPWM held level long reference data value less than equal counter value then pulse held High level long data value greater than counter value. pulse width equal tCLK 65536. Capture Mode capture mode, signal edge that detected TBCAP opens gate loads current counter value into data register. select rising falling edges trigger this operation. Timer also gives capture input source: signal edge TBCAP pin. select capture input setting value timer capture input selection port control register, P3CON, (set AAH). When P3CON3.2 TBCAP input normal input selected. When P1CON3.2 normal output selected. Both kinds timer interrupts used capture mode: timer overflow interrupt generated whenever counter overflow occurs; timer match/capture interrupt generated whenever counter value loaded into data register. reading captured data value TBDATAH/L, assuming specific value timer clock frequency, calculate pulse width (duration) signal that being input TBCAP pin.
10-1
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
TIMER CONTROL REGISTER (TBCON) timer control register, TBCON, Select timer operating mode (interval timer, capture mode, mode) Select timer input clock frequency Clear timer counter, TBCNTH/L Enable timer overflow interrupt timer match/capture interrupt Clear timer match/capture interrupt pending conditions TBCON located address 9EH, read/write addressable using Register addressing mode. reset clears TBCON '00H'. This sets timer normal interval timer mode, selects input clock frequency fOSC/1024, disables timer interrupts. disable counter operation, please TBCON.7 111B. clear timer counter time during normal operation writing TBCON.3. timer overflow interrupt (TBOVF) interrupt level vector address 00H. When timer overflow interrupt occurs serviced CPU, pending condition cleared automatically hardware. enable timer match/capture interrupt, must write TBCON.1 "1". generate exact time interval, should write TBCON.2 which clear counter interrupt pending bit. detect match/capture overflow interrupt pending condition when TBINT TBOVF disabled, application program should poll pending bit. When detected, timer match/capture overflow interrupt pending. When sub-routine been serviced, pending condition must cleared software writing interrupt pending bit.
10-12
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
Timer Control Register (TBCON) 9EH, R/W, Reset:
Timer input clock selection bits: fx/1024 fx/256 fx/64 fx/1 External clock (TBCLK) falling edge External clock (TBCLK) rising edge Counter stop
Timer overflow interrupt enable bit: Enable overflow interrupt Disable overflow interrupt
Timer match/capture interrupt enable bit: Disable interrupt Enable interrupt
Timer operation mode selection bits: Interval mode (TBOUT) Capture mode (capture rising edge, counter running occur) Capture mode (capture falling edge, counter running occur) mode (OVF match interrupt occur)
Timer counter clear bit: effect Clear timer counter (when write)
Figure 10-7. Timer Control Register (TBCON)
10-13
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
Timer Counter High-Byte Register (TBCNTH) 9AH,
Reset Value: Timer Counter Low-Byte Register (TBCNTL) 9BH,
Reset Value: Timer Data High-Byte Register (TBDATAH) 9CH,
Reset Value: Timer Data Low-Byte Register (TBDATAL) 9DH,
Reset Value:
Figure 10-8. Timer Counter Register
10-14
KS86C6308/P6308 (Preliminary Spec)
BASIC TIMER TIMER TIMER
TBCON.7-.5
fx/1024 fx/256 fx/64 fx/8 fx/1 TBCLK 16-Bit Compatator TBCAP 16-Bit Counter (Read-Only) Clear Match TBCON.1 Pending TBINT TBOUT TBPWM TBCON.2 Pending TBCON.0 TBOVF
Timer Buffer Reg.
TBCON.4-.3
TBCON.4-.3 Counter Clear Signal Match Timer Data Register
Pending located other register
Figure 10-9. Timer Functional Block Diagram
10-15
BASIC TIMER TIMER TIMER
KS86C6308/P6308 (Preliminary Spec)
NOTES
10-16
KS86C6308/P6308 (Preliminary Spec)
UNIVERSAL SERIAL
1OVERVIEW
UNIVERSAL SERIAL
Universal Serial (USB) communication architecture that supports data transfer between host computer wide range peripherals. actually cable which peripherals share bandwidth through host scheduled token based protocol. basic blocks used KS86C6308 Repeater, Controller, Serial Interface Engine Function Interface Unit. module KS86C6308 accommodate both full speed (12Mbs) speed (1.5Mbs) transfer rate device described Universal Serial Specification Revision 1.0. KS86C6308 briefly describe microcontroller with 88RCRI core with on-chip peripheral that serve function seen Figure 11-1. KS86C6308 compound device. usability dynamic, serve function providing interface peripheral same time, serve providing ports additional peripherals perform these functions separately. Please refer specification revision detail description USB. Functional Features: Three functions endpoint pairs FIFO sizes; endpoint support three transfer types bytes) Connectivity four downstream ports Power management Device connect/disconnect detection fault detection recovery Supports both full speed(12Mbs) speed (1.5Mbs) transfer rate powered support Programmable ganged individual port power control Protocol handling hardware control command execution hardware Flexible unit interface descriptors other extensions Embedded function with programmable endpoints Built-in 3.3V voltage regulator
UNIVERSAL SERIAL
KS86C6308/P6308 (Preliminary Spec)
General Function Features: On-chip transceivers Automatic transmit/receive FIFO management Suspend/resume interrupt Programmable ganged power switching individual port power switching General Features: Most functions will carried hardwired module except special instructions. endpoint0: transmit/receive FIFO (8-bytes) endpoint1: transmit data buffer register (1-byte) internal downstream port Four external downstream port
11-2
KS86C6308/P6308 (Preliminary Spec)
UNIVERSAL SERIAL
XCVR 1-Up Stream
Voltage Regulator (3.3
Repeater (RPTR)
Command Unit (HCU)
XCVR
XCVR
XCVR
XCVR
Power Control
Gang pwr.
Control/Status
4-DownStream
Figure 11-1. Module Block Diagram
11-3
UNIVERSAL SERIAL
KS86C6308/P6308 (Preliminary Spec)
FUNCTION DESCRIPTIONS
SERIAL INTERFACE ENGINE (SIE) Serial Interface Engine handles communication protocol USB, shared between Controller Function Interface only transmit receive time. function carry serial protocol, data encoding/decoding, checking/generation data conversion between serial parallel data. Serial Interface Engine implements protocol layer USB. handles clock recovery, error checking, handshake packet directed time response from host late, other protocol related functions. consists Digital Phase Locked Loop (DPLL) clock recovery from incoming data, checker generator, stuff removal logic, NRZI encoder/decoder, shift register serial/parallel conversion, decoder, data toggle sync detect logic. INTERFACE UNIT (SIU) Interface Unit interfaces with parallel data pass HIU, multiplex data from send SIE. Other important function compare device endpoint address token packet with valid device endpoint addresses from embedded function, generate address valid signal complete handshake start wait data phase. REPEATER (RPTR) Repeater function repeat data from upstream port enabled downstream ports repeat data from downstream port upstream port. Multiple downstream ports cannot transmitting data same time according protocol, that happens would error will handled separately. This block handles global suspend resume from upstream port also handles remote resume from down stream port upstream port, well enable downstream port. Repeater block consists logic port control, repeater state machine data multiplexers data upstream each downstream ports. port control manages connectivity/disconnectivity, suspend/resume, reset SOP/EOP detection. repeater state-machine manages direction data multiplexers, detection error condition like babble loss activity. CONTROLLER controller endpoints, Endpoint0 Interrupt Endpoint. host configuration information, status also control enabling/disabling ports, turning power off, other various controllable features. INTERFACE UNIT (HIU) Like interface, Interface Unit interfaces with side, command unit interface other side. interface provided extra flexibility allow handle certain commands like GET_DESRIPTOR, able read port status registers, handle unimplemented commands HCU. will have 8-byte bi-directional FIFOs loading setup data from host MCU, loading data from host. This block logic will also handle multiplexing data from unit.
11-4
KS86C6308/P6308 (Preliminary Spec)
UNIVERSAL SERIAL
COMMAND UNIT (HCU) This block logic executes commands received from host SETUP packet. Simple commands like FEATURE, CLEAR FEATURE STATUS executed single cycle require multiple packets, these commands implemented here hardware. Some commands like DESCRIPTORS take multiple packets complete transaction these will handled MCU. Also command implemented will passed handle. Command Unit executes sub-set commands hub, receive host, supported Compound Device which UsbCompM implemented. executes both standard device class commands class commands. required commands some optional commands supported, following list commands implemented. Rest required commands other supported optional commands need implemented firmware MCU. Standard Requests: SET_ADDRESS GET_STATUS, device, interface, endpoints GET_CONFIGURATION, device SET_CONFIGURATION, device SET_ FEATURE, device, interface, endpoints CLEAR_FEATURE, device, interface, endpoints SET_INTERFACE GET_INTERFACE Class Requests: CLEAR_HUB_FEATURE CLEAR_PORT_FEATURE, port GET_BUS_STATE, port GET_HUB_STATUS GET_PORT_STATUS, port SET_HUB_FEATURE SET_PORT_FEATURE, port
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