SAM87RI PRODUCT FAMILY Samsung's SAM87RI family 8-bit single-chip

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SAM87RI PRODUCT FAMILY Samsung's SAM87RI family 8-bit single-chip

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KS86C6104/P6104
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family 8-bit single-chip CMOS microcontrollers offer fast efficient CPU, wide range integrated peripherals, supports device. dual address/data architecture bit- nibble-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations.
KS86C6104/P6104 MICROCONTROLLER
KS86C6104/P6104 microcontroller with function used wide range general purpose applications. especially suitable mouse joystick controller available 20-pin 24-pin package. KS86C6104/P6104 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM87RI core. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C6104/P6104 Kbytes program memory on-chip bytes including bytes working register. Using SAM87Ri design approach, following peripherals were integrated with SAM87Ri core: configurable ports pins) bit-programmable pins external interrupts 8-bit timer/counter with operating modes
KS86C6104 microcontroller also available (One Time Programmable) version, KS86P6104. KS86P6104 microcontroller on-chip 4-Kbyte one-time-programmable EPROM instead masked ROM. KS86P6104 comparable KS86C6104, both function configuration.
KS86C6104/P6104
FEATURES
SAM87RI core Timer/Counter 8-bit basic timer watchdog function programmable oscillation stabilization interval generation function 8-bit timer/counter with Compare/Overflow counter
Memory 4-Kbyte internal program memory (ROM) 208-byte bytes working register
Serial Compatible speed (1.5 Mbps) device specification. Serial interface engine (SIE) Packet decoding/generation generation checking NRZI encoding/decoding bit-stuffing 8-byte receive/transmit buffer
Instruction instructions IDLE STOP instructions added powerdown modes
Instruction Execution Time fOSC
Interrupts interrupt sources with vector level, vector interrupt structure
Operating Temperature Range 40°C 85°C
Operating Voltage Range 5.25
Oscillation Circuit Options crystal/ceramic oscillator External clock source
Package Types 20-pin 24-pin
General bit-programmable pins
Comparator 4-channel mode, 4-bit resolution 3-channel mode, external reference design
KS86C6104/P6104
BLOCK DIAGRAM
RESET
TEST PORT INTERRUPT CONTROL
XOUT
PORT COMPARATOR
P1.0/CIN0/SCLK P1.1/CIN1/SDAT P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 P1.6/INT1 P1.7/INT
BASIC TIMER
SAM87RI
PORT
P0.0/INT0 P0.1/INT0 P0.2/INT0
TIMER
4-KB
208-BYTE REGISTER
D3.3Vout
Figure 1-1. Block Diagram
KS86C6104/P6104
ASSIGNMENTS
Xout TEST P0.0/INT0 P0.1/INT0
RESET
P1.0/CIN0 P1.1/CIN1 P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3Vout
KS86C6104
(TOP VIEW)
P0.2/INT0 P1.7/INT1 P1.6/INT
Figure 1-2. Assignment Diagram (20-Pin Package)
KS86C6104/P6104
Xout TEST P0.0/INT0 P0.1/INT0
RESET
P1.0/CIN0 P1.1/CIN1 P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3V
KS86C6104
(TOP VIEW)
P0.2/INT0 P1.7/INT1 P1.6/INT
Figure 1-3. Assignment Diagram (24-Pin Package)
KS86C6104/P6104
DESCRIPTIONS
Table 1-1. KS86C6104/P6104 Descriptions Names P0.0-P0.2 Type Description Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors individually assignable input pins software automatically disable output pins. Port0 individually configured external interrupt inputs. Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors individually assignable input pins software. Port1.0-1.3 configured comparator input Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors individually assignable input pins software automatically disabled output pins. Port1.4-1.7 individually configured external interrupt inputs. Only used tranceive/receive port. Internal regulator output referencing voltage System clock input output (crystal/ceramic oscillator, external clock source) External interrupt bit-programmable port0. External interrupt bit-programmable portRESET signal input pin.
Circuit Number
Numbers
Share Pins INT0
P1.0-P1.3
19-16
CIN0- CIN3
P1.4-P1.7
D+/D3.3VOUT XIN, XOUT
12-11
INT0 INTRESET
Port0 Port1
TEST
Test signal input (for factory only; must connected VSS) Power input ground power core.
KS86C6104/P6104
CIRCUITS
Table 1-2. Circuit Assignments KS86C6104/P6104 Circuit Number Circuit Type Port0, Port1.4-1.7, INT0, INT1 Port1.0-1.3 KS86C6104/P6104 Assignments
NOTE: Diagrams circuit types C-D, presented below.
DATA
PULL-UP ENABLE DATA CIRCUIT TYPE
OUTPUT DISABLE
OUTPUT DISABLE
IN/OUT
Figure 1-4. Circuit Type
Figure 1-5. Circuit Type
KS86C6104/P6104
PULL-UP ENABLE DATA OUTPUT DISABLE CIRCUIT TYPE IN/OUT
ANALOG/ EXTERNAL VREF INPUT
Figure 1-6. Circuit Type
KS86C6104/P6104
Right Button
KS86P6104
CON_B XOUT P0.0/INT0
Button
Left Button Button
V3.3 Cable
RESET
P0.1/INT0
P1.7/INT
P1.2/CIN2 P1.3/CIN3 P1.1/CIN1 P0.2/INT0 P1.0/CIN0
Figure 1-7. Mouse Circuit Diagram
Array
KS86C6104/P6104
NOTES
1-10
KS86C6104/P6104
ADDRESS SPACES
OVERVIEW
ADDRESS SPACES
KS86C6104/P6104 microcontroller kinds address space: Program memory (ROM) Internal register file 13-bit address supports both program memory. Special instructions related internal logic determine when 13-bit carries addresses program memory. separate 8-bit register carries addresses data between internal register file. KS86C6104 bytes mask-programmable program memory on-chip. KS86C6104/P6104 microcontroller bytes general-purpose registers internal register file. Forty-eight bytes register file mapped system peripheral control functions.
ADDRESS SPACES
KS86C6104/P6104
PROGRAM MEMORY (ROM)
NORMAL OPERATING MODE (INTERNAL ROM) KS86C6104/P6104 bytes (locations 0H-0FFFH) internal mask-programmable program memory. first bytes (0000H-0001H) interrupt vector address. program reset address 0100H.
4,096 4-KBYTE INTERNAL PROGRAM MEMORY AREA Program start
1000H
0100H 0002H 0001H 0000H
Interrupt vector
Figure 2-1. Program Memory Address Space
KS86C6104/P6104
ADDRESS SPACES
REGISTER ARCHITECTURE
upper bytes KS86C6104/P6104's internal register file addressed working registers, system control registers peripheral control registers. lower bytes internal register file (00H-BFH) called general purpose register space. many SAM87RI microcontrollers, addressable area internal register file further expanded additional more register pages general purpose register space (00H-BFH). This register file expansion implemented KS86C6104/P6104.
PERIPHERAL CONTROL REGISTERS BYTES COMMON AREA
SYSTEM CONTROL REGISTERS WORKING REGISTERS
BYTES
GENERAL PURPOSE REGISTER FILE STACK AREA
Figure 2-2. Internal Register File Organization
ADDRESS SPACES
KS86C6104/P6104
COMMON WORKING REGISTER AREA (C0H-CFH)
SAM87Ri register architecture provides efficient method working register addressing that takes full advantage shorter instruction formats reduce execution time. This16-byte address range called common area. That locations this area used working registers operations that address location page register file. Typically, these working registers serve temporary buffers data operations between different pages. However, because KS86C6104/P6104 uses only page common area internal data operation. Register addressing mode used access this area Registers addressed either single 8-bit register paired 16-bit register. 16-bit register pairs, address first 8-bit register always even number address next register number. most significant byte 16-bit data always stored even-numbered register; least significant byte always stored next odd-numbered register.
EVEN ADDRESS
Figure 2-3. 16-Bit Register Pairs
PROGRAMMING Addressing Common Working Register Area
following examples show, should access working registers common area, locations C0H-CFH, using working register addressing mode only. Examples: 0C2H,40H R2,40H 0C3H,#45H Invalid addressing mode! (C2H) value location Invalid addressing mode! (C3H)
working register addressing instead:
working register addressing instead: R3,#45H
KS86C6104/P6104
ADDRESS SPACES
SYSTEM STACK
KS86-series microcontrollers system stack subroutine calls returns store data. PUSH instructions used control system stack operations. KS86C6104/P6104 architecture supports stack operations internal register file. STACK OPERATIONS Return addresses procedure calls interrupts data stored stack. contents saved stack CALL instruction restored instruction. When interrupt occurs, contents FLAGS register pushed stack. IRET instruction then pops these values back their original locations. stack address always decremented before push operation incremented after operation. stack pointer (SP) always points stack frame stored stack, shown Figure 2-4.
HIGH ADDRESS
STACK STACK FLAGS STACK CONTENTS AFTER INTERRUPT
STACK CONTENTS AFTER CALL INSTRUCTION
ADDRESS
Figure 2-4. Stack Operations
STACK POINTER (SP) Register location contains 8-bit stack pointer (SP) that used system stack operations. After reset, value undetermined. Because only internal memory space implemented KS86C6104/P6104, must initialized 8-bit value range 00H-BFH. NOTE case Stack Pointer initialized 00H, decreased when stack operation starts. This means that Stack Pointer access invalid stack area.
ADDRESS SPACES
KS86C6104/P6104
PROGRAMMING Standard Stack Operations Using PUSH
following example shows perform stack operations internal register file using PUSH instructions:
SP,#0C0H
(Normally, 0C0H initialization routine)
PUSH PUSH PUSH PUSH
CCON
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH
CCON
CCON
Stack address 0BCH Stack address 0BDH CCON Stack address 0BEH Stack address 0BFH
KS86C6104/P6104
ADDRESSING MODES
OVERVIEW
ADDRESSING MODES
Instructions that stored program memory fetched execution using program counter. Instructions indicate operation performed data operated Addressing mode method used determine location data operand. operands specified SAM87RI instructions condition codes, immediate data, location register file, program memory, data memory. SAM87RI instruction supports explicit addressing modes. these addressing modes available each instruction. addressing modes their symbols follows: Register Indirect Register (IR) Indexed Direct Address (DA) Relative Address (RA) Immediate (IM)
ADDRESSING MODES
KS86C6104/P6104
REGISTER ADDRESSING MODE Register addressing mode, operand content specified register (see Figure 3-1). Working register addressing differs from Register addressing because uses 16-byte working register space register file 4-bit register within that space (see Figure 3-2).
PROGRAM MEMORY 8-BIT REGISTER FILE ADDRESS ONE-OPERAND INSTRUCTION (EXAMPLE) OPCODE POINTS REGISTER REGISTER FILE
REGISTER FILE
OPERAND
VALUE USED INSTRUCTION EXECUTION
SAMPLE INSTRUCTION: CNTR Where CNTR label 8-bit register address
Figure 3-1. Register Addressing
REGISTER FILE
PROGRAM MEMORY 4-BIT WORKING REGISTER TWOOPERAND INSTRUCTION (EXAMPLE)
LSBs POINTS WORKING REGISTER OPCODE
OPERAND
SAMPLE INSTRUCTION: R1,R2 Where R1=C1H R2=C2H
Figure 3-2. Working Register Addressing
KS86C6104/P6104
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) Indirect Register (IR) addressing mode, content specified register register pair address operand. Depending instruction used, actual address point register register file, program memory (ROM), external memory space (see Figures through 3-6). 8-bit register indirectly address another register. 16-bit register pair used indirectly address another memory location.
PROGRAM MEMORY 8-BIT REGISTER FILE ADDRESS ONE-OPERAND INSTRUCTION (EXAMPLE) OPCODE POINTS REGISTER REGISTER FILE ADDRESS OPERAND USED INSTRUCTION VALUE USED INSTRUCTION EXECUTION SAMPLE INSTRUCTION: @SHIFT
REGISTER FILE
ADDRESS
OPERAND
Where SHIFT label 8-bit register address
Figure 3-3. Indirect Register Addressing Register File
ADDRESSING MODES
KS86C6104/P6104
INDIRECT REGISTER ADDRESSING MODE (Continued)
REGISTER FILE
PROGRAM MEMORY REGISTER EXAMPLE INSTRUCTION REFERENCES PROGRAM MEMORY OPCODE POINTS REGISTER PAIR 16-BIT ADDRESS POINTS PROGRAM MEMORY PAIR
PROGRAM MEMORY SAMPLE INSTRUCTIONS: CALL @RR2 @RR2 VALUE USED INSTRUCTION OPERAND
Figure 3-4. Indirect Register Addressing Program Memory
KS86C6104/P6104
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
REGISTER FILE
PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS
LSBs OPERAND POINTS WORKING REGISTER
OPCODE
SAMPLE INSTRUCTION: R6,@R2 VALUE USED INSTRUCTION OPERAND
Figure 3-5. Indirect Working Register Addressing Register File
ADDRESSING MODES
KS86C6104/P6104
INDIRECT REGISTER ADDRESSING MODE (Concluded)
REGISTER FILE
PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS EXAMPLE INSTRUCTION REFERENCES EITHER PROGRAM MEMORY DATA MEMORY
NEXT BITS POINT WORKING REGISTER PAIR REGISTER PAIR 16-BIT ADDRESS POINTS PROGRAM MEMORY DATA MEMORY
OPCODE
SELECTS
PROGRAM MEMORY DATA MEMORY
VALUE USED INSTRUCTION
OPERAND
SAMPLE INSTRUCTIONS: R5,@RR2 R3,@RR14 @RR4,R8 Program memory access External data memory access External data memory access
Figure 3-6. Indirect Working Register Addressing Program Data Memory
KS86C6104/P6104
ADDRESSING MODES
INDEXED ADDRESSING MODE Indexed addressing mode adds offset value base address during instruction execution order calculate effective operand address (see Figure 3-7). Indexed addressing mode access locations internal register file external memory. short offset Indexed addressing mode, 8-bit displacement treated signed integer range -128 +127. This applies external memory accesses only (see Figure 3-8). register file addressing, 8-bit base address provided instruction added 8-bit offset contained working register. external memory accesses, base address stored working register pair designated instruction. 8-bit 16-bit offset given instruction then added base address (see Figure 3-9). only instruction that supports Indexed addressing mode internal register file Load instruction (LD). instructions support Indexed addressing mode internal program memory, external program memory, external data memory, when implemented.
REGISTER FILE
VALUE USED INSTRUCTION OPERAND
PROGRAM MEMORY X(OFFSET) TWOOPERAND INSTRUCTION EXAMPLE OPCODE LSBs POINTS WORKING REGISTERS
INDEX
SAMPLE INSTRUCTION: R0,#BASE[R1] Where BASE 8-bit immediate value
Figure 3-7. Indexed Addressing Register File
ADDRESSING MODES
KS86C6104/P6104
INDEXED ADDRESSING MODE (Continued)
REGISTER FILE PROGRAM MEMORY 4-BIT WORKING REGISTER ADDRESS XS(OFFSET) OPCODE NEXT BITS POINT WORKING REGISTER PAIR REGISTER PAIR 16-BIT ADDRESS ADDED OFFSET
SELECTS
BITS BITS PROGRAM MEMORY DATA MEMORY
BITS
OPERAND
VALUE USED INSTRUCTION
SAMPLE INSTRUCTIONS: R4,#04H[RR2] values program address (RR2 #04H) loaded into register Identical operation example, except that external program memory accessed.
R4,#04H[RR2]
Figure 3-8. Indexed Addressing Program Data Memory with Short Offset
KS86C6104/P6104
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
PROGRAM MEMORY (OFFSET) 4-BIT WORKING REGISTER ADDRESS XLL(OFFSET) NEXT BITS POINT WORKING REGISTER PAIR
REGISTER FILE
REGISTER PAIR 16-BIT ADDRESS ADDED OFFSET
OPCODE
SELECTS
BITS BITS PROGRAM MEMORY DATA MEMORY VALUE USED INSTRUCTION
BITS
OPERAND
SAMPLE INSTRUCTIONS: R4,#1000H[RR2] values program address (RR2 #1000H) loaded into register Identical operation example, except that external program memory accessed.
R4,#1000H[RR2]
Figure 3-9. Indexed Addressing Program Data Memory with Long Offset
ADDRESSING MODES
KS86C6104/P6104
DIRECT ADDRESS MODE (DA) Direct Address (DA) mode, instruction provides operand's 16-bit memory address. Jump (JP) Call (CALL) instructions this addressing mode specify 16-bit destination address that loaded into whenever CALL instruction executed. instructions Direct Address mode specify source destination address Load operations program memory (LDC) external data memory (LDE), implemented.
PROGRAM DATA MEMORY
PROGRAM MEMORY
MEMORY ADDRESS USED
UPPER ADDR BYTE LOWER ADDR BYTE SELECTS PROGRAM MEMORY DATA MEMORY: PROGRAM MEMORY DATA MEMORY
OPCODE
SAMPLE INSTRUCTIONS: R5,1234H values program address (1234H) loaded into register Identical operation example, except that external program memory accessed.
R5,1234H
Figure 3-10. Direct Addressing Load Instructions
3-10
KS86C6104/P6104
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
PROGRAM MEMORY
NEXT OPCODE
PROGRAM MEMORY ADDRESS USED LOWER ADDR BYTE UPPER ADDR BYTE OPCODE
SAMPLE INSTRUCTIONS: CALL C,JOB1 DISPLAY Where JOB1 16-bit immediate address Where DISPLAY 16-bit immediate address
Figure 3-11. Direct Addressing Call Jump Instructions
ADDRESSING MODES
KS86C6104/P6104
RELATIVE ADDRESS MODE (RA) Relative Address (RA) mode, two's-complement signed displacement between specified instruction. displacement value then added current value. result address next instruction executed. Before this addition occurs, contains address instruction immediately following current instruction. instructions that support addressing
PROGRAM MEMORY
NEXT OPCODE
PROGRAM MEMORY ADDRESS USED
CURRENT VALUE DISPLACEMENT CURRENT INSTRUCTION OPCODE SIGNED DISPLACEMENT VALUE
SAMPLE INSTRUCTION: ULT,$+OFFSET Where OFFSET value range +127 -128
Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) Immediate (IM) addressing mode, operand value used instruction value supplied operand field itself. Immediate addressing mode useful loading constant values into registers.
PROGRAM MEMORY
OPERAND OPCODE
(THE OPERAND VALUE INSTRUCTION) SAMPLE INSTRUCTION: R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
KS86C6104/P6104
CONTROL REGISTERS
OVERVIEW
CONTROL REGISTERS
this section, detailed descriptions KS86C6104/P6104 control registers presented easy-to-read format. These descriptions will help familiarize with mapped locations register file. also them quick-reference source when writing application programs. System peripheral registers summarized Table 4-1. Figure illustrates important features standard register description format. Control register descriptions arranged alphabetical order according register mnemonic. More information about control registers presented context various peripheral hardware descriptions Part this manual.
CONTROL REGISTERS
KS86C6104/P6104
Table 4-1. System Peripheral Control Registers Register Name Timer counter register Timer data register Timer control register Clock control register System flags register Stack pointer Basic timer control register Basic timer counter System mode register Port data register Port data register Comparison result register Port control register Comparator control mode register Port control register (high nibble) Port control register (low nibble) Port interrupt control register Port interrupt pending register Port interrupt control register Port interrupt pending register function address register Control endpoint status register Interrupt endpoint status register Control endpoint byte count register Control endpoint FIFO register Interrupt endpoint FIFO register interrupt pending register interrupt enable register power management register reset register Mnemonic T0CNT T0DATA T0CON Location mapped. CLKCON FLAGS Locations D6H-D8H mapped. Locations DAH-DBH mapped. BTCON BTCNT Location mapped. Locations E2H-E4H mapped. CDATA P0CON CCON P1CONH P1CONL P0INT P0PND P1INT P1PND Locations EEH-EFH mapped. FADDR EP0CSR EP1CSR EP0BCNT EP0FIFO EP1FIFO USBPND USBINT PWRMGR Locations F9H-FEH mapped. USBRST
KS86C6104/P6104
CONTROL REGISTERS
number(s) that is/are appended register name addressing Register mnemonic Full register name
Name individual function Register address (hexadecimal)
FLAGS System Flags Register
Identifier
RESET
Value
Read/Write
Carry Flag Operation does generate carry borrow condition Operation generates carry-out borrow into high-order Zero Flag Operation result non-zero value Operation result zero Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
R/W=
Read-only Write-only Read/write used
Description effect specific settings
RESET value notation:
number:
Addressing mode modes modify register values
used Undetermined value Logic zero Logic
Figure 4-1. Register Description Format
CONTROL REGISTERS
KS86C6104/P6104
BTCON Basic Timer Control Register
Identifier
RESET Value
Read/Write
Watchdog Timer Enable Bits Disable watchdog function Enable watchdog function other value
Basic Timer Input Clock Selection Bits OSC/4096 OSC/1024 OSC/128 Invalid setting
Basic Timer Counter Clear (note) effect Clear BTCNT
Basic Timer Divider Clear (note) effect Clear both dividers
NOTE: When write BTCON.0 BTCON.1), basic timer counter basic timer divider) cleared. then cleared automatically "0".
KS86C6104/P6104
CONTROL REGISTERS
CCON Comparator Mode Register
Identifier
RESET Value
Read/Write
Comparator Enable Disable comparator Enable comparator
Conversion Time Conversion time 27/fx) Conversion time 24/fx)
External Reference Voltage Internal reference voltage External reference voltage
Always logic zero Reference voltage (Vref) selection 0.7)/16,
CONTROL REGISTERS
KS86C6104/P6104
CLKCON System Clock Control Register
Identifier
RESET Value
Read/Write
Oscillator Wake-up Function Enable main system oscillator wake-up power down mode Disable main system oscillator wake-up power down mode
used KS86C6104/P6104 Clock (System Clock) Selection Bits Divide (fOSC/16) Divide (fOSC/8) Divide (fOSC/2) Non-divided clock (fOSC)
used KS86C6104/P6104
KS86C6104/P6104
CONTROL REGISTERS
EP0CSR Control Endpoint Status Register
Identifier
RESET Value
Read/Write
SETUP_END Clear effect (when write) Clear SETUP_END (bit4)
OUT_PKT_RDY Clear effect (when write) Clear OUT_PKT_RDY (bit0)
STALL Signal Sending effect (when write) Send STALL signal host
Setup Transfer effect (when write) sets this when control transfer ends before DATA_END (bit3)
Setup Data effect (when write) this after loading unloading last packet data into FIFO
STALL Signal Receive clear this STALL condition sets this control transaction ended protocol violation
Packet Ready clear this once packet been successfully sent host sets this after writing packet data into Endpoint0 FIFO
Packet Ready effect (when write) sets this once valid token written FIFO
CONTROL REGISTERS
KS86C6104/P6104
EP1CSR Interrupt Endpoint Status Register
Identifier
RESET Value
Read/Write
DATA_TOGGLE Clear effect (when write) Clears data toggle sequence
Maximum Packet Size Bits effect (when write) Indicates maximum packet size interrupt endpoint
FIFO Flush effect (when write) FIFO flushed, IN_PKT_RDY cleared
Force STALL clears this STALL condition Issues STALL handshake
Packet Ready clear this once packet been successfully sent host sets this after writing packet data into Endpoint1 FIFO
KS86C6104/P6104
CONTROL REGISTERS
FLAGS System Flags Register
Identifier
RESET Value
Read/Write
Carry Flag Operation does generate carry borrow condition
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Overflow Flag Operation result +127 -128 Operation result +127 -128
used KS86C6104/P6104
CONTROL REGISTERS
KS86C6104/P6104
P0CON Port Control Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 Port P0.2 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up resistor Output mode, push-pull used
Port P0.1 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up resistor Outmode, push-pull used
Port P0.0 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up resistor Output mode, push-pull used
4-10
KS86C6104/P6104
CONTROL REGISTERS
P0INT Port Interrupt Control Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 P0.2 Interrupt Enable Bits External interrupt disable External interrupt enable
P0.1 Interrupt Enable Bits External interrupt disable External interrupt enable
P0.0 Interrupt Enable Bits External interrupt disable External interrupt enable
CONTROL REGISTERS
KS86C6104/P6104
P0PND Port Interrupt Pending Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 P0.2 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.1 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P0.0 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-12
KS86C6104/P6104
CONTROL REGISTERS
P1CONH Port Control Register (High Byte)
Identifier
RESET Value
Read/Write
Port P1.7 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up register Output mode, push-pull used
Port P1.6 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up register Output mode, push-pull used
Port P1.5 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up register Output mode, push-pull used
Port P1.4 Configuration Bits Input, rising edge external interrupt Input, falling edge external interrupt with pull-up register Output mode, push-pull used
4-13
CONTROL REGISTERS
KS86C6104/P6104
P1CONL Port Control Register (Low Byte)
Identifier
RESET Value
Read/Write
Port P1.3 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up resistor Push-pull output mode Comparator input, analog input
Port P1.2 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up resistor Push-pull output mode Comparator input, analog input
Port P1.1 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-up resistor Push-pull output mode Comparator input, analog input
Port P1.0 Configuration Bits Schmitt trigger input Schmitt trigger input with pull-upresistor Push-pull output mode Comparator input, analog input
4-14
KS86C6104/P6104
CONTROL REGISTERS
P1INT Port Interrupt Control Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 P1.7 Interrupt Enable External interrupt disable External interrupt enable
P1.6 Interrupt Enable External interrupt disable External interrupt enable
P1.5 Interrupt Enable External interrupt disable External interrupt enable
P1.4 Interrupt Enable External interrupt disable External interrupt enable
4-15
CONTROL REGISTERS
KS86C6104/P6104
P1PND Port Interrupt Pending Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 P1.7 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P1.6 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P1.5 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
P1.4 Interrupt Pending pending (when read)/clear pending (when write) Pending (when read)/no effect (when write)
4-16
KS86C6104/P6104
CONTROL REGISTERS
PWRMGR Power Management Register
Identifier
RESET Value
Read/Write
Always logic zero RESUME Signal Sending RESUME signal ended While suspend state, wants initiate resume, writes this register 10ms (maximum 15ms), clears this register. suspend mode, this "1", generates resume signaling.
SUSPEND Status Cleared automatically when writes zero RESUME signal sending when function receives resume signal from host while suspend mode This when SUSPEND interrupt occur
4-17
CONTROL REGISTERS
KS86C6104/P6104
System Mode Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 Global Interrupt Enable Disable global interrupt processing Enable global interrupt processing
Page Selection Bits Page Page (not used KS86C6104) Page (not used KS86C6104) Page (not used KS86C6104)
4-18
KS86C6104/P6104
CONTROL REGISTERS
T0CON Timer Control Register
Identifier
RESET Value
Read/Write
Counter Input Clock Selection Bits OSC/4096 OSC/256 OSC/8 used KS86C6104/P6104
Operating Mode Selection Bits Overflow mode (OVF interrupt occur) Interval timer mode (The counter automatically cleared whenever T0DATA value equals T0CNT value) Invalid selection
Counter Clear (T0CLR) effect Clear counter (when write)
Overflow Interrupt Enable (T0OVF) Disable overflow interrupt Enable overflow interrupt
Match Interrupt Enable (T0INT) Disable match interrupt Enable match interrupt
Interrupt Pending (T0PND) interrupt pending (when read)/Clear this pending (when write) Interrupt pending(when read)/No effect(when write)
NOTE: When write T0CON.3, timer counter cleared. then cleared automatically "0".
4-19
CONTROL REGISTERS
KS86C6104/P6104
USBINT Interrupt Enable Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 SUSPEND/RESUME Interrupt Enable Disable SUSPEND RESEME interrupt (default) Enable SUSPEND RESEME interrupt
ENDPOINT1 Interrupt Pending Disable ENDPOINT interrupt Enable ENDPOINT interrupt (default)
ENDPOINT0 Interrupt Pending Disable ENDPOINT interrupt Enable ENDPOINT interrupt (default)
4-20
KS86C6104/P6104
CONTROL REGISTERS
USBPND Interrupt Pending Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 RESUME Interrupt Pending effect (once read, this cleared automatically) This set, RESUME signaling received while SUSPEND mode
SUSPEND Interrupt Pending effect (once read, this cleared automatically) This set, when suspend signaling received
ENDPOINT1 Interrupt Pending effect (once read, this cleared automatically) This set, when endpoint1 needs serviced
ENDPOINT0 Interrupt Pending effect (once read, this cleared automatically) This set, while endpoint needs serviced. under following conditions: OUT_PKT_RDY IN_PKT_RDY cleared SENT_STALL gets DATA_END gets cleared SETUP_END gets
CONTROL REGISTERS
KS86C6104/P6104
USBRST RESET Register
Identifier
RESET Value
Read/Write
used KS86C6104/P6104 Reset Signal Receive Clear reset signal This when host send reset signal
4-22
KS86C6104/P6104
INTERRUPT STRUCTURE
OVERVIEW
INTERRUPT STRUCTURE
SAM87RI interrupt structure basic components: vector, sources. number interrupt sources serviced through interrupt vector which assigned address 0000H-0001H.
VECTOR
SOURCES
0000H 0001H
NOTES: SAM87RI interrupt only vector address (0000H-0001H) number value expandable.
Figure 5-1. KS86-Series Interrupt Type
INTERRUPT PROCESSING CONTROL POINTS Interrupt processing controlled ways: globally, specific interrupt level source. systemlevel control points interrupt structure therefore: Global interrupt enable disable instructions) Interrupt source enable disable settings corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, system mode register, (DFH), used enable disable interrupt processing. SYM.2 enable disable global interrupt processing, which modifying SYM.2. Enable Interrupt (EI) instruction must included initialization routine that follows reset operation order enable interrupt processing. Although manipulate SYM.2 directly enable disable interrupts during normal operation, recommend that instructions this purpose.
INTERRUPT STRUCTURE
KS86C6104/P6104
INTERRUPT PENDING FUNCTION TYPES When interrupt service routine executed, application program's service routine must clear appropriate pending before return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there interrupt priority register SAM87RI, order service determined sequence source which executed interrupt service routine.
"EI" INSTRUCTION EXECUTION
RESET
INTERRUPT PENDING REGISTER
INTERRUPT PRIORITY DETERMINED SOFTWARE POLLING METHOD VECTOR INTERRUPT CYCLE
SOURCE INTERRUPTS SOURCE INTERRUPT ENABLE
GLOBAL INTERRUPT CONTROL (EI, instructions)
Figure 5-2. Interrupt Function Diagram
KS86C6104/P6104
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE interrupt request polling servicing sequence follows: source generates interrupt request setting interrupt request pending "1". generates interrupt acknowledge signal. service routine starts source's pending flag cleared software. Interrupt priority must determined software polling method.
INTERRUPT SERVICE ROUTINES Before interrupt request serviced, following conditions must met: Interrupt processing must enabled (EI, SYM.2 "1") Interrupt must enabled interrupt's source (peripheral control register) above conditions met, interrupt request acknowledged instruction cycle. then initiates interrupt machine cycle that completes following processing sequence: Reset (clear "0") global interrupt enable register (DI, SYM.2 "0") disable subsequent interrupts. Save program counter status flags stack. Branch interrupt vector fetch service routine's address. Pass control interrupt service routine. When interrupt service routine completed, Interrupt Return instruction (IRET) occurs. IRET restores status flags sets SYM.2 "1"(EI), allowing process next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES interrupt vector area contains address interrupt service routine. Vectored interrupt processing follows this sequence: Push program counter's low-byte value stack. Push program counter's high-byte value stack. Push FLAGS register values stack. Fetch service routine's high-byte address from vector address 0000H. Fetch service routine's low-byte address from vector address 0001H. Branch service routine specified 16-bit vector address.
INTERRUPT STRUCTURE
KS86C6104/P6104
KS86C6104/P6104 INTERRUPT STRUCTURE KS86C6104/P6104 microcontroller thirteen peripheral interrupt sources: Timer match interrupt Timer overflow interrupt Suspend interrupt Resume interrupt Endpoint interrupts Endpoint Endpoint Three external interrupts port P0.0-P0.2 Four external interrupts port P1.4-P1.7
Timer Match Interrupt T0CON.0 T0CON.1 Timer Overflow Interrupt T0CON.2 P0PND.0 P0PND.1 P0PND.2 P0.0 Interrupt P0INT.0 P0.1 Interrupt P0INT.1 P0.2 Interrupt P0INT.2 P1.4 Interrupt P1INT.0 P1.5 Interrupt P1INT.1 P1.6 Interrupt P1INT.2 P1.7 Interrupt P1INT.3 Endpoint Interrupt USBINT.0 Endpoint Interrupt USBINT.1 Suspend Interrupt USBINT.2 Resume Interrupt USBINT.2
P1PND.0 P1PND.1 P1PND.2 EI/DI (SYM.2) P1PND.3
Vector (0000H)
USBPND.0 USBPND.1 USBPND.2 USBPND.3
NOTE: Interrupt service priority should managed interrupt service routine.
Figure 5-3. KS86C6104/P6104 Interrupt Structure
KS86C6104/P6104
CLOCK CIRCUIT
OVERVIEW
CLOCK CIRCUIT
KS86C6104/P6104 oscillation circuit options, crystal/ceramic oscillation external clock source. crystal ceramic oscillation source provides maximum clock. XOUT pins connect oscillation source on-chip clock circuit. External clock crystal/ceramic oscillator circuits shown Figures 7-2.
KS86C6104 XOUT XOUT
KS86C6104
Figure 7-1. External Oscillator MAIN OSCILLATOR LOGIC
Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator)
increase processing speed reduce clock noise, non-divided logic implemented main oscillator circuit. this reason, very high resolution waveforms (square signal edges) must generated order efficiently process logic operations. CLOCK STATUS DURING POWER-DOWN MODES power-down modes, Stop mode Idle mode, affect clock oscillation follows: Stop mode, main oscillator "freezes," halting peripherals. contents register file current system register values retained. RESET operation releases Stop mode, starts oscillator. Idle mode, internal clock signal gated CPU, interrupt control timer. current status preserved, including stack pointer, program counter, flags. Data register file retained. Idle mode released RESET interrupt (external internally-generated).
CLOCK CIRCUIT
KS86C6104/P6104
SYSTEM CLOCK CONTROL REGISTER (CLKCON) system clock control register, CLKCON, located location D4H. read/write addressable following functions: Oscillator wake-up function enable/disable (CLKCON.7) Oscillator frequency divide-by value: non-divided, (CLKCON.4 CLKCON.3) CLKCON register controls whether external interrupt used trigger Stop mode release (This called "IRQ wake-up" function). wake-up enable CLKCON.7. After RESET, external interrupt oscillator wake-up function enabled, main oscillator activated, fOSC/16 (the slowest clock speed) selected clock. necessary, then increase clock speed fOSC, fOSC/2 fOSC/8.
SYSTEM CLOCK CONTROL REGISTER (CLKCON) D4H,
Oscillator wake-up enable bit: Enable main system oscillator wake-up function Disable main system oscillator wake-up function effect
effect Divide-by selection bits clock frequency: fOSC/16 fOSC/8 fOSC/2 fOSC (non-divided)
Figure 7-3. System Clock Control Register (CLKCON)
KS86C6104/P6104
CLOCK CIRCUIT
STOP Instruction CLKCON.4,
Oscillator Stop MAIN Oscillator Wake-up NOISE FILTER 1/16 CLOCK
CLKCON.7
Figure 7-4. System Clock Circuit Diagram
CLOCK CIRCUIT
KS86C6104/P6104
NOTES
KS86C6104/P6104
RESET POWER-DOWN
OVERVIEW
RESET POWER-DOWN
SYSTEM RESET
During power-on reset, voltage High level RESET forced level. RESET signal input through filter circuit where then synchronized with clock. This brings KS86C6104/P6104 into known operating status. RESET must held level minimum time interval after power supply comes within tolerance order allow time internal clock oscillation stabilize. minimum required oscillation stabilization time reset approximately 10ms 216/f OSC, fOSC MHz). When reset occurs during normal operation (with both RESET High level), signal RESET forced reset operation starts. system peripheral control registers then their default hardware reset values (see Table 8-1). following sequence events occur during reset operation: interrupts disabled. watchdog function (basic timer) enabled. Ports Schmitt trigger input mode pull-up resistors disabled. Peripheral control data registers disabled reset their initial values. program counter loaded with reset address, 0100H. When programmed oscillation stabilization time interval elapsed, address stored location 0100H (and 0101H) fetched executed. NOTE program duration oscillation stabilization interval, must make appropriate settings basic timer control register, BTCON, before entering Stop mode. Also, want basic timer watchdog function (which causes system reset basic timer counter overflow occurs), disable writing '1010B' upper nibble BTCON.
RESET POWER-DOWN
KS86C6104/P6104
POWER-DOWN MODES
STOP MODE Stop mode invoked instruction STOP (opcode 7FH). Stop mode, operation peripherals halted. That on-chip main oscillator stops supply current reduced less than system functions halted when clock "freezes," data stored internal register file retained. Stop mode released ways: RESET signal external interrupt. Using RESET Release Stop Mode Stop mode released when RESET signal released returns High level. system peripheral control registers then reset their default values contents data registers retained. RESET operation automatically selects slow clock (1/16) because CLKCON.3 CLKCON.4 cleared '00B'. After oscillation stabilization interval elapsed, executes system initialization routine fetching 16-bit address stored locations 0100H 0101H. Using External Interrupt Release Stop Mode Only external interrupts with RC-delay noise filter circuit used release Stop mode (Clock-related external interrupts cannot used). External interrupts KS86C6104/P6104 interrupt structure does meet this criteria. Note that when Stop mode released external interrupt, current values system peripheral control registers changed. When interrupt release Stop mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. external interrupt Stop mode release, also program duration oscillation stabilization interval. this, must make appropriate control clock settings before entering Stop mode. external interrupt serviced when Stop mode release occurs. Following IRET from service routine, instruction immediately following that initiated Stop mode executed. NOTE STOP mode when external clock source being used oscillation circuit option. IDLE MODE Idle mode invoked instruction IDLE (opcode 6FH). Idle mode, operations halted while select peripherals remain active. During Idle mode, internal clock signal gated CPU, interrupt logic timer/counters. Port pins retain mode (input output) they time Idle mode entered. There ways release Idle mode: Execute RESET. system peripheral control registers reset their default values contents data registers retained. reset automatically selects slow clock (1/16) because CLKCON.3 CLKCON.4 cleared '00B'. interrupts masked, RESET only release Idle mode. Activate enabled interrupt, causing Idle mode released. When interrupt release Idle mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. interrupt then serviced. Following IRET from service routine, instruction immediately following that initiated Idle mode executed. NOTE Only external interrupts that clock-related used release Stop mode. release Idle mode, however, type interrupt (that internal external) used.
KS86C6104/P6104
RESET POWER-DOWN
HARDWARE RESET VALUES
Tables through list values system registers, peripheral control registers, peripheral data registers following reset operation normal operating mode. following notation used these tables represent specific reset values: shows RESET value logic logic zero, respectively. means that value undefined following RESET. dash ('-') means that either used mapped.
Table 8-1. Register Values after RESET Register Name General purpose registers(page Working registers Timer counter Timer data register Timer control register Clock control register System flags register Stack pointer Basic timer control register Basic timer counter System mode register Port data register Port data register Mnemonic T0CNT T0DATA T0CON CLKCON FLAGS BTCON BTCNT Address 00H-7FH C0H-CFH Values After RESET
Location mapped.
Locations mapped. Locations mapped.
Location mapped.
Locations mapped.
NOTE: timer counter, T0CNT, basic timer counter, BTCNT, comparison result, CDATA, read-only. other registers read/write addressable.
RESET POWER-DOWN
KS86C6104/P6104
Table 8-1. Register Values after RESET (continued) Bank Register Name Comparison result register Port control register Comparator control mode register Port control register (high nibble) Port control register (low nibble) Port interrupt control register Port interrupt pending register Port 1interrupt control register Port interrupt pending register function address register Control Endpoint status register Interrupt Endpoint status register Control Endpoint byte count register Control Endpoint FIFO register Interrupt Endpoint FIFO register interrupt pending register interrupt enable register power management register reset register Mnemonic CDATA P0CON CCON P1CONH P1CONL P0INT P0PND P1INT P1PND FADDR EP0CSR EP1CSR EP0BCNT EP0FIFO EP1FIFO USBPND USBINT PWRMGR USBRST Address Values After RESET
Locations -EFH mapped.
Locations mapped.
KS86C6104/P6104
PORTS
OVERVIEW
Port
PORTS
KS86C6104/P6104 ports (Port Port pins total. access these ports directly writing reading port data register addresses. mouse applications, ports 1.0-1.3 usually configured mouse sensing input. Port used button data input. Table 9-1. KS86C6104/P6104 Port Configuration Overview Function Description Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors individually assignable input pins software. Port0 also configured external interrupt inputs. Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors individually assignable input pins software and, they automatically disabled output pins. Port1.0-Port1.3 configured comparator input. Port1.4-Port1.7 individually configured external interrupt inputs. Programmability
PORTS
KS86C6104/P6104
PORT DATA REGISTERS Table gives overview port data register names, locations, addressing characteristics. Data registers ports have structure shown Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port data register Port data register Mnemonic
PORT DATA REGISTER 0-1)
P1.7
P1.6
P1.5
P1.4
P1.3
Pn.2
Pn.0
Figure 9-1. Port Data Register Format
KS86C6104/P6104
PORTS
PORT PORT Ports 1are bit-programmable, general-purpose, ports. select Schmitt trigger input mode push-pull output mode. Port1.0 Port1.3 configured comparator input. access ports directly writing reading corresponding port data registers (E0H) (E1H). RESET clears port control registers P0CON, P1CONH, P1CONL '00H', configuring port port pins Schmitt trigger inputs.
PORT CONTROL REGISTERS P0CON, E6H,
P0CON: 5,3,1 4,2,0
P0.2
P0.0
Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge external interrupt with pull-up resistor. Push-pull output mode. used.
Figure 9-2. Port Control Registers (P0CON)
PORTS
KS86C6104/P6104
PORT CONTROL REGISTERS P1CONH, E8H, R/W, P1CONL, E9H,
P1CONH: P1CONL: 7,5,3,1 6,4,2,0
P1.7 P1.3
P1.6 P1.2
P1.5
P1.4 P1.0
Port Mode Selection Schmitt trigger input, rising edge external interrupt. Schmitt trigger input, falling edge external interrupt with pull-up resistor. Push-pull output mode. Comparator input (not used P1CONH).
Figure 9-3. Port Control Registers (P1CONH, P1CONL)
PROGRAMMING Configuring KS86C6104/P6104 Port Pins Specification
This example shows configure ports specification. programming parameters follows: Examples: port push-pull output mode P0CON,#0AAH P0.0-P0.3 Push-pull output port 1.4-port schmitt trigger input mode P1CONH,#00H P1.4-P1.7 Schmitt trigger input port 1.0-port comparator input mode P1CONL,#0FFH P1.0-P1.3 Comparator input
KS86C6104/P6104
BASIC TIMER TIMER
Basic Timer (BT)
BASIC TIMER TIMER
MODULE OVERVIEW
KS86C6104/P6104 default timers: 8-bit basic timer 8-bit general-purpose timer/counter. 8-bit timer/counter called timer
basic timer (BT) different ways: watchdog timer provide automatic reset mechanism event system malfunction. signal required oscillation stabilization interval after reset Stop mode release. functional components basic timer block are: Clock frequency divider (fOSC divided 4096, 1024, 128) with multiplexer 8-bit basic timer counter, BTCNT (DDH, read-only) Basic timer control register, BTCON (DCH, read/write) Timer Timer operating modes, which select appropriate T0CON setting: Interval timer mode Overflow mode Timer following functional components: Clock frequency divider (fOSC divided 4096, 256, with multiplexer 8-bit counter (T0CNT), 8-bit comparator, 8-bit reference data register (T0DATA) Timer overflow interrupt (T0OVF) match interrupt (T0INT) generation Timer control register, T0CON
BASIC TIMER TIMER
KS86C6104/P6104
BASIC TIMER CONTROL REGISTER (BTCON) basic timer control register, BTCON, used select input clock frequency, clear basic timer counter frequency dividers, enable disable watchdog timer function. reset clears BTCON '00H'. This enables watchdog function selects basic timer clock frequency OSC/4096. disable watchdog function, must write signature code '1010B' basic timer register control bits BTCON.7-BTCON.4. 8-bit basic timer counter, BTCNT, cleared time during normal operation writing BTCON.1. clear frequency dividers both basic timer input clock timer clock, write BTCON.0.
BASIC TIMER CONTROL REGISTER (BTCON) DCH,
Watchdog timer enable bits: 1010B Disable watchdog function Other value Enable watchdog function
Divider clear basic timer timer effect Clear both dividers Basic timer counter clear bit: effect Clear BTCNT
Basic timer input clock selection bits: /4096 /1024 /128 Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
KS86C6104/P6104
BASIC TIMER TIMER
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function program basic timer overflow signal generate reset setting BTCON.7-BTCON.4 value other than '1010B' (The '1010B' value disables watchdog function). reset clears BTCON '00H', automatically enabling watchdog timer function. reset also selects clock determined current CLKCON register setting) divided 4096 clock. reset whenever basic timer counter overflow occurs. During normal operation, application program must prevent overflow, accompanying reset operation, from occurring. this, BTCNT value must cleared writing BTCON.1) regular intervals. system malfunction occurs circuit noise some other error condition, counter clear operation will executed basic timer overflow will occur, initiating reset. other words, during normal operation, basic timer overflow loop overflow 8-bit basic timer counter, BTCNT) always broken BTCNT clear instruction. malfunction does occur, reset triggered automatically. Oscillation Stabilization Interval Timer Function also basic timer program specific oscillation stabilization interval following reset when Stop mode been released external interrupt. Stop mode, whenever reset external interrupt occurs, oscillator starts. BTCNT value then starts increasing rate fOSC/4096 (for reset), rate preset clock source (for external interrupt). When BTCNT.4 set, signal generated indicate that stabilization interval elapsed gate clock signal that resume normal operation. summary, following events occur when Stop mode released: During Stop mode, power-on reset external interrupt occurs trigger Stop mode release oscillation starts. power-on reset occurred, basic timer counter will increase rate fOSC /4096. external interrupt used release Stop mode, BTCNT value increases rate preset clock source. Clock oscillation stabilization interval begins continues until basic timer counter set. When BTCNT.4 set, normal operation resumes. Figure 10-2 10-3 show oscillation stabilization time RESET STOP mode release, respectively.
10-3
BASIC TIMER TIMER
KS86C6104/P6104
Oscillation stabilization time
Normal operating mode
RESET
Reset Release Voltage trst
Internal Reset Release
Oscillator (Xout) Oscillator stabilization time
BTCNT clock
BTCNT value
10000B 00000B
WAIT (4096 fosc Basic timer increment operations IDLE mode
NOTE: Duration oscillator stabilization wait time, tWAIT, when released Power-on-reset 4096x16/fosc. trst external resister chip capacitor)
Figure 10-2. Oscillation Stabilization Time RESET
10-4
KS86C6104/P6104
BASIC TIMER TIMER
Normal operating mode
STOP mode
Oscillation stabilization time
Normal operating mode
STOP instruction execution External interrupt STOP mode release signal
RESET
STOP release signal Oscillator (Xout) BTCNT clock
10000B
BTCNT value
00000B
WAIT Basic timer increment
NOTE: Duration oscillator stabilization wait time, tWAIT, released interrupt determined setting basic timer control register, BTCON. BTCON.3 BTCON.2 tWAIT (4096 fosc (1024 fosc (128 fosc fosc tWAIT (When fosc MHz) 10.92 0.341 42.6
Figure 10-3. Oscillation Stabilization Time STOP Mode Release
10-5
BASIC TIMER TIMER
KS86C6104/P6104
TIMER CONTROL REGISTER (T0CON) T0CON located address D2H, read/write addressable. reset clears T0CON '00H'. This sets timer normal interval match mode, selects input clock frequency fOSC/4096, disables timer overflow interrupt match interrupt. clear timer counter time during normal operation writing T0CON.3. timer overflow interrupt enabled writing T0CON.1. When timer overflow interrupt occurs serviced CPU, pending condition must cleared software writing timer interrupt pending bit, T0CON.0. enable timer match interrupt, must write T0CON.1 "1". detect interrupt pending condition, application program polls T0CON.0. When detected, timer match/ capture interrupt pending. When interrupt request been serviced, pending condition must cleared software writing timer interrupt pending bit, T0CON.0.
TIMER CONTROL REGISTER (T0CON) D2H,
Timer input clock selection bits: /4096 /256 Invalid selection Timer operating mode selection bits: Interval match mode Invalid selection Invalid selection Overflow mode
Timer interrupt pending bit: interrupt pending Clear pending (when write) Interrupt pending (when read) effect (when write) Timer match interrupt enable bit: Disable match interrupt Enable match interrupt Timer overflow interrupt enable bit: Disable overflow interrupt Enable overflow interrupt Timer counter clear bit: effect Clear timer counter (when write)
Figure 10-4. Timer Control Register (T0CON)
10-6
KS86C6104/P6104
BASIC TIMER TIMER
TIMER FUNCTION DESCRIPTION Interval Match Mode interval match mode, match signal generated when counter value identical value written reference data register, T0DATA. match signal generates timer match interrupt then clears counter. example, write value '10H' T0DATA, counter will increment until reaches '10H'. this point, match interrupt generated, counter value reset counting resumes. Overflow Mode overflow mode, overflow signal generated regardless value written reference data register when counter value overflowed. overflow signal generates timer overflow interrupt then counter cleared.
T0OVF Data T0PND T0INT
Counter
Comparator
Match
T0DATA Buffer Register When 8-Bit counter cleared, this buffer open T0DATA Data
Figure 10-5. Simplified Timer Function Diagram: Interval Timer Mode
10-7
BASIC TIMER TIMER
KS86C6104/P6104
RESET
STOP 1/4096
Write '1010xxxxB' disable. Data 8-Bit Basic Counter (BTCNT Read-Only)
RESET
Bits
1/1024 1/128
When BTCNT.4 after releasing from RESET STOP mode, clock starts. Bits
Bits Data 1/4096 1/256 8-Bit Counter (T0CNT Read-Only) Overflow
OVINT
T0CLR T0INT Match Signal Match/ Overflow
8-Bit Comparator
Bits T0DATA Buffer Register
When 8-Bit counter cleared, this buffer open T0DATA Data
Basic Timer Control Register
Timer Control Register
Figure 10-6. Basic Timer Timer Block Diagram
10-8
KS86C6104/P6104
UNIVERSAL SERIAL
1OVERVIEW
UNIVERSAL SERIAL
Universal Serial (USB) communication architecture that supports data transfer between host computer wide range peripherals. actually cable which peripherals share bandwidth through host scheduled token based protocol. module KS86C6104/P6104 designed serve speed transfer rate (1.5 Mbs) device described Universal Serial Specification Revision 1.0. KS86C6104/P6104 briefly describe microcontroller with 87Ri core with on-chip peripheral seen figure 11-1. KS86C6104/P6104 comes equipped with Serial Interface Engine (SIE), which handles communication protocol USB. KS86C6104/P6104 supports following control logic: packet decoding/generation, generation/checking, NRZI encoding/decoding, Sync detection, (end packet) detection stuffing. KS86C6104/P6104 supports types data transfers; control interrupt. endpoints used this device; Endpoint Endpoint Please refer specification revision detail description USB.
Transceiver
Voltage Regulator
SAM87RI CORE
(Serial Interface Engine)
Endpoint0 FIFO Endpoint1 FIFO
Data
Figure 11-1. Peripheral Interface
UNIVERSAL SERIAL
KS86C6104/P6104
Serial Interface Engine (SIE) Serial Interface Engine interfaces serial data handles, deserialization/serialization data, NRZI encoding/decoding, clock extraction, generation checking, stuffing other specifications pertaining protocol such handling inter packet time decoding. Control Logic control logic manages data movements between transceiver manipulating transceiver endpoint register. This includes both transmit receive operations USB. logic contains byte count buffers transmit operations that load active transmit endpoint's byte count this determine number bytes transfer. same buffer used receive transactions count number bytes received transfer that number receive endpoint's byte count register transaction. control logic KS86C6104/P6104, when transmitting, manages parallel serial conversion, packet generation, generation, NRZI encoding stuffing. When receiving, control logic KS86C6104/P6104 handles Sync detection, packet decoding, (end packet) detection, (un)stuffing, NRZI decoding, checking serial parallel conversion Protocol transactions involve transmission packets. KS86C6104/P6104 supports three packet types; Token, Data Handshake. Each transaction starts when host controller sends Token Packet device. Token packets generated host decoded device. Token Packet includes type description, direction transaction, device address endpoint number. Data Handshake packets both decoded generated device. transaction, data transferred from host device from device host. transaction source then sends Data Packet indicates that data transfer. destination then responds with Handshake Packet indicating whether transfer successful. Data Transfer Types data transfer occurs between host software specific endpoint device. endpoint supports specific type data transfer. KS86C6104/P6104 supports data transfer endpoints: control interrupt. Control transfer configures assigns address device when detected. Control transfer also supports status transaction, returning status information from device host. Interrupt transfer refers small, spontaneous data transfer from device host. Endpoints Communication flows between host software endpoints device. Each endpoint device identifier number. addition endpoint number, each endpoint supports specific transfer type. KS86C6104/P6104 supports endpoints: Endpoint supports control transfer, Endpoint supports interrupt transfer.
11-2
KS86C6104/P6104
UNIVERSAL SERIAL
FUNCTION ADDRESS REGISTER (USBADDR) This register holds address assigned host computer. USBADDR located address read/write addressable. Bit7 used
Bit6-0 FADDR: updates this register once decodes SET_ADDRESS command. must write this register before clears OUT_PKT_RDY (bit0) sets DATA_END (bit3) EP0STU register. function controller this register's value decode Token packet address. reset, device configured value reset
Function Address Register(FADDR) F0H,
used 7-bit programming device address. This register maintains address assigned host. function controller uses this register's value decode token packet address. reset when device configured value reset
Figure 11-2. Function Address Register (FADDR)
11-3
UNIVERSAL SERIAL
KS86C6104/P6104
CONTROL ENDPOINT STATUS REGISTER (EP0CSR) EP0CSR register controls Endpoint (Control Endpoint), also holds status bits Endpoint EP0CSR located read/write addressable. Bit7 Bit6 Bit5 CLEAR_SETUP_END: writes this clear SETUP_END (bit4). This automatically cleared after writing block. CLEAR_OUT_PKT_RDY: writes this clear OUT_PKT_RDY (bit0). This automatically cleared after writing block. SEND_STALL: writes this send STALL signal Host, same time clears OUT_PKT_RDY (bit0), decodes invalid token. issues STALL Handshake current control transfer. This gets cleared once STALL Handshake issued current control transfer. SETUP_END: sets this bit, when control transfer ends before DATA_END (bit3) set. clears this bit, writing SERVICED_SETUP_END (bit7). When sets this bit, interrupt generated MCU. When such condition occurs, flushes FIFO, invalidates MCU's access FIFO. DATA_END: sets this bit: After loading last packet data into FIFO, same time IN_PKT_RDY set. While clears OUT_PKT_RDY after unloading last packet data. zero length data phase, when clears OUT_PKT_RDY bit, sets IN_PKT_RDY bit. Bit2 Bit1 SENT_STALL: sets this bit, control transaction ended protocol violation. interrupt generated when this gets set. clears this STALL condition. IN_PKT_RDY: sets this bit, after writing packet data into Endpoint FIFO. clears this bit, once packet been successfully sent host. interrupt generated when clears this that load next packet. zero length data phase, sets IN_PKT_RDY DATA_END same time. OUT_PKT_RDY: sets this bit, once valid token written FIFO. interrupt generated, when sets this bit. clears this writing SERVICED_OUT_PKT_RDY bit.
Bit4
Bit3
Bit0
NOTES: control transfer case, where there data phase, after unloading setup token, sets IN_PKT_RDY, DATA_END same time clears OUT_PKT_RDY setup token. When SETUP_END set, OUT_PKT_RDY also set. This happens when current transfer ended, control transfer received before service interrupt. such case, should first clear SETUP_END bit, then start servicing control transfer.
11-4
KS86C6104/P6104
UNIVERSAL SERIAL
Control Endpoint Status Register (EP0CSR) F1H,
CLEAR_ SETUP_END CLEAR_ OUT_PKT_RDY SEND_STALL
OUT_PKT_RDY IN_PKT_RDY SENT_STALL DATA_END
SETUP_END
Figure 11-3. Control Endpoint Status Register (EP0CSR)
11-5
UNIVERSAL SERIAL
KS86C6104/P6104
INTERRUPT ENDPOINT STATUS REGISTER (EP1CSR) EP1CSR control register Endpoint Interrupt Endpoint. This register located address read/write addressable. Bit7 CLR_DATA_TOGGLE: writes this clear data toggle sequence bit. When writes this register, data toggle initialized DATA0.
Bit6-3 MAXP: These bits indicate maximum packet size endpoint, needs updated before sets IN_PKT_RDY. Once set, contents valid till re-writes them. Bit2 Bit1 Bit0 FLUSH_FIFO: When writes this register, FIFO flushed, IN_PKT_RDY cleared. should wait IN_PKT_RDY cleared flush take place. FORCE_STALL: writes this register issue STALL Handshake USB. clears this bit, STALL condition. IN_PKT_RDY: sets this bit, after writing packet data into Endpoint FIFO. clears this bit, once packet been successfully sent Host. interrupt generated when clears this bit, load next packet.
Control Endpoint Status Register (EP1CSR) F2H,
CLEAR_DATA_TOGGLE MAXP
IN_PKT_RDY FORCE_STALL FLUSH_FIFO
Figure 11-4. Interrupt Endpoint Status Register (EP1CSR)
CONTROL ENDPOINT BYTE COUNT REGISTER (EP0BCNT) EP0BCNT register number valid bytes Endpoint FIFO. located address read only addressable. Once receives OUT_PKT_RDY (Bit0 EP0CSR) Endpoint then read this register find number bytes read from Endpoint FIFO.
11-6
KS86C6104/P6104
UNIVERSAL SERIAL
CONTROL ENDPOINT FIFO REGISTER (EP0FIFO) This register bi-directional, byte depth FIFO used transfer Control Endpoint data. EP0FIFO located address read/write addressable. Initially, direction FIFO, from Host MCU. After setup token received control transfer, that after unload setup token bytes, clears OUT_PKT_RDY, direction FIFO changed automatically from Host. INTERRUPT ENDPOINT FIFO REGISTER (EP1FIFO) EP1FIFO uni-direction 8-byte depth FIFO used transfer data from Host. writes data this register, when finished IN_PKT_RDY. This register located address F5H. INTERRUPT PENDING REGISTER (USBPND) USBPND register interrupt bits endpoints power management. This register cleared once read MCU. While bits set, interrupt generated. USBPND located address F6H. Bit7-4 used Bit3 Bit2 Bit1 Bit0 RESUME_PND: While suspend mode, resume signaling received this gets set. SUSPEND_PND: This set, when suspend signaling received. ENDPT1_PND: This set, when Endpoint needs serviced. ENDPT0_PND: This set, when Endpoint needs serviced. under following conditions: OUT_PKT_RDY set. IN_PKT_RDY gets cleared. SENT_STALL gets set. DATA_END gets cleared. SETUP_END gets set.
Interrupt Pending Register (USBPND) F6H,
used RESUME_PND
ENDPT0_PND ENDPT1_PND
SUSPEND_PND
Figure 11-5. Interrupt Pending Register (USBPND)
11-7
UNIVERSAL SERIAL
KS86C6104/P6104
INTERRUPT ENABLE REGISTER (USBINT) USBINT located address read/write addressable. This register serves interrupt mask register. corresponding then respective interrupt enabled. default, interrupts except suspend interrupt enabled. Interrupt enables bits suspend resume combined into single (bit Bit7-3 used Bit2 ENABLE_SUSPEND_RESUME_INT: Enable SUSPEND RESUME INTERRUPT Disable SUSPEND RESUME INTERRUPT (default) ENABLE_ENDPT1_INT: Enable ENDPOINT INTERRUPT (default) Disable ENDPOINT INTERRUPT ENABLE_ENDPT0_INT: Enable ENDPOINT INTERRUPT (default) Disable ENDPOINT INTERRUPT
Bit0
Interrupt Enable Register (USBINT) F7H,
used
ENABLE_ENDPT0_INT ENABLE_ENDPT1_INT ENABLE_SUSPEND_RESUME_INT
Figure 11-6. Interrupt Enable Register (USBINT)
11-8
KS86C6104/P6104
UNIVERSAL SERIAL
POWER MANAGEMENT REGISTER (PWRMGR) PWRMGR register interacts with Host's power management system execute system power events such SUSPEND RESUME. This register located address read/write addressable. Bit7-2 RESERVED: value read from this zero. Bit1 SEND_RESUME: While SUSPEND state, wants initiate RESUME, writes this register 10ms (maximum 15ms), clears this register. SUSPEND mode this reads "1", generates RESUME signaling. SUSPEND_STATE: Suspend state when sets suspend interrupt. This cleared automatically when: writes SEND_RESUME RESUME signaling (after SEND_RESUME 10ms). receives RESUMES signaling from Host while SUSPEND mode.
Bit0
Power Management Register (PWRMGR) F8H,
value read form this zero
SUSPEND_STATE SEND_RESUME
Figure 11-7. Power Management Register (PWRMGR)
11-9
UNIVERSAL SERIAL
KS86C6104/P6104
RESET REGISTER (USBRST) USBRST register receives reset signal from Host. This register located address read/write addressable. Bit7-1 used Bit0 USBRST: This when Host issues reset signal.
RESET Register (USBRST) FFH,
used
USBRST
Figure 11-8. RESET Register (USBRST)
11-10
KS86C6104/P6104
COMPARATOR
OVERVIEW
Analog comparator
COMPARATOR
P1.0-P1.3 used analog input port comparator. reference voltage 4-channel comparator supplied either internally externally P1.3. When internal reference voltage used, four channels (P1.0-P1.3) used analog inputs internal reference voltage varied levels. external reference voltage input P1.3, other three pins (P1.0-P1.2) port used analog input. Unused port pins should connected current saving. When conversion completed, result saved comparison result register CDATA. initial values CDATA undefined comparator operation disabled RESET
Internal reference voltage generator (4-bit resolution) External reference voltage source P1.3 Comparator mode register (CCON) Four multiplexed analog data input pins (CIN0-CIN3) 4-channel conversion data result register (CDATA) 4-bit digital input port (alternatively, port)
FUNCTION DESCRIPTION
comparator compares analog voltage input CIN0-CIN3 with external internal reference voltage (VREF) that selected CCON register. result written comparison result register CDATA address E5H. comparison result calculated follows. Analog input voltage VREF Analog input voltage VREF obtain comparison result, data must read from CDATA register after VREF updated changing CCON value after conversion time elapsed. COMPARATOR CONTROL REGISTER (CCON) comparator control register CCON 8-bit register that used operation mode comparator. initiate comparison procedure, write reference voltage selection data comparator control register CCON comparison start enable bit, CCON.7.
COMPARATOR
KS86C6104/P6104
4-bit Comparator Control Register (CCON)
Comparator start control bit: Start enable operation Disable operation
Reference voltage (VREF) selection bits: 0.5)
Comparison time selection bit: Comparison time CPU) Comparison time CPU)
Reference selection bits: CIN3: External reference, CIN0-2: Analog input Internal reference, CIN0-3: Analog input
Figure 12-1. Comparison Control Register (CCON)
12-2
KS86C6104/P6104
COMPARATOR
BLOCK DIAGRAM
P1.0/CIN0 P1.1/CIN0 P1.2/CIN1 P1.3/CIN2 VREF (EXTERNAL) CCON.7 1/2R 1/2R VREF (INTERNAL) CCON.6 CCON.5 CCON.4 CCON.3 CCON.2 CCON.1 CCON.0 INTERNAL COMPARISON RESULT REGISTER (CMPREG)
Figure 12-2. Comparator Functional Block Diagram
12-3
COMPARATOR
KS86C6104/P6104
NOTES
12-4
KS86C6104/P6104
ELECTRICAL DATA
OVERVIEW
capacitance
ELECTRICAL DATA
this section, following KS86C6104/P6104 electrical characteristics presented tables graphs: Absolute maximum ratings D.C. electrical characteristics A.C. electrical characteristics Input timing RESET Oscillator characteristics Operating voltage range Oscillation stabilization time Clock timing measurement points Data retention supply voltage Stop mode Stop mode release timing when initiated RESET Stop mode release timing when initiated external interrupt Characteristic curves Comparator Electrical Characteristics
ELECTRICAL DATA
KS86C6104/P6104
Table 13-1. Absolute Maximum Ratings 25°C) Parameter Supply voltage Input voltage Output voltage Output current high Output current Operating temperature Storage temperature Symbol TSTG ports output ports active pins active active Total current ports Conditions Rating
Unit
13-2
KS86C6104/P6104
ELECTRICAL DATA
Table 13-2. D.C. Electrical Characteristics 40°C 85°C, 5.25 Parameter Input highvoltage Symbol VIH1 VIH2 Input voltage VIL1 VIL2 Output high voltage input pins except VIL2, output ports except output ports except inputs except ILIH2 except XIN, XOUT inputs except ILIL2 except XOUT, VOUT output pins except VOUT output pins except RESET only Normal operation mode 6-MHz clock Idle mode; 6-MHz clock Stop mode; oscillator stop Conditions input pins except VIH2, Unit
Output voltage
Input high leakage current
ILIH
ILIH2 Input leakage current ILIL
ILIL2 Output high leakage current Output leakage current Pull-up resistors ILOH ILOL Supply current (note) IDD1 IDD2 IDD3
NOTES: Supply current does include current drawn through internal pull-up resistors external output current load. This parameter guaranteed, tested (include D-). Only 5.25 satisfy spec 1.0.
13-3
ELECTRICAL DATA
KS86C6104/P6104
Table 13-3. Input/Output Capacitance 40°C 85°C, Parameter Input capacitance Output capacitance capacitance Symbol COUT Table 13-4. A.C. Electrical Characteristics 40°C 85°C, 5.25 Parameter Noise filter
RESET input width
Conditions MHz; unmeasured pins connected
Unit
Symbol tNF2 tRSL
Conditions
RESET only delay)
Unit
tNF1H, tNF1L delay) Input
NF1L
NF1H
RESET
0.5VDD
Figure 13-1. Input Timing RESET
13-4
KS86C6104/P6104
ELECTRICAL DATA
Table 13-5. Oscillator Characteristics 40°C 85°C) Oscillator Main crystal Main ceramic (fOSC) Clock Circuit
Test Condition Oscillation frequency 5.25
Unit
XOUT
External clock
XOUT
Oscillation frequency 5.25
Table 13-6. Oscillation Stabilization Time 40°C 85°C, 5.25 Oscillator Main crystal Main ceramic Oscillator stabilization wait time Test Condition fOSC (Oscillation stabilization occurs when equal minimum oscillator voltage range.) tWAIT stop mode release time reset Unit
216/fOSC
tWAIT stop mode release time interrupt
NOTE: oscillator stabilization wait time, tWAIT, when released interrupt, determined setting basic timer control register, BTCON.
13-5
ELECTRICAL DATA
KS86C6104/P6104
Figure 13-2. Clock Timing Measurement Points
Table 13-7. Data Retention Supply Voltage Stop Mode 70°C) Parameter Data retention supply voltage Data retention supply current Symbol VDDDR IDDDR Conditions Stop mode Stop mode; VDDDR Unit
13-6
KS86C6104/P6104
ELECTRICAL DATA
INTERNAL RESET
STOP MODE DATA RETENTION MODE
IDLE MODE (BASIC TIMER ACTIVE)
VDDDR
RESET
EXECUTION STOP WAIT
NORMAL OPERATING MODE
Figure 13-3. Stop Mode Release Timing When Initiated RESET
STOP MODE DATA RETENTION MODE
IDLE MODE (BASIC TIMER ACTIVE)
VDDDR EXTERNAL INTERRUPT EXECUTION STOP INSTRUCTION tWAIT
NORMAL OPERATING MODE
Figure 13-4. Stop Mode Release Timing When Initiated External Interrupt
13-7
ELECTRICAL DATA
KS86C6104/P6104
Table 13-8. Comparator Electrical Characteristics 40°C 85°C, 5.25 Parameter Conversion time Symbol tCON Conditions 1000 Unit FCPU
Comparator input voltage Comparator input impedance Comparator reference voltage Comparator input current Reference input current Comparator block current
VICN VREF ICIN IREF ICOM
(when power down mode)
NOTES: Conversion time time required from moment conversion operation starts until ends. ICOM operating current during conversion.
13-8
KS86C6104/P6104
ELECTRICAL DATA
Table 13-9. Speed Source Electrical Characteristics (USB) 40°C 85°C, Voltage Regulator Output V33out Parameter Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Voltage Regulator Output Voltage Symbol Trfm Vcrs Conditions (Tr/Tf) Unit
V33OUT with V33OUT capacitor
Test Point D.U.T
2.8V
MEASUREMENT POINTS
50pF-350pF
Figure 13-5. Data Signal Rise Fall Time
Vcrs
MAX: MIN:
Figure 13-6. Output Signal Crossover Point Voltage
13-9
ELECTRICAL DATA
KS86C6104/P6104
NOTES
13-10
KS86C6104/P6104 MICROCONTROLLER
MECHANICAL DATA
OVERVIEW diagram
MECHANICAL DATA
This section contains following information about device package: Package dimensions millimeters
0-15°
6.40
7.62
3.25
26.40
0.46 (1.77) 1.52 2.54
NOTE: Dimensions millimeters.
Figure 14-1. 20-DIP0300A Package Dimensions
3.30
0.51MIN
5.08MAX
26.80
0.25
20-DIP-300A
0.05
MECHANICAL DATA
KS86C6104/P6104 MICROCONTROLLER
0-8°
10.30
7.50
9.53
+0.10
24-SOP-375
0.15 0.05
15.34
(0.69)
0.38
1.27
NOTE: Dimensions millimeters.
Figure 14-2. 24-SOP-375 Package Dimensions
14-2
0.05MIN
2.70MAX
15.74
2.30
0.10
0.85 ±0.20
KS86C6104/P6104
KS86P6104
OVERVIEW
KS86P6104
KS86P6104 single-chip CMOS microcontroller (One Time Programmable) version KS86C6104 microcontroller. on-chip instead masked ROM. EPROM accessed serial data format. KS86P6104 fully compatible with KS86C6104, both function configuration. Because simple programming requirements, KS86P6104 ideal evaluation chip KS86C6104.
/VSS Xout TEST/TEST P0.0/INT0 P0.1/INT0
RESET
/VDD P1.0/CIN0/SCLK P1.1/CIN1/SDAT P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3Vout
KS86P6104
(TOP VIEW)
/RESET
P0.2/INT0 P1.7/INT1 P1.6/INT
Figure 15-1. KS86P6104 Assignments (20-DIP Package)
KS86P6104
KS86C6104/P6104
VSS/V Xout TEST/TEST P0.0/INT0 P0.1/INT0
RESET
VDD/ P1.0/CIN0/ SCLK P1.1/CIN1/ SDAT P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1 3.3V
KS86P6104
(TOP VIEW)
RESET
P0.2/INT0 P1.7/INT1 P1.6/INT
Figure 15-2. KS86P6104 Assignments (24-SOP Package)
15-2
KS86C6104/P6104
KS86P6104
Table 15-1. Descriptions Pins Used Read/Write EPROM Main Chip Name P1.0 (Pin Name SDAT DIP) During Programming Function Serial Data (Output when reading, Input when writing) Input Push-pull Output Port assigned Serial Clock (Input Only Pin) write test mode Operating mode Chip Initialization EPROM Cell Writing Power Supply (Indicates Mode Entering) When writing 12.5V applied when reading. Logic Power Supply Pin.
P1.1 (Pin TEST
RESET
SCLK (TEST)
RESET
VDD/VSS
VDD/VSS
Table 15-2. Comparison KS86P6104 KS86C6104 Features Characteristic Program Memory Operating Voltage (VDD) Programming Mode Configuration EPROM Programmability KS86P6104 byte EPROM 5.25 (RESET)=12.5V DIP/24 User Program time DIP/24 Programmed factory KS86C6104 byte mask 5.25
15-3
KS86P6104
KS86C6104/P6104
OPERATING MODE CHARACTERISTICS When 12.5 supplied (RESET) KS86P6104, EPROM programming mode entered. operating mode (read, write, read protection) selected according input signals pins listed Table 14-3 below. Table 15-3. Operating Mode Selection Criteria (RESET) 12.5 12.5 12.5 REG/
Address (A15-A0) 0000H 0000H 0000H 0E3FH
EPROM read
Mode
EPROM program EPROM verify EPROM read protection
NOTE: means level; means High level.
Table 15-4. D.C. Electrical Characteristics 40°C 85°C, 5.25 Parameter Supply Current (note) Symbol IDD1 IDD2 IDD3
NOTE:
Conditions Normal mode; clock Idle mode; clock Stop mode; oscillator stop
Unit
Supply current does include current drawn through internal pull-up resistors external output current loads.
15-4
KS86C6104/P6104
KS86P6104
START
Address= First Location
=5V, PP=12.5V
Program Pulse
Increment
FAIL
Verify Byte
Verify Byte
FAIL
Last Address
Increment Address
VPP=
FAIL
Compare Byte
PASS
Device Failed
Device Passed
Figure 15-3. Programming Algorithm
15-5
KS86P6104
KS86C6104/P6104
NOTES
15-6
KS86C6104/P6104
DEVELOPMENT TOOLS
OVERVIEW
SHINE
DEVELOPMENT TOOLS
Samsung provides powerful easy-to-use development support system turnkey form. development support system configured with host system, debugging tools, support software. host system, standard computer that operates with MS-DOS operating system used. type debugging tool including hardware software provided: sophisticated powerful in-circuit emulator, SMDS2+, KS57, KS86, KS88 families microcontrollers. SMDS2+ improved version SMDS2. Samsung also offers support software that includes debugger, assembler, program setting options.
Samsung Host Interface in-circuit Emulator, SHINE, multi-window based debugger SMDS2+. SHINE provides pull-down pop-up menus, mouse support, function/hot keys, context-sensitive hyper-linked help. advanced, multiple-windowed user interface that emphasizes ease use. Each window sized, moved, scrolled, highlighted, added, removed completely. SAMA ASSEMBLER Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, universal assembler, generates object code standard hexadecimal format. Assembled program code includes object code that used data required SMDS program control data. assemble programs, SAMA requires source file auxiliary definition (DEF) file with device specific information. SASM86 SASM86 relocatable assembler Samsung's KS86-series microcontrollers. SASM86 takes source file containing assembly language statements translates into corresponding source code, object code comments. SASM86 supports macros conditional assembly. runs MS-DOS operating system. produces relocatable object code only, user should link object file. Object files linked with other object files loaded into memory. HEX2ROM HEX2ROM file generates code from file which been produced assembler. code must needed fabricate microcontroller which mask ROM. When generating code (.OBJ file) HEX2ROM, value "FF" filled into unused area upto maximum size target device automatically.
DEVELOPMENT TOOLS
KS86C6104/P6104
TARGET BOARDS Target boards available KS86-series microcontrollers. required target system cables adapters included with device-specific target board. OTPs times programmable microcontrollers (OTPs) under development KS86C6104 microcontroller.
IBM-PC Compatible
RS-232C
SMDS2+
PROM/OTP WRITER UNIT
TARGET APPLICATION SYSTEM
BREAK/ DISPLAY UNIT PROBE ADAPTER TRACE/TIMER UNIT
SAM4 BASE UNIT
TB866104A TARGET BOARD
POWER SUPPLY UNIT
CHIP
Figure 16-1. SMDS Product Configuration (SMDS2+)
16-2
KS86C6104/P6104
DEVELOPMENT TOOLS
TB866104A TARGET BOARD TB866104A target board used KS86C6104 microcontrollers. supported SMDS2+ development systems. TB866104A target board also used KS86C6104.
TB866104A
User_V RESET IDLE STOP J101 SMDS2 SMDS2+ 20-DIP SOCKET
100-PIN CONNECTOR
KS86E6100 CHIP
EXTERNAL TRIGGERS
SM1307A
Figure 16-2. TB866104A Target Board Configuration
16-3
DEVELOPMENT TOOLS
KS86C6104/P6104
Table 16-1. Power Selection Settings TB866104A User_Vcc' Settings User_Vcc
SMDS2+ TB866104A TARGET SYSTEM
Operating Mode
Comments SMDS2/SMDS2+ supplies target board (evaluation chip) target system.
User_Vcc
SMDS2+ TB866104A External TARGET SYSTEM
SMDS2/SMDS2+ supplies only target board (evaluation chip). target system must have power supply.
NOTE: following symbol User_VCC" Setting column indicates electrical short (off) configuration:
SMDS2+ Selection (SAM8) order write data into program memory that available SMDS2+, target board should selected SMDS2+ through switch follows. Otherwise, program memory writing function available. Table 16-2. SMDS2+ Tool Selection Setting "SW1" Setting SMDS2 SMDS2+ Operating Mode
R/W* SMDS2+
R/W*
TARGET BOARD
16-4
KS86C6104/P6104
DEVELOPMENT TOOLS
Table 16-3. Using Single Header Pins Input Path External Trigger Sources Target Board Part Comments
EXTERNAL TRIGGERS
Connector from external trigger sources application system
connect external trigger source external trigger channels (CH1 CH2) SMDS2+ breakpoint trace functions.
16-5
DEVELOPMENT TOOLS
KS86C6104/P6104
J101 P0.0/INT0 P0.1/INT0
RESET
P0.2/INT0 P1.7/INT1 P1.6/INT
P1.0/CIN0 P1.1/CIN1 P1.2/CIN2 P1.3/CIN3 P1.4/INT1 P1.5/INT1
Figure 16-3. 20-Pin Socket TB866104A
20-PIN SOCKET
TARGET BOARD J101 20-PIN SOCKET
TARGET SYSTEM J101 20-PIN SOCKET
Part Name: AS20D Order Code: SM6304
Figure 16-4. KS86C6104 Probe Adapter Cable 20-DIP Package
16-6

SAM87RI PRODUCT FAMILY Samsung's SAM87RI family 8-bit single-chip

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