700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs Selectable CLK, nCLK LVCMOS TEST_CLK TEST_CLK accept following input levels: LVCMOS LVTTL CLK, nCLK pair accept following differential input levels: LVPECL, LVHSTL, LVDS, SSTL Output frequency range: 25MHz 700MHz Differential input TEST_CLK input frequency: 60MHz range: 200MHz 700MHz Accepts single-ended input signal LVCMOS with resistor bias nCLK input Parallel interface programming counter output dividers period jitter: Cycle-to-cycle jitter: 17ps (typical) 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-101 general purpose, dual output Differential-to-3.3V LVPECL high frequency HiPerClockSsynthesizer member HiPerClockSfamily High Performance Clock Solutions from ICS. ICS8432-101 selectable TEST_CLK CLK, nCLK inputs. TEST_CLK input accepts LVCMOS LVTTL input levels translates them 3.3V LVPECL levels. CLK, nCLK pair accept most standard differential input levels. operates frequency range 200MHz 700MHz. frequency programmed steps equal value input differential single ended reference frequency. output frequency programmed using serial parallel interfaces configuration logic. phase noise characteristics ICS8432-101 makes ideal clock source Gigabit Ethernet, Fiber Channel Infiniband applications.
BLOCK DIAGRAM
VCO_SEL CLK_SEL TEST_CLK nCLK
ASSIGNMENT
VCO_SEL nP_LOAD nCLK
TEST FOUT1 nFOUT1 VCCO FOUT0 nFOUT0
TEST_CLK CLK_SEL VCCA S_LOAD S_DATA S_CLOCK
PHASE DETECTOR FOUT0 nFOUT0 FOUT1 nFOUT1
ICS8432-101
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
CONFIGURATION INTERFACE LOGIC
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz clock input. Valid loop divider values different input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-101 features fully integrated therefore requires external components setting loop bandwidth. differential clock input used input ICS8432-101. This input into phase detector. 25MHz clock input provides 25MHz phase detector reference frequency. operates over range 200MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-101 support input modes programmable divider output divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode nP_LOAD input initially LOW. data inputs through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, input frequency divider defined follows: fVCO value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock 25MHz reference defined frequency defined follows: fOUT fVCO Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-toLOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data Output divider CMOS Fout
S_DATA S_CLOCK S_LOAD
*NULL
M0:M8, N0:N1 nP_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE: NULL timing slot must observed.
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Input Input Input Input Power Input Input Input Input Input Input Pullup Pulldown Pulldown Pullup Pulldown Pulldown Pulldown Pulldown Pullup divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. connect. Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Positive supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Master reset. Forces outputs LOW, does effect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLOCK. Shift register serial input. Data sampled rising edge S_CLOCK. Controls transition data from shift register into dividers. LVCMOS LVTTL interface levels. Analog supply pin. Clock select input. Selects between differential clock input TEST_CLK input reference source. When HIGH, selects CLK, nCLK inputs. When LOW, selects TEST_CLK input. LVCMOS LVTTL interface levels. Test clock input. LVCMOS LVTTL interface levels. Non-inver ting differential clock input. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 S_CLOCK S_DATA S_LOAD VCCA CLK_SEL TEST_CLK nCLK nP_LOAD VCO_SEL
Inver ting differential clock input. Parallel load input. Determines when data present M8:M0 Pulldown loaded into divider, when data present N1:N0 sets output divider value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. Pullup LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characterisitics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE PARALLEL
SERIAL MODES FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider output divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond differential input TEST_CLK input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs Divider Value Output Frequency (MHz) Minimum Maximum 87.5
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REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 0.5V -0.5V VCCO 0.5V 47.9°C/W lfpm) -65°C 150°C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCx Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK VCO_SEL, CLK_SEL, S_LOAD, S_DATA, S_CLOCK, nP_LOAD, M0:M8, N0:N1 TEST_CLK M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD CLK_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD CLK_SEL, VCO_SEL Output High Voltage Output Voltage TEST TEST Test Conditions Minimum -0.3 -0.3 3.465V 3.465V 3.465V, 3.465V, 3.135V, -36mA 3.135V, 36mA
Typical
Maximum
Units
Input Voltage
Input High Current
Input Current
-150
8432DY-101
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ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions nCLK nCLK 3.465V 3.465V 3.465V, 3.465V, -150 0.15 0.85 Minimum Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V. NOTE Common mode voltage defined VIH.
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO 0.85 Units
Peak-to-Peak Output Voltage Swing VSWING NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter TEST_CLK; NOTE Input Frequency CLK, nCLK; NOTE Test Conditions Minimum Typical Maximum Units
S_CLOCK NOTE differential input TEST_CLK frequency range, value must operate within 200MHz 700MHz range. Using minimum input frequency 12MHz, valid values Using maximum frequency 25MHz, valid values
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 50MHz 50MHz nP_LOAD S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol FOUT Parameter Output Frequency Cycle-to-Cycle Jitter, RMS; NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time Setup Time
tjit(cc) tjit(per) tsk(o)
Hold Time Output Duty Cycle
S_DATA S_CLOCK S_CLOCK S_LOAD
Lock Time tLOCK parameters measured 500MHz unless noted otherwise. NOTE cycle-to-cyle jitter input will euqal jiter output. does jitter. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
LVPECL
VCC, VCCA, VCCO
-1.3V 0.135V
3.3V OUTPUT LOAD TEST CIRCUIT
nCLK
Cross Points
DIFFERENTIAL INPUT LEVEL
nFOUTx FOUTx
nFOUTy FOUTy
tsk(o)
OUTPUT SKEW
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Vref
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
nFOUTx
FOUTx
tcycle
jit(cc) tcycle -tcycle
Cycle-to-Cycle Jitter
Clock Inputs Outputs
INPUT
OUTPUT RISE
nFOUTx TEST, FOUTx
Pulse Width
PERIOD
PERIOD
tPERIOD
8432DY-101
tcycle
SWING
FALL TIME
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATIONS
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8432-101 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01µF bypass capacitor should connected each VCCA pin.
3.3V .01µF VCCA .01µF
FIGURE POWER SUPPLY FILTERING
TERMINATION LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. There simple termination schemes. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V FOUT
FOUT
(VOH
FIGURE LVPECL OUTPUT TERMINATION
8432DY-101
FIGURE LVPECL OUTPUT TERMINATION
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
schematic ICS8432-101 layout example used this layout guideline shown Figure ICS8432-101 recommended board layout this example shown Figure This layout example used general guideline. layout actual system will depend selected component types, density components, density traces, stacking P.C. board.
nCLK 0.01u XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
TEST FOUT1/2 nFOUT1/2 VCCO FOUT nFOUT
VCO_SEL nP_LOAD nCLK
REF_IN nCLK_SEL VDDA S_LOAD S_DATA S_CLOCK
Termination
FOUT FOUTN
8432-101
Termination (not shown layout)
TEST
0.1u
INC15 0.1u
FIGURE SCHEMATIC
RECOMMENDED LAYOUT
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
system failure. trace shape trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. traces with transmission lines FOUT nFOUT should have equal delay adjacent each other. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock trace same layer. Whenever possible, avoid vias clock traces. trace affect trace characteristic impedance hence degrade signal quality. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow more space between clock trace other signal trace. Make sure other signal trace routed between clock trace pair. matching termination resistors should located close receiver input pins possible. Other termination schemes also used shown this example.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placing decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power generated via. Maximize size power (ground) decoupling capacitor. Maximize number vias between power (ground) pads. This reduce inductance between power (ground) plane component power (ground) pins. VCCA shares same power supply with VCC, insert filter C11, between. Place this filter close VCCA possible.
CLOCK TRACES
TERMINATION
component placements, locations orientations should arranged achieve best clock signal quality. Poor clock signal quality degrade system performance cause system failure. synchronous high-speed digital system, clock signal less tolerable poor signal quality than other signals. ringing rising falling edge excessive ring back cause
VCCA Close input pins receiver TL1N
TL1N
TL1, traces equal length
FIGURE BOARD LAYOUT
ICS8432-101
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
LOGIC CONTROL INPUT
logic input control signals 3.3V LVCMOS compatible. logic control input contains diodes either pull-up pull-down resistor shown Figure data sheet provides pull-up pull-down information each input pin. Leaving input floating will control logic default setting.
INPUT_PU INPUT_DOWN
Input with internal pull resistor
Input with internal pull down resistor
FIGURE LOGIC CONTROL INPUT CIRCUITRY
logic high, input connected directly through resistor shown Figure 6(A). logic low, control input connect directly through resistor ground shown Figure 6(B). control signal source from LVCMOS/LVTTL driver that separated power supply, series current resistor required random power sequence shown Figure
Logic_control_input Logic_control_input
Input Logic
Input Logic
FIGURE RECOMMENDED LOGIC CONTROL INPUT
LOGIC HIGH
LOGIC
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
VDD1
LVCMOS/LVTTL
Logic_control_input
FIGURE CURRENT LIMIT RESISTOR
RANDOM POWER SEQUENCE
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8432-101. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8432-101 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 110mA 381.2mW Power (outputs)MAX 30.2mW/Loaded Output pair outputs loaded, total power 30.2mW 60.4mW
Total Power_MAX (3.465V, with outputs switching) 381.2mW 60.4mW 441.6mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.441W 42.1°C/W 88.6°C. This well below limit 125°C This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
8432DY-101
REV. MARCH 2002
Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
1.0V
OH_MAX
1.0V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50W] 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50W] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8432-101 3712
8432DY-101
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL
Reference Document: JEDEC Publication MS-026
8432DY-101
MINIMUM
NOMINAL
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0.60 0.75 0.10 1.40 0.37 0.15 1.45 0.45 0.20
REV. MARCH 2002
ICS8432-101
700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432DY-101 ICS8432DY-101 Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432DY-101 ICS8432DY-101T
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432DY-101
REV. MARCH 2002

700MHZ, PHASE NOISE, DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER

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