75A, 80V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging
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HUF75542P3, HUF75542S3S
75A, 80V, 0.014 Ohm, N-Channel, UltraFET Power MOSFETs Packaging
JEDEC TO-220AB
SOURCE DRAIN GATE
JEDEC TO-263AB
Features
Ultra On-Resistance rDS(ON) 0.014,
GATE SOURCE DRAIN (FLANGE) HUF75542P3 DRAIN (FLANGE) HUF75542S3S
Simulation Models Temperature Compensated PSPICE® SABERElectrical Models Spice SABER Thermal Impedance Models www.fairchildsemi.com Peak Current Pulse Width Curve Rating Curve
Symbol
Ordering Information
PART NUMBER HUF75542P3 PACKAGE TO-220AB TO-263AB BRAND 75542P 75542S
HUF75542S3S
NOTE: When ordering, entire part number. suffix obtain variant tape reel, e.g., HUF75542S3ST.
Absolute Maximum Ratings
25oC, Unless Otherwise Specified HUF75542P3, HUF75542S3S UNITS Figure Figures 1.54 W/oC
Drain Source Voltage (Note VDSS Drain Gate Voltage (RGS 20k) (Note VDGR Gate Source Voltage Drain Current Continuous 25oC, 10V) (Figure Continuous 100oC, 10V) (Figure Pulsed Drain Current Pulsed Avalanche Rating Power Dissipation Derate Above 25oC Operating Storage Temperature TSTG Maximum Temperature Soldering Leads 0.063in (1.6mm) from Case Package Body 10s, Techbrief TB334. Tpkg NOTE: 25oC 150oC.
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Product reliability information found severe environments, Automotive HUFA series. Fairchild semiconductor products manufactured, assembled tested under ISO9000 QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S
Electrical Specifications
PARAMETER STATE SPECIFICATIONS Drain Source Breakdown Voltage Zero Gate Voltage Drain Current BVDSS IDSS 250µA, (Figure 75V, 70V, 150oC Gate Source Leakage Current STATE SPECIFICATIONS Gate Source Threshold Voltage Drain Source Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction Case Thermal Resistance Junction Ambient TO-220 TO-263 0.65
oC/W oC/W
25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS UNITS
±100
IGSS
±20V
VGS(TH) rDS(ON)
VDS, 250µA (Figure 75A, (Figure
0.012
0.014
SWITCHING SPECIFICATIONS (VGS 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge Threshold Gate Charge Gate Source Gate Charge Gate Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS 25V, 1MHz (Figure 2750 Qg(TOT) Qg(10) Qg(TH) 40V, 75A, Ig(REF) 1.0mA (Figures td(ON) td(OFF) tOFF 40V, 10V, (Figures 12.5
Source Drain Diode Specifications
PARAMETER Source Drain Diode Voltage SYMBOL 37.5A Reverse Recovery Time Reverse Recovered Charge 75A, dISD/dt 100A/µs 75A, dISD/dt 100A/µs TEST CONDITIONS 1.25 1.00 UNITS
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S Typical Performance Curves
POWER DISSIPATION MULTIPLIER CASE TEMPERATURE (oC) CASE TEMPERATURE (oC) DRAIN CURRENT THERMAL IMPEDANCE NORMALIZED DUTY CYCLE DESCENDING ORDER 0.05 0.02 0.01 NOTES: DUTY FACTOR: t1/t2 PEAK 10-3 10-2 RECTANGULAR PULSE DURATION 10-1 SINGLE PULSE 0.01 10-5 10-4
FIGURE NORMALIZED POWER DISSIPATION CASE TEMPERATURE
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000 25oC PEAK CURRENT TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT FOLLOWS: TRANSCONDUCTANCE LIMIT CURRENT THIS REGION 10-5 10-4 10-3 10-2 PULSE WIDTH 10-1
FIGURE PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S Typical Performance Curves
AVALANCHE CURRENT SINGLE PULSE RATED 25oC 100µs
(Continued)
1000 (L)(IAS)/(1.3*RATED BVDSS VDD) (L/R)ln[(IAS*R)/(1.3*RATED VDD)
DRAIN CURRENT
STARTING 25oC STARTING 150oC
10ms
OPERATION THIS AREA LIMITED rDS(ON) DRAIN SOURCE VOLTAGE
0.001
0.01
tAV, TIME AVALANCHE (ms)
NOTE: Refer Fairchild Application Notes AN9321 AN9322. FIGURE UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE FORWARD BIAS SAFE OPERATING AREA
PULSE DURATION 80µs DUTY CYCLE 0.5%
DRAIN CURRENT
DRAIN CURRENT
175oC 25oC
-55oC
PULSE DURATION 80µs DUTY CYCLE 0.5% 25oC
GATE SOURCE VOLTAGE
DRAIN SOURCE VOLTAGE
FIGURE TRANSFER CHARACTERISTICS
FIGURE SATURATION CHARACTERISTICS
NORMALIZED DRAIN SOURCE RESISTANCE PULSE DURATION 80µs DUTY CYCLE 0.5% NORMALIZED GATE THRESHOLD VOLTAGE
VDS, 250µA
10V,
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
FIGURE NORMALIZED DRAIN SOURCE RESISTANCE JUNCTION TEMPERATURE
FIGURE NORMALIZED GATE THRESHOLD VOLTAGE JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S Typical Performance Curves
NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE 250µA CAPACITANCE (pF)
(Continued)
10000 1MHz CISS
1000
COSS
CRSS
JUNCTION TEMPERATURE (oC)
DRAIN SOURCE VOLTAGE
FIGURE NORMALIZED DRAIN SOURCE BREAKDOWN VOLTAGE JUNCTION TEMPERATURE
FIGURE CAPACITANCE DRAIN SOURCE VOLTAGE
GATE SOURCE VOLTAGE
WAVEFORMS DESCENDING ORDER:
GATE CHARGE (nC)
NOTE: Refer Fairchild Application Notes AN7254 AN7260. FIGURE GATE CHARGE WAVEFORMS CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S Test Circuits Waveforms
BVDSS VARY OBTAIN REQUIRED PEAK
0.01
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
Qg(TOT)
Qg(10) Qg(TH) Ig(REF)
Ig(REF)
FIGURE GATE CHARGE TEST CIRCUIT
FIGURE GATE CHARGE WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE SWITCHING TIME TEST CIRCUIT
FIGURE SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S PSPICE Electrical Model
.SUBCKT HUF75542P3
4.4e-9 4.2e-9 2.5e-9 DBODY DBODYMOD DBREAK DBREAKMOD DPLCAP DPLCAPMOD
2000
LDRAIN DPLCAP RLDRAIN DBREAK EBREAK MWEAK MMED MSTRO LSOURCE RSOURCE RLSOURCE RVTHRES VBAT RBREAK RVTEMP SOURCE DBODY DRAIN RSLC1 ESLC
RSLC2
LGATE GATE RLGATE EVTEMP RGATE EVTHRES
LDRAIN 1.0e-9 LGATE 2.6e-9 LSOURCE 1.1e-9 MMED MMEDMOD MSTRO MSTROMOD MWEAK MWEAKMOD RBREAK RBREAKMOD RDRAIN RDRAINMOD 5.5e-3 RGATE RLDRAIN RLGATE RLSOURCE RSLC1 RSLCMOD 1e-6 RSLC2 RSOURCE RSOURCEMOD 3.3e-3 RVTHRES RVTHRESMOD RVTEMP RVTEMPMOD S1AMOD S1BMOD S2AMOD S2BMOD
VBAT ESLC .MODEL DBODYMOD 2.5e-12 2.85e-3 TRS1 2e-3 TRS2 1e-6 3.2e-9 5.5e-8 0.6) .MODEL DBREAKMOD 2.9e- 1TRS1 3TRS2 1e-6) .MODEL DPLCAPMOD (CJO 3.4e- 1e-3 .MODEL MMEDMOD NMOS (VTO 3.06 1e-30 .MODEL MSTROMOD NMOS (VTO 1e-30 .MODEL MWEAKMOD NMOS (VTO 2.67 0.08 1e-30 .MODEL RBREAKMOD (TC1 =1.3e- 3TC2 -9e-7) .MODEL RDRAINMOD (TC1 1.1e-2 2.5e-5) .MODEL RSLCMOD (TC1 4.5e-3 1e-5) .MODEL RSOURCEMOD (TC1 .MODEL RVTHRESMOD (TC1 -2.5e-3 -1.1e-5) .MODEL RVTEMPMOD (TC1 -2.75e- 3TC2 .MODEL S1AMOD VSWITCH (RON 1e-5 .MODEL S1BMOD VSWITCH (RON 1e-5 .MODEL S2AMOD VSWITCH (RON 1e-5 .MODEL S2BMOD VSWITCH (RON 1e-5 .ENDS ROFF ROFF ROFF ROFF -6.0 VOFF= -4.5) -4.5 VOFF= -6.0) -0.5 VOFF= 0.5) VOFF= -0.5)
NOTE: further discussion PSPICE model, consult PSPICE Sub-Circuit Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written William Hepp Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
EBREAK 87.2 EVTHRES EVTEMP
RDRAIN
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S SABER Electrical Model
template huf75542p3 n2,n1,n3 electrical n2,n1,n3 iscl dp.model dbodymod 2.5e-12, 2.85e-3, 5.5, trs1 2e-3, trs2 1e-6, 3.2e-9, 5.5e-8, 0.6) dp.model dbreakmod 2.9e-1, trs1 1e-3, trs2 1e-6) dp.model dplcapmod (cjo 3.4e-9, 1e-30, 0.8, m.model mmedmod (type=_n, 3.06, 4.8, 1e-30, m.model mstrongmod (type=_n, 3.5, 1e-30, m.model mweakmod (type=_n, 2.67, 0.08, 1e-30, sw_vcsp.model s1amod (ron 1e-5, roff 0.1, -6.0, voff -4.5) DPLCAP sw_vcsp.model s1bmod (ron =1e-5, roff 0.1, -4.5, voff -6.0) sw_vcsp.model s2amod (ron 1e-5, roff 0.1, -0.5, voff 0.5) sw_vcsp.model s2bmod (ron 1e-5, roff 0.1, 0.5, voff -0.5) RSLC1 c.ca 4.4e-9 c.cb 4.2e-9 c.cin 2.5e-9 dp.dbody model=dbodymod dp.dbreak model=dbreakmod dp.dplcap model=dplcapmod i.it l.ldrain 1e-9 l.lgate 2.6e-9 l.lsource 1.1e-9
LGATE GATE RLGATE RSLC2 ISCL EVTEMP RGATE MSTRO EVTHRES RDRAIN MWEAK MMED EBREAK RSOURCE RLSOURCE RVTHRES VBAT RBREAK RVTEMP DBODY DBREAK
LDRAIN DRAIN RLDRAIN
m.mmed model=mmedmod, l=1u, w=1u m.mstrong model=mstrongmod, l=1u, w=1u m.mweak model=mweakmod, l=1u, w=1u res.rbreak 1.3e-3, -9e-7 res.rdrain 5.5e-3, 1.1e-2, 2.5e-5 res.rgate res.rldrain res.rlgate res.rlsource res.rslc1 1e-6, 4.5e-3, 1e-5 res.rslc2 res.rsource 3.3e-3, res.rvtemp -2.75e-3, res.rvthres -2.5e-3, -1.1e-5 spe.ebreak 87.2 spe.eds spe.egs spe.esg spe.evtemp spe.evthres sw_vcsp.s1a model=s1amod sw_vcsp.s1b model=s1bmod sw_vcsp.s2a model=s2amod sw_vcsp.s2b model=s2bmod v.vbat dc=1 equations (n51->n50) +=iscl iscl: v(n51,n50) 2.5))
LSOURCE
SOURCE
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
HUF75542P3, HUF75542S3S SPICE Thermal Model
T75542 CTHERM1 4.1e-3 CTHERM2 5.5e-3 CTHERM3 8.6e-3 CTHERM4 1.5e-2 CTHERM5 1.6e-2 CTHERM6 6.5e-2 RTHERM1 2.0e-4 RTHERM2 3.5e-3 RTHERM3 2.5e-2 RTHERM4 9.0e-2 RTHERM5 1.6e-1 RTHERM6 2.3e-1
RTHERM1 CTHERM1 JUNCTION
RTHERM2
CTHERM2
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model t75542 template thermal_model thermal_c ctherm.ctherm1 4.1e-3 ctherm.ctherm2 5.5e-3 ctherm.ctherm3 8.6e-3 ctherm.ctherm4 1.5e-2 ctherm.ctherm5 1.6e-2 ctherm.ctherm6 6.5e-2 rtherm.rtherm1 2.0e-4 rtherm.rtherm2 3.5e-3 rtherm.rtherm3 2.5e-2 rtherm.rtherm4 9.0e-2 rtherm.rtherm5 1.6e-1 rtherm.rtherm6 2.3e-1
RTHERM4
CTHERM4
RTHERM5
CTHERM5
RTHERM6
CTHERM6
CASE
©2001 Fairchild Semiconductor Corporation
HUF75542P3, HUF75542S3S Rev.
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