SAM87RI PRODUCT FAMILY Samsung's SAM87Ri family 8-bit single-chip
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KS86C4204/C4208/P4208
SAM87RI PRODUCT FAMILY
Samsung's SAM87Ri family 8-bit single-chip CMOS microcontrollers offers fast efficient CPU, wide range integrated peripherals, various mask-programmable sizes. address/data architecture large number bit-configurable ports provide flexible programming environment applications with varied memory requirements. Timer/counters with selectable operating modes included support real-time operations.
KS86C4204/C4208/P4208 MICROCONTROLLER
KS86C4204/C4208/P4208 single-chip 8-bit microcontroller fabricated using advanced CMOS process. built around powerful SAM87Ri core. KS86C4204/C4208/P4208 versatile microcontroller, with converter, SIO, zero-crossing detection capability used wide range general purpose applications. Stop Idle power-down modes were implemented reduce power consumption. increase on-chip register space, size internal register file logically expanded. KS86C4204/C4208/P4208 have 4-Kbyte 8-Kbyte program memory on-chip (ROM) 208-bytes general purpose register area RAM. Using SAM87Ri design approach, following peripherals were integrated with SAM87Ri core: Four configurable ports pins) Nine interrupt sources with vector interrupt level 8-bit timer/counter with various operating modes Analog digital converter with input channels 10-bit resolution synchronous module module 12-bit output
ideal wide range electronic applications requiring simple timer/counter, PWM, ADC, SIO, IIC, capture functions. KS86C4204/C4208/P4208 available 28/32-pin 30-pin SDIP package.
KS86P4208 (One Time Programmable) version KS86C4204/C4208 microcontroller. KS86P4208 on-chip 8-Kbyte one-time-programmable EPROM instead masked ROM. KS86P4208 fully compatible with KS86C4204/C4208, function, D.C. electrical characteristics configuration.
KS86C4204/C4208/P4208
FEATURES
SAM87RI core Timer/Counters Memory 208-byte general purpose register area (RAM) 4K/8K byte internal program memory (ROM) module Instruction instructions SAM87RI core provides SAM87 core instruction except word-oriented instruction, multiplication, division, some one-byte instruction 12-bit 2-ch (Max: 250KHz) 6-bit base 6-bit extension frame 8-bit timer/counter 8-bit basic timer watchdog function 8-bit timer/counter with three operating mode 8-bit timer/counter
Converter analog input pins 10-bit conversion resolution
Instruction Execution Time fosc(minimum)
Buzzer Frequency Range Interrupts interrupt sources vector interrupt level Oscillator Freqeuncy General Four ports (total 24pins) programmable ports 1-MHz 16-MHz external crystal oscillator Maximum 16-MHz clock 4MHz(typ) signal generated
Operating Temperature Range 40°C 85°C
Serial synchronous serial module Selectable transmit receive rates
Operating Voltage Range (LVD) LVD)
Multi-Master IIC-Bus Serial peripheral interface
Interface Protocol Spec Serial
Zero-Crossing Detection Circuit Zero crossing detection circuit that generates digital signal synchronism with signal input
Package Types KS86C4204/C4208 32-pin SOP-450 LVD) 30-pin SDIP-400 LVD) 28-pin SOP-375
Built-in reset Circuit (LVD) voltage detector safe reset
KS86C4204/C4208/P4208
BLOCK DIAGRAM
P0.0-P0.7 SCK,SO, AD8-AD1
P1.0-P1.3 BUZ, INT0,
Basic Timer
Port
Port
XOUT (CAP) T0(PWM)
Port Interrupt Control Port P2.0-P2.7 AD0-AD7
Timer
Timer
Port
P3.0-P3.3
AD0-AD1
SAM87RI
P1.1/BUZ
P2.7/SCLK P2.6/SDAT P0.0/SCK P0.1/SO P0.2/SI
P0.7/PWM0 P1.3/PWM
4K/8K
208-Byte Register File
Figure 1-1. Block Diagram
KS86C4204/C4208/P4208
ASSIGNMENTS
XOUT TEST P0.1/SO P0.0/SCK
RESET
P3.0 P3.2 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5
KS86C4204 /C4208 32-SOP (Top View)
P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P3.3 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT
Figure 1-2. Assignment Diagram (32-Pin Package)
KS86C4204/C4208/P4208
ASSIGNMENTS (Continued)
XOUT TEST P0.1/SO P0.0/SCK
RESET
P3.0 P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5
KS88C4204 /C4208 30-SDIP (Top View)
P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P3.1 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT
Figure 1-3. Assignment Diagram (30-Pin SDIP Package)
XOUT TEST P0.1/SO P0.0/SCK
RESET
P2.0/AD0 P2.1/AD1 P2.2/AD2 P2.3/AD3 P2.4/AD4 P2.5/AD5
KS88C4204 /C4208 28-SOP (Top View)
P0.2/SI P0.3/CLO P0.4/AD8 P0.5/AD9 P0.6/AD10 P0.7/AD11/PWM0 P1.0/T0/ZCD P1.1/BUZ P1.2/INT0 P1.3/INT1/PWM1 P2.7/AD7/SCLK P2.6/AD6/SDAT
Figure 1-4. Assignment Diagram (28-Pin Package)
KS86C4204/C4208/P4208
DESCRIPTIONS
Table 1-1. KS86C4204/C4208/P4208 Descriptions Names P0.0-P0.7 Type Description Bit-programmable port Schmitt trigger input push-pull, open-drain output. Pull-up resistors assignable software. Bit-programmable port Schmitt trigger input push-pull output. Pull-up resistors assignable software. Port pins also used alternative functions. Bit-programmable port Schmitt trigger input push-pull, open drain output. Pull resistors assignable software. Port also used external interrupt, input. Push-pull open-drain output port. Pull-up resistors assignable software. Crystal/ceramic, oscillator signal system clock. System RESET signal input pin. Test signal input (for factory only: must connected VSS) converter reference voltage input ground Voltage input ground Serial interface clock input output Serial data output Serial data output System clock output port CLOCK DATA Hz-20 frequency output buzzer sound. Zero crossing detector input Timer capture input 10-bit output External interrupt input 12-bit output converter input Type Share Pins SCK,SO,SI CLO, AD8-AD11 T0/ZCD INT0 INT1 AD0-AD7
P1.0-P1.3
P2.0-P2.7
P3.0-P3.3 XIN, XOUT RESET TEST AVREF, AVSS VDD, SCLK SDAT INT0 INT1 PWM0 PWM1 AD0-AD1
P0.0 P0.1 P0.2 P0.3 P2.7 P2.6 P1.1 P1.0 P1.0 P1.2 P1.3 P0.7 P1.3 P2.0-P2.7 P0.4-P0.7
KS86C4204/C4208/P4208
CIRCUITS
P-Channel N-Channel Data
P-Channel
Output DIsable
N-Channel
Figure 1-5. Circuit Type
Last Developing: 99.02.02
Figure 1-7. Circuit Type
Pull-Up Resistor Resistor Enable Data Output DIsable Pull-up Resistor P-Channel
Circuit Type
Data
Figure 1-6. Circuit Type
Figure 1-8. Circuit Type
KS86C4204/C4208/P4208
Pull-up Resistor
P-CH Data Output Disable N-CH
Pull-up Enable
Data Output Disable
Pull-up Enable
Input
Figure 1-9. Circuit Type
Figure 1-11. Circuit Type
Pull-up Resistor
P-CH Data Output Disable N-CH
Pull-up Enable
Input Analog Input
Figure 1-10. Circuit Type
KS86C4204/C4208/P4208
ADDRESS SPACES
ADDRESS SPACES
OVERVIEW
KS86C4204/C4208/P4208 microcontroller kinds address space: Internal program memory (ROM) Internal register file 13-bit address supports program memory operations. separate 8-bit register carries addresses data between internal register file. KS86C4204/C4208/P4208 have 4-Kbytes 8-Kbytes mask-programmable on-chip program memory: which configured Internal mode, 4-Kbyte internal program memory used. KS86C4204/C4208/P4208 microcontroller general-purpose registers internal register file. Forty-four bytes register file mapped system peripheral control functions.
ADDRESS SPACES
KS86C4204/C4208/P4208
PROGRAM MEMORY (ROM)
Normal Operating Mode KS86C4204/C4208/P4208 have 4-Kbytes (locations 0H-0FFFH) 8-Kbytes (locations 0H-1FFFH) internal mask-programmable program memory. first 2-bytes (0000H-0001H) interrupt vector address. Unused locations (0002H-00FFH) used normal program memory. program reset address 0100H.
(DECIMAL) 8,181 8-Kbyte Program Memory Area
(HEX) 1FFFH
4,095
(HEX) 0FFFH 4-Kbyte Program Memory Area
Program start
0100H 0002H 0001H 0000H
Interrupt Vector
Figure 2-1. Program Memory Address Space
KS86C4204/C4208/P4208
ADDRESS SPACES
REGISTER ARCHITECTURE
upper 64-bytes KS86C4204/C4208/P4208's internal register file addressed working registers, system control registers peripheral control registers. lower 192-bytes internal register file(00H-BFH) called general purpose register space. total addressable register space thereby 256-bytes. 252registers this space accessed; available general-purpose use. many SAM87Ri microcontrollers, addressable area internal register file further expanded additional register pages general purpose register space (00H-BFH). This register file expansion implemented KS86C4204/C4208/P4208, however. specific register types area bytes) that they occupy internal register file summarized Table 2-1. Table 2-1. Register Type Summary Register Type system control registers Peripheral, I/O, clock control data registers General-purpose registers (including 16-bit common working register area) Total Addressable Bytes Number Bytes
ADDRESS SPACES
KS86C4204/C4208/P4208
Peripheral Control Registers Bytes Common Area System Registers Working Registers
Bytes (Page
General Pupose Registers Stack Area (page
Figure 2-2. Internal Register File Organization
KS86C4204/C4208/P4208
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H-CFH)
SAM87Ri register architecture provides efficient method working register addressing that takes full advantage shorter instruction formats reduce execution time. This 16-byte address range called common area. That locations this area used working registers operations that address location page register file. Typically, these working registers serve temporary buffers data operations between different pages. However, because KS86C4204/C4208/P4208 uses only page common area internal data operation. Register addressing mode used access this area Registers addressed either single 8-bit register paired 16-bit register. 16-bit register pairs, address first 8-bit register always even number address next register number. most significant byte 16-bit data always stored even-numbered register; least significant byte always stored next odd-numbered register.
Even Address
Figure 2-3. 16-Bit Register Pairs
PROGRAMMING Addressing Common Working Register Area
following examples show, should access working registers common area, locations C0H-CFH, using working register addressing mode only. Examples: 0C2H,40H Invalid addressing mode!
working register addressing instead: R2,40H (C2H) value location
0C3H,#45H
Invalid addressing mode!
working register addressing instead: R3,#45H (C3H)
ADDRESS SPACES
KS86C4204/C4208/P4208
SYSTEM STACK
KS86-series microcontrollers system stack subroutine calls returns store data. PUSH instructions used control system stack operations. KS86C4204/C4208/P4208 architecture supports stack operations internal register file. Stack Operations Return addresses procedure calls interrupts data stored stack. contents saved stack CALL instruction restored instruction. When interrupt occurs, contents FLAGS register pushed stack. IRET instruction then pops these values back their original locations. stack address always decremented before push operation incremented after operation. stack pointer (SP) always points stack frame stored stack, shown Figure 2-4.
High Address
Stack
Stack
FLAGS Stack Contents After Interrupt
Stack Contents After Call Instruction
Address
Figure 2-4. Stack Operations Stack Pointer (SP) Register location contains 8-bit stack pointer (SP) that used system stack operations. After reset, value undetermined. Because only internal memory space implemented KS86C4204/C4208/P4208, must initialized 8-bit value range 00H-0C0H. NOTE case Stack Pointer initialized 00H, decreased when stack operation starts. This means that Stack Pointer access invalid stack area.
KS86C4204/C4208/P4208
ADDRESS SPACES
PROGRAMMING Standard Stack Operations Using PUSH
following example shows perform stack operations internal register file using PUSH instructions:
SP,#0C0H
(Normally, 0C0H initialization routine)
PUSH PUSH PUSH PUSH
Stack address 0BFH Stack address 0BEH Stack address 0BDH Stack address 0BCH
Stack address 0BCH Stack address 0BDH Stack address 0BEH Stack address 0BFH
ADDRESS SPACES
KS86C4204/C4208/P4208
NOTES
KS86C4204/C4208/P4208
ADDRESSING MODES
OVERVIEW
ADDRESSING MODES
Instructions that stored program memory fetched execution using program counter. Instructions indicate operation performed data operated Addressing mode method used determine location data operand. operands specified SAM87Ri instructions condition codes, immediate data, location register file, program memory, data memory. SAM87Ri instruction supports explicit addressing modes. these addressing modes available each instruction. addressing modes their symbols follows: Register Indirect Register (IR) Indexed Direct Address (DA) Relative Address (RA) Immediate (IM)
ADDRESSING MODES
KS86C4204/C4208/P4208
REGISTER ADDRESSING MODE Register addressing mode, operand content specified register (see Figure 3-1). Working register addressing differs from Register addressing because uses 16-byte working register space register file 4-bit register within that space (see Figure 3-2).
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
OPCODE
Point Rigister Register File Value used Instruction Execution
OPERAND
Sample Instruction: CNTR Where CNTR label 8-bit register address
Figure 3-1. Register Addressing
Register File
Program Memory 4-bit Working Register Two-Operand Instruction (Example) LSBs Point Woking Register
OPCODE
OPERAND
Sample Instruction: Where
Figure 3-2. Working Register Addressing
KS86C4204/C4208/P4208
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR) Indirect Register (IR) addressing mode, content specified register register pair address operand. Depending instruction used, actual address point register register file, program memory (ROM), external memory space (see Figures through 3-6). 8-bit register indirectly address another register. 16-bit register pair used indirectly address another memory location.
Program Memory 8-bit Register File Address One-Operand Instruction (Example)
Register File
OPCODE
Point Rigister Register File Address Operand used Instruction
ADDRESS
Value used Instruction Execution
OPERAND
Sample Instruction: @SHIFT Where SHIFT label 8-bit register address
Figure 3-3. Indirect Register Addressing Register File
ADDRESSING MODES
KS86C4204/C4208/P4208
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory Example Instruction References Program Memory REGISTER PAIR 16-Bit Address Point Program Memory
OPCODE
Point Rigister Pair
Program Memory
Sample Instructions: CALL @RR2 @RR2
Value used Instruction
OPERAND
Figure 3-4. Indirect Register Addressing Program Memory
KS86C4204/C4208/P4208
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory 4-bit Working Register Address LSBs Point Woking Register
OPCODE
OPERAND
Sample Instruction:
Value used Instruction
OPERAND
Figure 3-5. Indirect Working Register Addressing Register File
ADDRESSING MODES
KS86C4204/C4208/P4208
INDIRECT REGISTER ADDRESSING MODE (Concluded)
Register File
Program Memory 4-bit Working Register Address OPCODE Next 3-bit Point Working Register Pair Register Pair
Example Instruction References either Program Memory Data Memory
Program Memory Data Memory Value used Instruction
OPERAND
Sample Instructions: R5,@RR2 R3,@RR14 @RR4, Program memory access External data memory access External data memory access
Figure 3-6. Indirect Working Register Addressing Program Data Memory
KS86C4204/C4208/P4208
ADDRESSING MODES
INDEXED ADDRESSING MODE Indexed addressing mode adds offset value base address during instruction execution order calculate effective operand address (see Figure 3-7). Indexed addressing mode access locations internal register file external memory. short offset Indexed addressing mode, 8-bit displacement treated signed integer range 127. This applies external memory accesses only (see Figure 3-8). register file addressing, 8-bit base address provided instruction added 8-bit offset contained working register. external memory accesses, base address stored working register pair designated instruction. 8-bit 16-bit offset given instruction then added base address (see Figure 3-9). only instruction that supports Indexed addressing mode internal register file Load instruction (LD). instructions support Indexed addressing mode internal program memory, external program memory, external data memory, when implemented.
Register File
Value used Instruction OPERAND
Program Memory Two-Operand Instruction Example X(OFFSET) OPCODE LSBs Point Woking Register
INDEX
Sample Instruction: #BASE[R1] Where BASE 8-bit immediate value
Figure 3-7. Indexed Addressing Register File
ADDRESSING MODES
KS86C4204/C4208/P4208
INDEXED ADDRESSING MODE (Continued)
Register File Program Memory 4-bit Working Register Address X(OFFSET) OPCODE Next bits Point Woking Register Pair Register Pair 16-bit Address added Offset
Selects bits
bits Program Memory Data Memory Value used Instruction
bits
OPERAND
Sample Instructions: #04H[RR2] R4,#04H[RR2] values program address (RR2 #04H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-8. Indexed Addressing Program Data Memory with Short Offset
KS86C4204/C4208/P4208
ADDRESSING MODES
INDEXED ADDRESSING MODE (Concluded)
Program Memory XLH(OFFSET) XLL(OFFSET) OPCODE
Register File
4-bit Working Register Address
Next bits Point Woking Register Pair Selects bits
Register Pair 16-bit Address added Offset
bits Program Memory Data Memory
bits
OPERAND
Value used Instruction
Sample Instructions: #1000H[RR2] R4,#1000H[RR2] values program address (RR2 #1000H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-9. Indexed Addressing Program Data Memory with Long Offset
ADDRESSING MODES
KS86C4204/C4208/P4208
DIRECT ADDRESS MODE (DA) Direct Address (DA) mode, instruction provides operand's 16-bit memory address. Jump (JP) Call (CALL) instructions this addressing mode specify 16-bit destination address that loaded into whenever CALL instruction executed. instructions Direct Address mode specify source destination address Load operations program memory (LDC) external data memory (LDE), implemented.
Program Data Memory
Program Memory
Memory Address used
UPPER ADDR BYTE LOWER ADDR BYTE dst/src OPCODE
Selects Program Memory Data Memory: Program Memory Data Memory
Sample Instructions: R5,1234H R5,1234H values program address (1234H) loaded into register Identical operation example, except that external program memory accessed.
Figure 3-10. Direct Addressing Load Instructions
3-10
KS86C4204/C4208/P4208
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
NEXT OPCODE
Memory Address used UPPER ADDR BYTE LOWER ADDR BYTE OPCODE
Sample Instructions: CALL C,JOB1 DISPLAY Where JOB1 16-bit immediate address Where DISPLAY 16-bit immediate address
Figure 3-11. Direct Addressing Call Jump Instructions
ADDRESSING MODES
KS86C4204/C4208/P4208
RELATIVE ADDRESS MODE (RA) Relative Address (RA) mode, two's-complement signed displacement between specified instruction. displacement value then added current value. result address next instruction executed. Before this addition occurs, contains address instruction immediately following current instruction. instructions that support addressing
Program Memory
NEXT OPCODE Program Memory Address used
Current Value Current Instruction DISPLACEMENT OPCODE Signed Displacement Value
Sample Instructions: ULT,$+OFFSET Where OFFSET value range +127 -128
Figure 3-12. Relative Addressing IMMEDIATE MODE (IM) Immediate (IM) addressing mode, operand value used instruction value supplied operand field itself. Immediate addressing mode useful loading constant values into registers.
Program Memory OPERAND OPCODE
(The Operand value instruction) Sample Instruction: R0,#0AAH
Figure 3-13. Immediate Addressing
3-12
KS86C4204/C4208/P4208
CONTROL REGISTERS
CONTROL REGISTERS
OVERVIEW
this section, detailed descriptions KS86C4204/C4208/P4208 control registers presented easyto-read format. These descriptions will help familiarize with mapped locations register file. also them quick-reference source when writing application programs. System peripheral registers summarized Table 4-1. Figure illustrates important features standard register description format. Control register descriptions arranged alphabetical order according register mnemonic. More information about control registers presented context various peripheral hardware descriptions Part this manual.
CONTROL REGISTERS
KS86C4204/C4208/P4208
Table 4-1. Register RESET Status Register Name Timer counter register Timer data register Timer control register (high) Timer control register (low) Clock control register System flags register Stack pointer register special register Basic timer control register Basic timer counter Test mode control register System mode register
NOTE: mapped, `x'is Undefined
Mnemonic T0CNT T0DATA T0CONH T0CONL CLKCON FLAGS MDSREG BTCON BTCNT FTSTCON
Address Location Address
RESET Value (bit)
Locations D6H-D8H mapped. Locations reserved.
KS86C4204/C4208/P4208
CONTROL REGISTERS
Table 4-1. Register RESET Status (Continued) Register Name Port data register Port data register Port data register Port data register Timer control register Timer data register Port control register (high) Port control register (low) Port pull-up resistor enable register Port control register Port pull-up, pending register Port control register (high) Port control register (low) Port pull-up resistor enable register Port control register data register control register prescaler IIC-bus clock control register IIC-bus clock/status register IIC-bus address register IIC-bus Tx/Rx data shift register 8-bit prescaler buzzer output control register converter data register (high) converter data register (low) data register extension data register data register extension data register control register Zero crossing detection control register
NOTE: mapped, `x'is Undefined
Mnemonic Address T1CON T1DATA P0CONH P0CONL P0PUR P1CON P1PND P2CONH P2CONL P2PUR P3CON SIODATA SIOCON SIOPS ICCR ICSR IDSR BUZPS ADCON ADDATAH ADDATAL PWM0 PWM0EX PWM1 PWM1EX PWMCON ZCMOD
RESET Value (bit)
CONTROL REGISTERS
KS86C4204/C4208/P4208
number(s) that is/are appended register name addressing Name individual Register function Full Register name mnemonic
Register address (hexadecimal)
FLAGS System Flags Register
Identifier RESET Value Read/Write
Carry Flag Operation dose generate carry borrow condition Operation generates carry-out borrow into high-order bit7
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Read-only Write-only Read/write used Addressing mode modes modify register values
Description effect specific settings
RESET value notation:
used Undetermind value Logic zero Logic
number:
Figure 4-1. Register Description Format
KS86C4204/C4208/P4208
CONTROL REGISTERS
ADCON
Identifier Value Read/Write .7-.4
Converter Control Register
Converter Input Selection Bits (P2.0) (P2.1) (P2.2) (P2.3) (P2.4) (P2.5) (P2.6) (P2.7) (P0.4) (P0.5) AD10 (P0.6) AD11 (P0.7) Internally connected Internally connected Internally connected Internally connected AVREF
End-of-Conversion Status conversion progress conversion complete
.2-.
Clock Source Selection fosc/16 fosc/8 fosc/4 fosc/
Conversion Start meaning conversion start
CONTROL REGISTERS
KS86C4204/C4208/P4208
BTCON
Identifier Value Read/Write .7-.4
Basic Timer Control Register
Watchdog Timer Function Enable Disable watchdog timer function Enable watchdog timer function Others
.3-.2
Basic Timer Input Clock Selection Bits fosc/4096 fosc/1024 fosc/128 Invalid setting
Basic Timer 8-bit Counter Clear (note) effect Clear basic timer counter value
Basic Timer Divider Clear (note) effect Clear both dividers
NOTE: When write BTCON.0 BTCON.1), basic timer counter basic timer divider) cleared. then cleared automatically "0".
KS86C4204/C4208/P4208
CONTROL REGISTERS
BUZPS
Identifier Value Read/Write
6-Bit Prescaler Buzzer Output
Buzzer Output Enable Disable buzzer output (buzzer off) Enable buzzer output (buzzer
Buzzer Clock Selection Divided (fx/256) Divided (fx/64)
.5-.0
6-Bit Prescaler
divided [fx/(256 64)] divided [fx/(256 64)] divided [fx/(256 64)] divided [fx/(256 64)] divided 2x(n+1) [fx/(256 64)] divided [fx/(256 64)]
CONTROL REGISTERS
KS86C4204/C4208/P4208
CLKCON
Identifier Value Read/Write
System Clock Control Register
Oscillator Wake-up Function Enable Enable main system oscillator wake-up function Disable main system oscillator wake-up function
used KS86C4204/C4208/P4208 Clock (System Clock) Selection Bits Divide (fosc/16) Divide (fosc/8) Divide (fosc/2) Non-divided clock (fosc)
.2-.0
used KS86C4204/C4208/P4208
NOTES: After reset, slowest clock (divided selected system clock. select faster clock speeds, load appropriate values CLKCON.3 CLKCON.4. fosc means oscillator frequency
KS86C4204/C4208/P4208
CONTROL REGISTERS
FLAGS
Identifier Value Read/Write
System Flags Register
Carry Flag Operation does generate carry borrow condition Operation generates carry-out borrow into high-order
Zero Flag Operation result non-zero value Operation result zero
Sign Flag Operation generates positive number (MSB "0") Operation generates negative number (MSB "1")
Overflow Flag Operation result Operation result
.3-.0
used KS86C4204/C4208/P4208
CONTROL REGISTERS
KS86C4204/C4208/P4208
ICCR
Identifier Value Read/Write
Multi-master IIC-Bus Clock Control Register
Acknowledgement Enable Acknowledgement disable mode Acknowledgement enable mode
Clock Selection fosc/16 fosc/512
Multi-master IIC-Bus Tx/Rx Interrupt Enable Disable interrupt Enable interrupt
Multi-master IIC-Bus Tx/Rx Interrupt pending When write this when ICSR.4 When 1-byte transmit/receive terminated, general call slave address match occurred, arbitration lost
.3-.0
ICCR.3-0: Transmit Clock 4-Bit Prescaler Bits clock IICLK/CCR<3:0> where, IICLK fosc/16 when IICR.6 "0", IICLK fosc/512 when ICCR.6
4-10
KS86C4204/C4208/P4208
CONTROL REGISTERS
ICSR
Identifier Value Read/Write .7-.6
Multi-master IIC-Bus Control/Status Register
Master/Slave Tx/Rx Mode Selection Bits Slave receiver mode (Default mode) Slave transmitter mode Master receiver mode Master transmitter mode
IIC-Bus Busy IIC-bus busy Stop condition generation IIC-bus busy (when read) Stop condition generation (when write)
IIC-bus Interface Module Enable Disable IIC-bus data transmit/receive Enable IIC-bus data transmit/receive
Arbitration Lost This when serial interface, master transmit mode, loses arbitration procedure. slave mode this flag when ICCR.5 ICSR.2
Address Match When Start Stop Reset When received slave address matches register general call
General Call When Start/Stop condition generated When received slave address "00000000" (general call)
Received Acknowledge received received
CONTROL REGISTERS
KS86C4204/C4208/P4208
P0CONH
Identifier Value Read/Write .7-.6
Port Control Register (High Byte)
Port P0.7/AD11/PWM0 Configuration Bits Schmitt trigger input converter input (AD11) Schmitt trigger input Push-pull output Alternative function (PWM0 Output)
.5-.4
Port P0.6/AD10 Configuration Bits Schmitt trigger input converter input (AD10) Schmitt trigger input Push-pull output Open-drain output
.3-.2
Port P0.5/AD9 Configuration Bits Schmitt trigger input converter input (AD9) Schmitt trigger input Push-pull output Open-drain output
.1-.0
Port P0.4/AD10 Configuration Bits Schmitt trigger input converter input (AD8) Schmitt trigger input Push-pull output Open-drain output
4-12
KS86C4204/C4208/P4208
CONTROL REGISTERS
P0CONL
Identifier Value Read/Write .7-.6
Port Control Register (Low Byte)
Port P0.3/CLO Configuration Bits Schmitt trigger input Alternative function; ouput Push-pull output Open-drain output
.5-.4
Port P0.2/SI Configuration Bits Schmitt trigger input; input Schmitt trigger input; input Push-pull output Open-drain output
.3-.2
Port P0.1/SO Configuration Bits Schmitt trigger input Alternative function; output Push-pull output Open-drain output
.1-.0
Port P0.0/SCK Configuration Bits Schmitt trigger input; input Alternative function; output Push-pull output Open-drain output
4-13
CONTROL REGISTERS
KS86C4204/C4208/P4208
P0PUR
Identifier Value Read/Write
Port Pull-up Resistor Enable Register
Port P0.7 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.6 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.5 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.4 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.3 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.2 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.1 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P0.0 Pull-up Resistor Enable Disable pull-up Enable pull-up
4-14
KS86C4204/C4208/P4208
CONTROL REGISTERS
P1CON
Identifier Value Read/Write
Port Control Register
Port P1.3/INT1/PWM1 Configuration Bits Schmitt trigger input; INT1 interrupt disabled Schmitt trigger input; Interrupt falling edge Push-pull output Alternative function (PWM1 output)
Port P1.2/INT0 Configuration Bits Schmitt trigger input; INT0 interrupt disabled Schmitt trigger input; Interrupt falling edge Push-pull output Schmitt trigger input; Interrupt rising edge
Port P1.1/BUZ Configuration Bits Schmitt trigger Schmitt trigger input Push-pull output Alternative function (BUZ output)
Port P1.0 /ZCD Configuration Bits Schmitt trigger input Capture input) input; enable Push-pull output Alternative function output; match PWM)
4-15
CONTROL REGISTERS
KS86C4204/C4208/P4208
P1PND
Identifier Value Read/Write
Port Interrupt Pending Register
Port P1.3/INT1/PWM1 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P1.2/INT0 Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P1.1/BUZ Pull-up Resistor Enable Disable pull-up Enable pull-up
Port P1.0/T0/ZCD Pull-up Resistor Enable Disable pull-up Enable pull-up
Port 1,P1.3/INT1/PWM1 Open-drain Enable Push pull output mode Open-drain output
Port P1.1/BUZ Open-drain Enable Push pull output mode Open-drain output
Port P1.3/INT1 Interrupt Pending interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)/No effect (when write)
Port P1.2/INT0 Interrupt Pending interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)/No effect (when write)
4-16
KS86C4204/C4208/P4208
CONTROL REGISTERS
P2CONH
Identifier Value Read/Write
Port Control Register (High Byte)
Port P2.7/AD7/SCLK Configuration Bits Schmitt trigger input converter input (AD7); Schmitt trigger input Push-pull output Alternative function (IIC Clock pin); Open-drain type
Port P2.6/AD6/SDAT Configuration Bits Schmitt trigger input converter input (AD6); Schmitt trigger input Push-pull output Alternative function (IIC Data pin); Open-drain type
Port P2.5/AD5 Configuration Bits Schmitt trigger input converter input (AD5); Schmitt trigger input Push-pull output Open-drain output
Port P2.4/AD4 Configuration Bits Schmitt trigger input converter input (AD4); Schmitt trigger input Push-pull output Open-drain output
4-17
CONTROL REGISTERS
KS86C4204/C4208/P4208
P2CONL
Identifier Value Read/Write
Port Control Register (Low Byte)
Port P2.3/AD3 Configuration Bits Schmitt trigger input converter input (AD3); Schmitt trigger input Push-pull output Open-drain output
Port P2.2/AD2 Configuration Bits Schmitt trigger input converter input (AD2); Schmitt trigger input Push-pull output Open-drain output
Port P2.1/AD1Configuration Bits Schmitt trigger input converter input (AD1); Schmitt trigger input Push-pull output Open-drain output
Port P2.0/AD0 Configuration Bits Schmitt trigger input converter input (AD0); Schmitt trigger input Push-pull output Open-drain output
4-18
KS86C4204/C4208/P4208
CONTROL REGISTERS
P2PUR
Identifier Value Read/Write
Port Pull-up Resistor Enable Register
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
Port Pull-up Resistor Enable Disable pull-up Enable pull-up
4-19
CONTROL REGISTERS
KS86C4204/C4208/P4208
P3CON
Identifier Value Read/Write
Port Control Register
Port P3.3 Configuration Bits Push-pull output Push-pull output Open-drain output; Pull-up resistor disable Open-drain output; Pull-up resistor enable
Port P3.2 Configuration Bits Push-pull output Push-pull output Open-drain output; Pull-up resistor disable Open-drain output; Pull-up resistor enable
Port P3.1 Configuration Bits Push-pull output Push-pull output Open-drain output; Pull-up resistor disable Open-drain output; Pull-up resistor enable
Port P3.0 Configuration Bits Push-pull output Push-pull output Open-drain output; Pull-up resistor disable Open-drain output; Pull-up resistor enable
4-20
KS86C4204/C4208/P4208
CONTROL REGISTERS
PWMCON
Identifier Value Read/Write .7-.6
Control Register
Input Clock Slection fosc/256 fosc/64 fosc/8 fosc/
Data Reload Interval Selection Reload from 12-bit counter overflow Reload from 6-bit counter overflow
Data Reload Interval Selection Reload from 12-bit counter overflow Reload from 6-bit counter overflow
Counter Clear effect Clear 12-bit counter (when write)
Counter Enable Stop counter Start (Resume counting)
Overflow Interrupt Enable (12-bit Counter Overflow) Disable interrupt Enable interrupt
12-Bit Counter Overflow Interrupt Pending interrupt pending Clear pending (when write) Interrupt pending
CONTROL REGISTERS
KS86C4204/C4208/P4208
SIOCON
Identifier Value Read/Write
Serial Module Control Registers
Shift Clock Selection Interval clock (P.S Clock) External clock (SCK)
Data Direction Control MSB-first mode LSB-first mode
Mode Selection Receive-only mode Transmit/Receive mode
Shift Clock Edge Selection falling edges, rising edges. rising edges, falling edges.
Counter Clear Shift Start action Clear 3-bit counter start shifting
Shift Operation Enable Disable shift clock counter Enable shift clock counter
Interrupt Enable Disable interrupt Enable interrupt
Interrupt Pending interrupt pending Clear pending condition (when write) Interrupt pending
4-22
KS86C4204/C4208/P4208
CONTROL REGISTERS
Identifier Value Read/Write .7-.3
System Mode Register
used KS86C4204/C4208/P4208 Global Interrupt Enable (note) Disable interrupt instruction) Enable interrupt Instruction)
Page Selection Bits page page (Not used KS86C4204/C4208/P4208) page (Not used KS86C4204/C4208/P4208) page (Not used KS86C4204/C4208/P4208)
NOTE: Following reset, enable global interrupt processing executing instruction (not writing SYM.2).
4-23
CONTROL REGISTERS
KS86C4204/C4208/P4208
T0CONH
Identifier Value Read/Write .7-.1
TIMER Control Register (High Byte)
used KS86C4204/C4208/P4208 Timer Overflow Interrupt Pending (overflow interrupt) interrupt pending (when read) Clear Pending (when write) Interrupt pending (when read)
4-24
KS86C4204/C4208/P4208
CONTROL REGISTERS
T0CONL
Identifier Value Read/Write
TIMER Control Register (Low Byte)
Timer Input Clock Selection Bits fosc/4096 fosc/256 fosc/8 fosc/
Timer Operating Mode Selection Bits Interval mode Capture mode (capture rising edge, counter running, OVF) Capture mode (capture falling edge, counter running, OVF) mode (OVF interrupt occur)
Timer Counter Clear effect Clear timer counter (when write)
Timer Overflow Interrupt Enable Disable overflow interrupt Enable overflow interrupt
Timer Interrupt Enable Disable interrupt Enable interrupt
Timer Interrupt Pending (Capture Match Interrupt) interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)
NOTE: When write T0CONL.3 timer counter cleared. then cleared automatically "0".
4-25
CONTROL REGISTERS
KS86C4204/C4208/P4208
T1CON
Identifier Value Read/Write
Timer Control Register
Timer Counter Control Disable operation Enable counter operation
Timer Input Clock Selection Bits fosc/4096 fosc/1024 fosc/512 fosc/256 fosc/128 fosc/32
Timer Counter Automatic Clear Enable Disable Enable clear signal clear timer counter
Timer Counter Clear Enable effect Clear timer counter (when write)
Timer Interrupt Enable Disable interrupt Enable interrupt
Timer Interrupt Pending interrupt pending Clear pending (when write) Interrupt pending
4-26
KS86C4204/C4208/P4208
CONTROL REGISTERS
ZCMOD
Identifier Value Read/Write .7-.5
Zero Crossing Detection Control Register
used KS86C4204/C4208/P4208 Operation Enable Disable operation Enable operation
Interrupt Mode Selection Bits Interrupt falling edge Interrupt rising edge Interrupt both edge used
Interrupt Enable Disable interrupt Enable interrupt
Interrupt Pending interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)
4-27
CONTROL REGISTERS
KS86C4204/C4208/P4208
NOTES
4-28
KS86C4204/C4208/P4208
INTERRUPT STRUCTURE
INTERRUPT STRUCTURE
OVERVIEW
SAM87Ri interrupt structure basic components: vector, sources. number interrupt sources serviced through interrupt vector which assigned address 0000H.
VECTOR
SOURCES
0000H 0001H
NOTES: SAM87Ri interrupt only vector address (0000H-0001H). number value expandable.
Figure 5-1. KS86-Series Interrupt Type INTERRUPT PROCESSING CONTROL POINTS Interrupt processing controlled ways: either globally, specific interrupt level source. system-level control points interrupt structure therefore: Global interrupt enable disable instructions) Interrupt source enable disable settings corresponding peripheral control register(s) ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, system mode register, (DFH), used enable disable interrupt processing. SYM.2 enable disable global interrupt processing respectively, modifying SYM.2. Enable Interrupt (EI) instruction must included initialization routine that follows reset operation order enable interrupt processing. Although manipulate SYM.2 directly enable disable interrupts during normal operation, recommend that instructions this purpose.
INTERRUPT STRUCTURE
KS86C4204/C4208/P4208
INTERRUPT PENDING FUNCTION TYPES When interrupt service routine executed, application program's service routine must clear appropriate pending before return from interrupt subroutine (IRET) occurs. INTERRUPT PRIORITY Because there interrupt priority register SAM87Ri, order service determined sequence source which executed interrupt service routine.
"EI" Instruction Execution RESET Source Interrupts Source Interrupts Enable
Interrupt Pending Register
Interrpt priority determind software polling method Global Interrupt Control (EI, instruction)
Vector Interrupt Cycle
Figure 5-2. Interrupt Function Diagram
KS86C4204/C4208/P4208
INTERRUPT STRUCTURE
INTERRUPT SOURCE SERVICE SEQUENCE interrupt request polling servicing sequence follows: source generates interrupt request setting interrupt request pending "1". generates interrupt acknowledge signal. service routine starts source's pending flag cleared software. Interrupt priority must determined software polling method. INTERRUPT SERVICE ROUTINES Before interrupt request serviced, following conditions must met: Interrupt processing must enabled (EI, SYM.2 "1") Interrupt must enabled interrupt's source (peripheral control register) above conditions met, interrupt request acknowledged instruction cycle. then initiates interrupt machine cycle that completes following processing sequence: Reset (clear "0") global interrupt enable register (DI, SYM.2 "0") disable subsequent interrupts. Save program counter status flags stack. Branch interrupt vector fetch service routine's address. Pass control interrupt service routine. When interrupt service routine completed, Interrupt Return instruction (IRET) occurs. IRET restores status flags sets SYM.2 (EI), allowing process next interrupt request. GENERATING INTERRUPT VECTOR ADDRESSES interrupt vector area contains address interrupt service routine. Vectored interrupt processing follows this sequence: Push program counter's low-byte value stack. Push program counter's high-byte value stack. Push FLAGS register values stack. Fetch service routine's high-byte address from vector address 0000H. Fetch service routine's low-byte address from vector address 0001H. Branch service routine specified 16-bit vector address.
INTERRUPT STRUCTURE
KS86C4204/C4208/P4208
KS86C4204/C4208/P4208 INTERRUPT STRUCTURE KS86C4204/C4208/P4208 microcontroller nine peripheral interrupt sources: Timer match/capture interrupt Timer overflow interrupt Timer match interrupt Zero-cross detection external interrupts port P1.2-P1.3 interrupt overflow interrupt IIC-bus Tx/Rx interrupt
VECTOR
ENABLE/DISABLE PENDING BITS T0CONL.0 T0CONL.1 T0CONH.0 T0CONL.2 T1CON.0 T1CON.1 ZCMOD.0 ZCMOD.1 P1PND.0 P1CON.1-0 P1PND.1 SYM.2 (EI, P1CON.3-2 SIOCON.0 SIOCON.1 PWNCON.0 PWNCON.1 ICCR.4 ICCR.5
SOURCES Timer Match Capture Timer Overflow Timer Match Zero-cross Detect P1.2 External Interrupt P1.3 External Interrupt Interrupt Overflow Interrupt Tx/Rx Interrupt
0000H 0001H
Figure 5-3. KS86C4204/C4208/P4208 Interrupt Structure
KS86C4204/C4208/P4208
CLOCK CIRCUIT
OVERVIEW
CLOCK CIRCUIT
oscillation source provides typical clock KS86C4204/C4208/P4208. internal capacitor supports oscillator circuit. external crystal ceramic oscillation source provides maximum clock. XOUT pins connect oscillation source on-chip clock circuit. Simplified oscillator crystal/ceramic oscillator circuits shown Figures 7-2.
CXIN KS86C4204 /C4208/P4208
KS86C4204 /C4208/P4208 XOUT
XOUT
Figure 7-1. Main Oscillator Circuit Oscillator with Internal Capacitor)
Figure 7-2. Main Oscillator Circuit (Crystal/Ceramic Oscillator)
MAIN OSCILLATOR LOGIC increase processing speed reduce clock noise, non-divided logic implemented main oscillator circuit. this reason, very high resolution waveforms (square signal edges) must generated order efficiently process logic operations. CLOCK STATUS DURING POWER-DOWN MODES power-down modes, Stop mode Idle mode, affect clock oscillation follows: Stop mode, main oscillator "freezes", halting peripherals. contents register file current system register values retained. Stop mode released, oscillator started, reset operation external interrupt with RC-delay noise filter (for KS86C4204/C4208/P4208, INT0-INT1). Idle mode, internal clock signal gated CPU, interrupt control timer. current status preserved, including stack pointer, program counter, flags. Data register file retained. Idle mode released reset interrupt (external internally-generated).
CLOCK CIRCUIT
KS86C4204/C4208/P4208
SYSTEM CLOCK CONTROL REGISTER (CLKCON) system clock control register, CLKCON, located location D4H. read/write addressable following functions: Oscillator wake-up function enable/disable (CLKCON.7) Oscillator frequency divide-by value: non-divided, (CLKCON.4 CLKCON.3) CLKCON register controls whether external interrupt used trigger Stop mode release (This called "IRQ wake-up" function). wake-up enable CLKCON.7. After reset, external interrupt oscillator wake-up function enabled, main oscillator activated, fOSC/16 (the slowest clock speed) selected clock. necessary, then increase clock speed fosc, fosc/2 fosc/8.
SYSTEM CLOCK CONTOL REGISTER (CLKCON) D4H,
Oscillator wake-up enable bit: Enable main system oscillator wake-up function power down mode Disable main system oscillator wake-up function power down mode
used KS86C4204/C4208/P4208 Divide-by selection bits clock frequency: fosc/16 fosc/8 fosc/2 fosc(non-divided)
used KS86C4204/C4208/P4208
Figure 7-3. System Clock Control Register (CLKCON)
KS86C4204/C4208/P4208
CLOCK CIRCUIT
Stop Instruction Oscillator Stop MAIN Oscillator Wake-up NOISE FILTER 1/16
CLKCON.3,.4
CLOCK P0.3/CLO P0CONL
CLKCON.7
NOTE: external interrupt with RC-delay nosie fillter used release Stop mode "wake-up" main ascillator KS86C4204/C4208/P4208, INT0-INT1 external interrupts interrupt this type.
Figure 7-4. System Clock Circuit Diagram
CLOCK CIRCUIT
KS86C4204/C4208/P4208
NOTES
KS86C4204/C4208/P4208
RESET POWER-DOWN
SYSTEM RESET
OVERVIEW power-on reset
POWER-DOWN
KS86C4204/C4208/P4208 RESET four ways:
external reset input pulled digital watchdog peripheral timing Voltage Detection (LVD) During power-on reset, voltage High level RESET forced level. RESET signal input through Schmitt trigger circuit where then synchronized with clock. This bring KS86C4204/C4208/P4208 into known operating status. ensure correct start-up, user should take care that reset signal released before level sufficient allow operation chosen frequency. must held level minimum time interval after power supply comes within tolerance order allow time internal clock oscillation stabilize. minimum required oscillation stabilization time reset approximately 6.55 216/fosc, fosc MHz). When reset occurs during normal operation (with both High level), signal forced reset operation starts. system peripheral control registers then their default hardware reset values (see Table 8-1). provides watchdog timer function order ensure graceful recovery from software malfunction. watchdog timer refreshed before end-of-counter condition (overflow) reached, internal reset will activated. on-chip Voltage Detector, features static Reset when supply voltage below reference value (Typ. Thanks this feature, external reset circuit removed while keeping application safety. long supply voltage below reference value, there internal static RESET. start only when supply voltage rises over reference value. NOTE program duration oscillation stabilization interval, must make appropriate settings basic timer control register, BTCON, before entering Stop mode. Also, want basic timer watchdog function (which causes system reset basic timer counter overflow occurs), disable writing "1010B" upper nibble BTCON.
RESET POWER-DOWN
KS86C4204/C4208/P4208
Initialization Sequence following sequence events occurs during reset operation: interrupts disabled. watchdog function (basic timer) enabled. Ports input mode pull-up resistors disabled. Peripheral control data registers disabled reset their initial values (See Table 8-1). program counter loaded with reset address, 0100H. When programmed oscillation stabilization time interval elapsed, address stored location 0100H (and 0101H) fetched executed.
RESET
Internal RESET Watchdog RESET RESET
Figure 8-1. Reset Block Diagram
Oscillation Stabilization wait time (6.55ms/at MHz)
RESET Input
Normal Mode Power-Down Mode
RESET Operation
Idle Mode
Operation Mode
Figure 8-2. Timing Oscillation Stabilization after RESET
KS86C4204/C4208/P4208
RESET POWER-DOWN
POWER-DOWN MODES
STOP MODE Stop mode invoked instruction STOP (opcode 7FH). Stop mode, operation peripherals halted. That on-chip main oscillator stops supply current reduced less than system functions halted when clock "freezes", data stored internal register file retained. Stop mode released ways: signal external interrupt. Using Release Stop Mode
Stop mode released when signal released returns High level. system peripheral control registers then reset their default values contents data registers retained. reset operation automatically selects slow clock (fosc/16) because CLKCON.3 CLKCON.4 cleared "00B". After oscillation stabilization interval elapsed, executes system initialization routine fetching 16-bit address stored locations 0100H 0101H. Using External Interrupt Release Stop Mode Only external interrupts with RC-delay noise filter circuit used release Stop mode (Clock-related external interrupts cannot used). External interrupts INT0-INT1 KS86C4204/C4208/P4208 interrupt structure meet this criteria. Note that when Stop mode released external interrupt, current values system peripheral control registers changed. When interrupt release Stop mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. external interrupt Stop mode release, also program duration oscillation stabilization interval. this, must make appropriate control clock settings before entering Stop mode. external interrupt serviced when Stop mode release occurs. Following IRET from service routine, instruction immediately following that initiated Stop mode executed. IDLE MODE Idle mode invoked instruction IDLE (opcode 6FH). Idle mode, operations halted while select peripherals remain active. During Idle mode, internal clock signal gated CPU, interrupt logic timer/counters. Port pins retain mode (input output) they time Idle mode entered. There ways release Idle mode: Execute reset. system peripheral control registers reset their default values contents data registers retained. reset automatically selects slow clock (fosc/16) because CLKCON.3 CLKCON.4 cleared "00B". interrupts masked, reset only release Idle mode. Activate enabled interrupt, causing Idle mode released. When interrupt release Idle mode, CLKCON.3 CLKCON.4 register values remain unchanged, currently selected clock value used. interrupt then serviced. Following IRET from service routine, instruction immediately following that initiated Idle mode executed. NOTES Only external interrupts that clock-related used release stop mode. release Idle mode, however, type interrupt (that internal external) used. Before enter STOP IDLE mode, (P1CON) (P0CONH, P2CONH, P2CONL) must disabled. Otherwise, STOP IDLE current will increased significantly.
RESET POWER-DOWN
KS86C4204/C4208/P4208
HARDWARE RESET VALUES
Table lists values system registers, peripheral control registers, peripheral data registers following reset operation normal operating mode. shows reset value logic logic zero, respectively. means that value undefined following reset. dash ("-") means that either used mapped.
Table 8-1. Register RESET Status Register Name Timer counter register Timer data register Timer control register (high) Timer control register (low) Clock control register System flags register Stack pointer register special register Basic timer control register Basic timer counter Test mode control register System mode register
NOTE: mapped, `x'is Undefined
Mnemonic T0CNT T0DATA T0CONH T0CONL CLKCON FLAGS MDSREG BTCON BTCNT FTSTCON
Address Location Address
RESET Value (bit)
Locations D6H-D8H mapped. Locations reserved.
KS86C4204/C4208/P4208
RESET POWER-DOWN
Table 8-1. Register RESET Status (Continued) Register Name Port data register Port data register Port data register Port data register Timer control register Timer data register Port control register (high) Port control register (low) Port pull-up resistor enable register Port control register Port pull-up, pending register Port control register (high) Port control register (low) Port pull-up resistor enable register Port control register data register control register prescaler IIC-bus clock control register IIC-bus clock/status register IIC-bus address register IIC-bus Tx/Rx data shift register 8-bit prescaler buzzer output control register converter data register (high) converter data register (low) data register extension data register data register extension data register control register Zero crossing detection control register
NOTE: mapped, `x'is Undefined
Mnemonic Address T1CON T1DATA P0CONH P0CONL P0PUR P1CON P1PND P2CONH P2CONL P2PUR P3CON SIODATA SIOCON SIOPS ICCR ICSR IDSR BUZPS ADCON ADDATAH ADDATAL PWM0 PWM0EX PWM1 PWM1EX PWMCON ZCMOD
RESET Value (bit)
KS86C4204/C4208/P4208
RESET POWER-DOWN
PROGRAMMING Sample KS86C4204/C4208/P4208 Initialization Routine
following sample program suggests program initial program settings ;-<< Interrupt Vector Address VECTOR INITIAL: SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data) 0000H 00H,INT_4208 0100H KS86C4208 only interrupt vector
;-<< Port Initialization P0CONH, P0CONL, P0PUR, #0FFH P1CON, #50H P1PND, #0F0H P2CONH, P2CONL, P2PUR, #0FFH P3CON, input input pull-up enable input, EXT.INT enable pull-up enable input input pull-up enable push-pull output
;-<< Timer Setting T0DATA, #41H T0CONL, #01000010B interrupt interval -1.667msec (10MHz base) Timer match output
;-<< Area Clear RAM_CLR: #0BFH ULE, RAM_CLR clear area setting
general register area 00H~BFH
RESET POWER-DOWN
KS86C4204/C4208/P4208
PROGRAMMING Sample KS86C4204/C4208/P4208 Initialization Routine (Continued)
;-<< Initialize Other Register
;-<< Main Loop MAIN:
#33H
CALL
SUB_ROUTINE0
subroutine call
CALL
SUB_ROUTINE
subroutine call
MAIN
;-<< Subroutine SUB_ROUTINE0:
SUB_ROUTINE1:
KS86C4204/C4208/P4208
RESET POWER-DOWN
PROGRAMMING Sample KS86C4204/C4208/P4208 Initialization Routine (Continued)
;-<< Interrupt Service Routine INT_4208: INT_TIMER0:
T0CONL #00000011B #00000011B INT_TIMER0
KS86C4208 just interrupt vector only Timer match interrupt enable T0CON's pending INT. enable check
T0CONL, #11111110B
pending clear
IRET
KS86C4204/C4208/P4208
PORTS
OVERVIEW
Port
PORTS
KS86C4204/C4208/P4208 four ports (0-3): 32-SOP type, with pins total 28-SOP type, with pins total. access these ports directly writing reading port data register addresses. Ports configured drive. (High current output: typical Table 9-1. KS86C4204/C4208/P4208 Port Configuration Overview Function Description Bit-programmable port Schmitt trigger input push-pull, opendrain put. Pull-up resistors assignable software. Bit-programable port Schmitt trigger input push-pull output. Pull-up resistors assignable software. Port1 pins also used alternative function. Bit-programmable port Schmitt trigger input push-pull, open drain output. Pull-up resistors assignable software. Port2 pins also used converter input. Push-pull open-drain output port. Pull-up resistors assignable software. Programmability
PORTS
KS86C4204/C4208/P4208
PORT DATA REGISTERS Table gives overview port data register names, locations, addressing characteristics. Data registers ports have structure shown Figure 9-1. Table 9-2. Port Data Register Summary Register Name Port data register Port data register Port data register Port data register Mnemonic
NOTE: reset operation clears P0-P3 data register "00H".
PORT DATA REGISTER 0-3) Pn.1 Pn.0
Pn.7
Pn.6
Pn.5
Pn.4
Pn.3
Pn.2
NOTES: Eight bits data register used port port Only lower four bits data register used port Only lower four bits data register used port (32-SOP type).
Figure 9-1. Port Data Register Format
KS86C4204/C4208/P4208
PORTS
PORT Port bit-programmable, general-purpose, ports. select normal input push-pull, open drain output mode. addition, configure pull-up resistor individual pins using control register settings. access port directly writing reading corresponding port data register, (E0H). reset clears port control register, P0CONH P0CONL, "00H" configuring port pins normal inputs. addition register used control Port P0PUR (E8H).
Pull-Up Register Typical) Pull-Up Enable Open-Drain P0CONH P0CONL
PWM, Data Output Disable (Input Mode)
IN/OUT
Input Data
Circuit Type
NOTE:
pins have protection diodes through VSS.
Mode Input Data Output Input
Figure 9-2. Port Circuit Diagram
PORTS
KS86C4204/C4208/P4208
PORT CONTROL REGISTERS (HIGH BYTE) E6H,
[.7-.6] Port P0.7/AD11/PWM0 Configuration Bits
Schmitt trigger input converter input (AD11); Schmitt trigger input Push-pull output Alternative function (PWM0 Output)
[.5-.4] Port P0.6/AD10 Configuration Bits
Schmitt trigger input converter input (AD10); Schmitt trigger input Push-pull output Open-drain output
[.3-.2] Port0, P0.5/AD9 Configuration Bits
Schmitt trigger input converter input (AD9); Schmitt trigger input Push-pull output Open-drain output
[.1-.0] Port0, P0.4/AD8 Configuration Bits
Schmitt trigger input converter input (AD8); Schmitt trigger input Push-pull output Open-drain output
Figure 9-3. Port High-Byte Control Register (P0CONH)
KS86C4204/C4208/P4208
PORTS
PORT CONTROL REGISTERS (LOW BYTE) E7H,
[.7-.6] Port P0.3/CLO Configuration Bits
Schmitt trigger input Alternative function; output Push-pull output Open-drain output
[.5-.4] Port P0.2/SI Configuration Bits
Schmitt trigger input; Input Schmitt trigger input; Input Push-pull output Open-drain output
[.3-.2] Port0, P0.1/SO Configuration Bits
Schmitt trigger input Alternative function; Output Push-pull output Open-drain output
[.1-.0] Port0, P0.0/SCK Configuration Bits
Schmitt trigger input; Input Alternative function; Output Push-pull output Open-drain output
Figure 9-4. Port Low-Byte Control Register (P0CONL)
PORTS
KS86C4204/C4208/P4208
PORT PULL-UP RESISTOR ENABLE REGISTERS E8H,
[.7] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.6] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.5] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.4] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.3] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.2] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.1] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.0] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
Figure 9-5. Port Pull-up Enable Control Registers (P0PUR)
KS86C4204/C4208/P4208
PORTS
PORT Port 4-bit port with individually configurable pins. used general port (Schmitt trigger input mode push-pull output mode). also port1 special input (ZCD) output (BUZ, PWM). addition, configure pull-up resistor individual using control register settings. normal operating mode, reset clears P1CON "00H", configuring P1.0-P1.3 normal Schmitt trigger inputs, also configure P1CON "0FFH" alternative functions. address port bits directly writing reading port data register, (E1H). port control register, P1CON located addresses E9H.
Pull-Up Register Typical) Pull-Up Enable P1CON
BUZ, Data Output Disable (Input Mode)
IN/OUT
Input Data External Interrupt Input
Circuit Type Noise Filter
NOTE:
pins have protection diodes through
Mode Input Data Output Input
Figure 9-6. Port Circuit Diagram
PORTS
KS86C4204/C4208/P4208
PORT CONTROL REGISTERS E9H,
[.7-.6] Port P1.3/PWM1/INT1 Configuration Bits
Schmitt trigger input; INT1 interrupt disabled Schmitt trigger input; Interrupt falling edge Push-pull output Alternative function (PWM1 Output)
[.5-.4] Port P1.2/INT0 Configuration Bits
Schmitt trigger input; INT0 interrupt disabled Schmitt trigger input; Interrupt falling edge Push-pull output Schmitt trigger input; Interrupt rising edge
[.3-.2] Port1, P1.1/BUZ Configuration Bits
Schmitt trigger input; Schmitt trigger input; Push-pull output Alternative function (BUZ Output)
[.1-.0] Port1, P1.0/T0/ZCD Configuration Bits
Schmitt trigger input Capture input) input; Enable Push-pull output Alternative function Output; match PWM)
Figure 9-7. Port Control Registers (P1CON)
KS86C4204/C4208/P4208
PORTS
PORT INTERRUPT PENDING REGISTERS EAH,
[.7] Port 1.3/INT1/PWM1, Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.6] Port 1.2/INT0, Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.5] Port 1.1/BUZ, Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.4] Port 1.0/T0/ZCD, Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.3] Port 1.3/INT1/PWM1, Open-drain Enable
Push pull output mode Open-drain output mode
[.2] Port 1.1/BUZ, Open-drain Enable
Push pull output mode Open-drain output mode
[.1] Port 1.3/INT1, Interrupt Pending
interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)/No effect (when write)
[.0] Port 1.2/INT0 Interrupt Pending
interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)/No effect (when write)
Figure 9-8. Port Interrupt Pending Registers (P1PND)
PORTS
KS86C4204/C4208/P4208
PORT Port 8-bit port with individually configurable pins. used general port (Schmitt trigger input mode push-pull output mode N-channel open-drain output mode). also port pins inputs. addition, configure pull-up resistor individual pins using control register settings. normal operating mode, reset clears P2CONH P2CONL "00H", configuring P2.0-P2.7 normal Schmitt trigger inputs. address port bits directly writing reading port data register, (E2H). port control register, P2CONH located addresses P2CONL ECH. additional register used control Port P2PUR (EDH). setting port open-drain pull-up resistor enable register, P2PUR, configure specific pins open-drain push-pull output.
Pull-Up Register Typical) Pull-Up Enable Open-Drain P2CONH P2CONL
SCL, Data Output Disable (Input Mode)
IN/OUT
Input Data SCLK SDAT
Circuit Type
NOTE:
pins have protection diodes through VSS.
Mode Input Data Output Input
Figure 9-9. Port Circuit Diagram
9-10
KS86C4204/C4208/P4208
PORTS
PORT CONTROL REGISTERS (HIGH BYTE) EBH,
[.7-.6] Port2, P2.7/AD7/SCLK Configuration Bits
Schmitt trigger input converter input (AD7); Schmitt trigger input Push-pull output Alternative function (IIC Clock pin):open-drain type
[.5-.4] Port P2.6/AD6/SDAT Configuration Bits
Schmitt trigger input converter input (AD6); Schmitt trigger input Push-pull output Alternative function (IIC Data pin):open-drain type
[.3-.2] Port2, P2.5/AD5 Configuration Bits
Schmitt trigger input converter input (AD5); Schmitt trigger input Push-pull output Open-drain output
[.1-.0] Port2, P2.4/AD4 Configuration Bits
Schmitt trigger input converter input (AD4); Schmitt trigger input Push-pull output Open-drain output
Figure 9-10. Port High-Byte Control Registers (P2CONH)
PORTS
KS86C4204/C4208/P4208
PORT CONTROL REGISTERS (LOW BYTE) ECH,
[.7-.6] Port2, P2.3/AD3 Configuration Bits
Schmitt trigger input converter input (AD3); Schmitt trigger input Push-pull output Open-drain output
[.5-.4] Port P2.2/AD2 Configuration Bits
Schmitt trigger input converter input (AD2); Schmitt trigger input Push-pull output Open-drain output
[.3-.2] Port2, P2.1/AD1 Configuration Bits
Schmitt trigger input converter input (AD1); Schmitt trigger input Push-pull output Open-drain output
[.1-.0] Port2, P2.0/AD0 Configuration Bits
Schmitt trigger input converter input (AD0); Schmitt trigger input Push-pull output Open-drain output
Figure 9-11. Port Low-Byte Control Register (P2CONL)
9-12
KS86C4204/C4208/P4208
PORTS
PORT PULL-UP RESISTOR ENABLE REGISTERS EDH,
[.7] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.6] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.5] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.4] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.3] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.2] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.1] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
[.0] Port Pull-up Resistor Enable
Disable pull-up Enable pull-up
Figure 9-12. Port Pull-up Resistor Enable Register (P2PUR)
9-13
PORTS
KS86C4204/C4208/P4208
PORT Port 4-bit port with individually configurable pins. used only output port. addition, configure pull-up register individual pins using control register settings. normal operating mode, reset clears P3CON "00H", configures P3.0-P3.3 push-pull output mode. Using P3CON register (EEH), alternatively configure port pins push-pull output, open-drain output.
Pull-Up Register Typical) Pull-Up Enable Open-Drain
Data Output Only
IN/OUT
NOTE:
pins have protection diodes through
VSS.
Figure 9-13. Port Circuit Diagram
9-14
KS86C4204/C4208/P4208
PORTS
PORT CONTROL REGISTERS EEH,
[.7-.6] Port P3.3 Configuration Bits
Push-pull output Push-pull output Open-drain output: pull-up resistor disable Open-drain output: pull-up resistor enable
[.5-.4] Port P3.2 Configuration Bits
Push-pull output Push-pull output Open-drain output: pull-up resistor disable Open-drain output: pull-up resistor enable
[.3-.2] Port3, P3.1 Configuration Bits
Push-pull output Push-pull output Open-drain output: pull-up resistor disable Open-drain output: pull-up resistor enable
[.1-.0] Port3, P3.0 Configuration Bits
Push-pull output Push-pull output Open-drain output: pull-up resistor disable Open-drain output: pull-up resistor enable
Figure 9-14. Port Control Registers (P3CON)
9-15
PORTS
KS86C4204/C4208/P4208
PROGRAMMING Configuring Port Pins Specification
following sample program shows configure KS86C4204/C4208/P4208 ports specification Program comments show effect settings:
P0CONH, #01101010B P0CONL, #10010101B P1CON, #10101010B P2CONH, #11111010B P2CONL, #10101010B P3CON, #00000000B
input 0.6-0.4 push-pull output push-pull output 0.2-0.0 setting 1.3-1.0 push-pull output 2.7, setting 2.5, push-pull output 2.0-2.3 push-pull output 3.3-3.0 push-pull output
9-16
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
Basic Timer (BT)
BASIC TIMER TIMERS
MODULE OVERVIEW
KS86C4204/C4208/P4208 three default timers: 8-bit basic timer, 8-bit general-purpose timer/counter, called timer 8-bit timer/counter zero-crossing detection circuit called timer
basic timer (BT) different ways: watchdog timer provide automatic reset mechanism event system malfunction. signal required oscillation stabilization interval after reset Stop mode release. functional components basic timer block are: Clock frequency divider (fOSC divided 4096, 1024, 128) with multiplexer 8-bit basic timer counter, BTCNT (DDH, read-only) Basic timer control register, BTCON (DCH, read/write) Timer Timer three operating modes, which select appropriate T0CONL setting: Interval timer mode Capture input mode 8-bit output mode Timer following functional components: Clock frequency divider (fosc divided 4096, 256, with multiplexer 8-bit counter (T0CNT), 8-bit comparator, 8-bit data register (T0DATA) (P1.0, match) timer match/PWM output capture input Timer overflow interrupt (T0OVF) match interrupt (T0INT) generation Timer control registers, T0CONH T0CONL (D2H respectively) Timer Timer operating mode, interval timer mode. clear timer counter appropriate setting T1CON register. T1CON.3 "1", T1CNT cleared edge detection. Timer following components: Clock frequency divider (fOSC divided 4096, 1024, 512, 256, 128, 8-bit counter (T1CNT), 8-bit comparator, 8-bit data register (T1DATA) Timer control register, T1CON
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
BASIC TIMER (BT)
BASIC TIMER CONTROL REGISTER (BTCON) basic timer control register, BTCON, used select input clock frequency, clear basic timer counter frequency dividers, enable disable watchdog timer function. reset clears BTCON "00H". This enables watchdog function selects basic timer clock frequency fosc/4096. disable watchdog function, must write signature code "1010B" basic timer register control bits BTCON.7-BTCON.4. 8-bit basic timer counter, BTCNT, cleared during normal operation writing BTCON.1. clear frequency dividers both basic timer input clock timer clock, write BTCON.0.
BASIC TIMER CONTROL REGISTER (BTCON) DCH,
Watchdog timer enable bits: 1010B Disable watchdog function Other value Enable watchdog function
Divider clear basic timer timer effect Clear both dividers Basic timer counter clear bits: effect Clear basic timer counter
Basic timer input clock selection bits: fosc/4096 fosc/1024 fosc/128 Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function program basic timer overflow signal (BTOVF) generate reset setting BTCON.7-BTCON.4 value other than "1010B" (The "1010B" value disables watchdog function). reset clears BTCON "00H", automatically enabling watchdog timer function. reset also selects clock determined current CLKCON register setting) divided 4096 clock. reset whenever basic timer counter overflows occurs. During normal operation, application program must prevent overflow, accompanying reset operation, from occurring. this, BTCNT value must cleared writing BTCON.1) regular intervals. system malfunction occurs circuit noise some other error condition, counter clear operation will executed basic timer overflow will occur, initiating reset. other words, during normal operation, basic timer overflow loop overflow 8-bit basic timer counter, BTCNT) always broken BTCNT clear instruction. malfunction does occur, reset triggered automatically. Oscillation Stabilization Interval Timer Function also basic timer program specific oscillation stabilization interval following reset when Stop mode been released external interrupt. Stop mode, whenever reset external interrupt occurs, oscillator starts. BTCNT value then starts increasing rate fOSC/4096 (for reset), rate preset clock source (for external interrupt). When BTCNT.4 set, signal generated indicate that stabilization interval elapsed gate clock signal that resume normal operation. summary, following events occur when Stop mode released: During Stop mode, power-on reset external interrupt occurs trigger Stop mode release oscillation starts. power-on reset occurred, basic timer counter will increase rate fOSC/4096. external interrupt used release Stop mode, BTCNT value increases rate preset clock source. Clock oscillation stabilization interval begins continues until basic timer counter set. When BTCNT.4 set, normal operation resumes. Figure 10-2 10-3 shows oscillation stabilization time STOP mode release.
10-3
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
Oscillation Stabilization
Normal Operating mode
Reset ReleaseVoltage RESET trst Internal Reset Release
Oscillator (XOUT) Oscillator Stabilization Time
BTCNT clock BTCNT value 10000B 00000B tWAIT 4096x16x1/fOSC
Basic timer increment operations IDLE mode
NOTE:
During oscillator stabilization wait time, Power-on-reset 4096x16/fosc.
WAIT,
when released
Figure 10-2. Oscillation Stabilization Time RESET
10-4
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
Normal Operating Mode STOP Instruction Execution External Interrupt
RESET
STOP Mode
Oscillation Stabilization Time
Normal Operating Mode
STOP Mode Release Signal
STOP Release Signal
Oscillator (XOUT)
BTCNT clock
10000B BTCNT Value 00000B tWAIT Basic Timer Increment NOTE: Duration oscillator stabilzation wait time, tWAIT, released interrupt determined setting basic timer control register, BTCON.
BTCON.3
BTCON.2
tWAIT
4096 16/fosc 1024 16/fosc 16/fosc Invalid setting
tWAIT (When MHz)
6.55 1.64
Figure 10-3. Oscillation Stabilization Time STOP Mode Release
10-5
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
PROGRAMMING Configuring Basic Timer
This example shows configure basic timer sample specification ;-<<Initialize system peripherals>> RESET 0100H BTCON,#10100010B SP,#0C0H
MHz) select (non-divided)
Reset start address disable interrupt disable watchdog function clock source: fosc/4096 (104 overflow CLKCON,#00011000B clock source KS86C4204/C4208/P4208 Stack pointer initial
;-<< Main loop MAIN
enable interrupt
overflow
BTCON,#02H
enable watchdog function clear basic timer counter (BTCON) before occurs
T,MAIN
10-6
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
TIMER
TIMER CONTROL REGISTERS (T0CONH T0CONL) timer control register byte, T0CONL, used select timer operating mode (interval timer, capture mode, mode) input clock frequency, clear timer counter, enable overflow interrupt match/capture interrupt. also contains pending match/capture interrupts. Timer control register high byte, T0CONH, contains pending overflow interrupt. Only T0CONH register used, T0CONH.0. reset clears T0CONL "00H". This sets timer normal interval timer mode, selects input clock frequency fOSC /4096, disables overflow interrupt match/capture interrupts. counter cleared time during normal operation writing T0CONL.3. overflow interrupt, T0OVF, IRQ0 with vector 00H. When overflow interrupt occurs serviced CPU, pending condition cleared manually writing T0CONH.0. enable match/capture interrupt (T0INT, IRQ0, vector 00H), must T0CONL.1 "1". interrupt service routine must clear pending condition writing interrupt pending bit, T0CONL.0.
TIMER CONTROL REGISTERS (HIGH BYTE) D2H, .0(8)
used
Timer overflow interrupt pending bit(overflow interrupt): interrupt pending (when read) Clear pending (when write) Interrupt pending (when read)
Figure 10-4. Timer High-Byte Control Registers (T0CONH)
10-7
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
TIMER CONTROL REGISTERS (LOW BYTE) D3H,
Timer interrupt clock selection bits: fosc/4096 fosc/256 fosc/8 fosc/1 Timer operating mode selection bits: Interval mode Capture mode (capture rising edge, counter running, occur) Capture mode (capture falling edge, counter running, occur) mode (OVF interrupt occur)
Timer interrupt pending bit: interrupt pending (when read) Clear pending (when write) interrupt pending (when read) Timer interrupt enable bit: Disable interrupt Enable interrupt Timer overflow interrupt enable bit: Disable overflow interrupt Enable overflow interrupt
Timer counter clear bit: effect Clear Timer counter (when write)
Figure 10-5. Timer Low-Byte Control Registers (T0CONL)
10-8
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
TIMER FUNCTION DESCRIPTION Timer Interrupts (IRQ0, Vectors 00H) Timer module generate interrupts; timer overflow interrupt (T0OVF), timer match/capture interrupt (T0INT). T0OVF interrupt level IRQ0, vector 00H; T0INT also level IRQ0, vector 00H. T0OVF interrupt pending condition cleared setting T0CONH.0 pending "0". T0INT pending condition must cleared software writing T0CONL.0 pending bit. INTERVAL TIMER MODE interval timer mode, match signal generated when counter value identical value written Timer reference data register, T0DATA. match signal generates Timer match interrupt (T0INT, vector 00H) then clears counter. example, write value "10H" T0DATA, counter will increment until reaches "10H". this point, Timer interrupt request generated, counter value reset counting resumes. With each match, level signal Timer output inverted.
Interrupt Enable/Disable
(Clear)
IRQ0 (T0OVF)
Counter
Interrupt Enable/Disable
IRQ0 (T0INT)
Comparator
Match
Toggle
P1.0/T0 P1CON.1,
Data Register
Figure 10-6. Simplified Timer Function Diagram (Interval Timer Mode)
10-9
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
Compare Value (T0DATA) Counter Value (T0CNT) Count Start T0CON Counter Clear (T0CONL.3)
Match
Match
Match Match Match Match Match
Clear
Clear T0DATA Value Change
Clear
Interrupt Request (T0CONL.0)
Figure 10-7. Timer Timing Diagram
10-10
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
PULSE WIDTH MODULATION MODE Pulse width modulation (PWM) mode lets program width (duration) pulse that output pin. interval timer mode, match signal generated when counter value identical value written data register (T0DATA). mode, however, match signal does clear counter runs continuously, overflowing "FFH", continues incrementing from "00H"). Although possible match signal generate T0INT interrupt, interrupt typically used PWM-type applications. Instead, pulse held High level long data register (T0DATA) value greater than counter (T0CNT) value 8-bit operation.
Timer Counter Clock (4MHz) T0DATA
T0DATA
250ns
32µs T0DATA
T0DATA
250ns Cycle 64µs
NOTES: system clock frequency 4MHz assumed. input clock timer count(T0CNT) assumed non-divided (fosc/1).
Figure 10-8. Simplified Timer Function Diagram (PWM Mode)
10-1
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
Interrupt Enable/Disable
(Clear)
IRQ0 (T0OVF)
Counter
Interrupt Enable/Disable
IRQ0 (T0INT)
Comparator
Match
T0CON P1CON.1,
P1.0/T0 High level when data counter; level when data counter
Data Register
Figure 10-9. Block Function Diagram
10-12
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
CAPTURE MODE capture mode, signal edge that detected opens gate loads current counter value into data register. Rising edges falling edges selected trigger this operation. Both kinds interrupts used capture mode: T0OVF generated when counter overflow occurs, T0INT generated when counter value loaded into data register. reading captured data value T0DATA, assuming specific value tCLK, determine pulse width (duration) signal being input pin. (See Figure 10-10.)
Interrupt Enable/Disable
Counter
IRQ0 (T0OVF) IRQ0 (T0INT) Interrupt Enable/Disable
P1.0/TO (CAP)
T0CONL
Data Register
Figure 10-10. Simplified Timer Function Diagram (Capture Mode)
10-13
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
Bits Clear
RESET
STOP Data Basic Timer Control Register (Write '1010xxxxB' disable.)
1/4096 1/1024 1/128
8-Bit Counter (BTCNT, Read-Only)
RESET
When BTCNT.4 after releasing from RESET STOP mode, clock starts. Bits Data 1/4096 1/256 Match 8-Bit Compatator T0CNT (D0H) (Read-Only) Clear IRQ0 (PWM interval) Bits T0DATA (D1H) (Read/Write) Basic Timer Control Register Data Timer Control Register IRQ0
(CAP)
Bits
NOTE: During power-on reset operation, idle during required oscillation stabilization interval (until basic timer counter set).
Figure 10-11. Basic Timer Timer Block Diagram
10-14
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
PROGRAMMING Configuring Timer (Interval Mode)
following sample program sets Timer interval timer mode. VECTOR INITIAL:
0000H 00H, INT_4208 0100H SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data) KS86C4208 only interrupt vector
T0DATA, #41H T0CONL, #01000010B
interrupt interval 1.69msec (10MHz base) Timer match interrupt enable
MAIN:
CALL
SUB_ROUTINE
SUB_ROUTINE:
MAIN
10-15
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
PROGRAMMING Configuring Timer (Interval Mode) (Continued)
INT_4208: INT_Timer
T0CONL #00000011B #00000011B INT_Timer
KS86C4208 just interrupt vector
only Timer match interrupt enable
T0CON'spending INT. enable check
T0CONL, #11110110B
pending clear
IRET
10-16
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
PROGRAMMING Configuring Timer (PWM Mode)
following sample program sets Timer 8-bit mode. INITIAL:
0100H
SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H
Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data)
P1CON, #00000011B T0DATA, #80H T0CONL, #01111000B
P1.0 (PWM) output half duty Timer mode
MAIN:
MAIN
10-17
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
TIMER TIMER CONTROL REGISTER (T1CON) timer control register,T1CON, located operates interval timer mode. setting appropriate bits T1CON select input clock frequency enable Timer interrupt. T1CON also contains pending Timer interrupt. reset clears T1CON "00H". This sets timer normal interval mode selects input clock frequency fosc/4096 disables Timer interrupt. clear timer counter either setting T1CON.2 enable clear signal clear timer counter setting T1CON.3 "1". enable Timer match interrupt (IRQ0, vector 00H) must T1CON.1 "1". interrupt service routine must clear pending condition writing Timer interrupt pending bit, T1CON.0.
TIMER CONTROL REGISTERS E4H,
Timer 1counter control bit: Disable operation Enable counter operation
Timer interrupt pending bit: interrupt pending (when read) Clear pending (when write) Interrupt pending (when read) Timer interrupt enable bit: Disable interrupt Enable interrupt Timer counter clear enable bit: effect Clear timer counter when write)
Timer input clock selection bits: fosc/4096 fosc/1024 fosc/512 fosc/256 fosc/128 fosc/32
Timer counter automatic clear enable bit: Disable Enable clear signal clear timer counter
Figure 10-12. Timer Control Register (T1CON)
10-18
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
Bits 1/4096 1/1024 1/512 1/256 1/128 1/32 1/256 1/64 IRQ0 8-BIT COUNTER Clear From Data
8-BIT COMPARATOR Match
DATA REGISTER
Data P1.1 P1CON.3, P1.1/BUZZE
6-Bit Prescaler
TOGGLE
NOTE:
When P1.1/BUZZER used BUZZER output pin, initial value (Low Level). (When bit7 BUZPS "0", output P1.1 Low.)
Figure 10-13. Timer Block Diagram
10-19
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
BUZZER OUTPUT CONTROL REGISTER (BUZPS) Buzzer output control register used select frequency from KHz. these various frequency used generate melody signal. selecting clock source (bit BUZPS) value prescaler, desire frequency obtained. BUZPS.7 used control buzzer output when P1.1 buzzer output mode (configure P1CON).
BUZPS CONTROL REGISTERS F6H,
BUZZER clock selection bit: Divided (fosc/256) Divided (fosc/64) BUZZER output enable bit: Disable buzzer output (Buzzer off) Enable buzzer output (Buzzer Prescaler value: 000000 000001 000010 111111 Divided [fosc/(256 64)] Divided [fosc/(256 64)] Divided [fosc/(256 64)] Divided 2x(n+1) [fosc/(256 64)] Divided [fosc/(256 64)]
Figure 10-14. Buzzer Output Control Register (BUZPS)
10-20
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
PROGRAMMING Configuring Timer following sample program sets Timer interval timer mode. VECTOR INITIAL:
0000H 00H, INT_4208 0100H KS86C4208 only interrupt vector
SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H
Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data)
T1DATA, #41H T1CON, #10010110B
interrupt interval 6.76msec (10MHz base) Timer1 match interrupt enable
MAIN:
CALL
SUB_ROUTINE
SUB_ROUTINE:
MAIN
10-2
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
+PROGRAMMING Configuring Timer (Continued)
INT_4208:
KS86C4208 just interrupt vector T1CON #00000011B #00000011B INT_T
Timer interrupt routine
INT_T1:
T1CON, #11111010B
pending clear
IRET
10-22
KS86C4204/C4208/P4208
BASIC TIMER TIMERS
+PROGRAMMING Configuring Buzzer
following sample program sets Buzzer output. VECTOR INITIAL:
0000H 00H, INT_4208 0100H KS86C4208 only interrupt vector
SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H
Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data)
P1CON, #00001100B BUZPS, #10000000B
P1.1 Buzzer output fosc/512 Buzzer wave output
MAIN:
CALL
SUB_ROUTINE
SUB_ROUTINE:
MAIN
10-23
BASIC TIMER TIMERS
KS86C4204/C4208/P4208
NOTES
10-24
KS86C4204/C4208/P4208
CONVERTER
1OVERVIEW
CONVERTER
converter (ADC) module uses successive approximation logic convert analog levels twelve input channels equivalent 10-bit digital values. analog input level must between AVREF AVSS values. converter following components: Twelve multiplexed analog input pins (AD0-AD11) Analog comparator with successive approximation logic 10-bit conversion data output registers (ADDATAH, ADDATAL) control register (ADCON) analog-to-digital conversion procedure initiated when writes value ADCON register address select twelve available input pins. select desired input channel setting appropriate bits ADCON register. KS86C4204/C4208/P4208 microcontroller performs 10-bit conversions only input channel time. dynamically select different analog input channels during program execution manipulating selection bits ADCON register. During normal conversion, logic initially sets successive approximation register 200H (the approximate half-way point 10-bit register). This register then updated automatically during each conversion step. successive approximation block performs 10-bit conversions input channel time. dynamically select different channels mainpulating channel selection value (ADCON.7-4) ADCON register. start conversion, should enable bit, ADCON.0. When conversion completed, ADCON.3, end-of-conversion (EOC) automatically result dumped into ADDATA register where read. converter then enters idle state. Remember read contents ADDATA before another conversion starts. Otherwise, previous result will overwritten next conversion result. NOTE Because does sample-and-hold circuitry, important that fluctuations analog level AD0-AD11 input pins during conversion procedure kept absolute minimum. change input level, perhaps circuit noise, will invalidate result.
CONVERTER
KS86C4204/C4208/P4208
INTERNAL REFERENCE VOLTAGE LEVELS function block, analog input voltage level compared reference voltage. analog input level must remain within range AVSS AVREF (usually, AVREF VDD). Different reference voltage levels generated internally along resistor tree during analog conversion process each conversion step. reference voltage level first conversion always AVREF. USING PINS STANDARD DIGITAL INPUT module's input pins alternatively used digital input port port AD0-AD7 share names P2.0-P2.7 AD8-AD11 share names P0.4-P0.7, respectively CONVERTER CONTROL REGISTER (ADCON) converter control register, ADCON, located address F7H. ADCON four functions: Bits select analog input (AD0-AD11). indicates status conversion. Bit2-1 select clock source. starts conversion. Only analog input channel selected time. dynamically select eight analog input pins (AD0-AD11) manipulating 4-bit value ADCON.7-ADCON.4
CONVERTER CONTROL REGISTERS F7H,
converter input selection bits: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110
Conversion start bit: meaning (P2.0) conversion start (P2.1) (P2.2) Clock source selection bit: (P2.3) fosc/16 (P2.4) fosc/8 (P2.5) fosc/4 (P2.6) fosc/1 (P2.7) (P0.4) (P0.5) End-of-Conversion status bit: AD10 (P0.6) conversion progress AD11 (P0.7) conversion complete Internally connected Internally connected Internally connected Internally connected
Figure 11-1. Converter Control Register (ADCON)
11-2
KS86C4204/C4208/P4208
CONVERTER
Converter Control Register ADCON (F7H) ADCON .7-4 ADCON Control Circuit AD0/P2.0 AD1/P2.1 Multiplexer Successive Approximation Circuit ADCON .2-1 Clock Selector ADCON (EOC Flag)
AD7/P2.7 AD8/P0.4
Analog Comparator
AD11/P0.7 Conversion Result Converter AVREF AVSS ADDATAH (F8H) ADDATAL (F9H)
Data
ADDATAH
ADDATAL
Figure 11-2. Converter Circuit Diagram
11-3
CONVERTER
KS86C4204/C4208/P4208
ADCON.0 Conversion Start Clock
ADDATA Previous Value
Valid Data
ADDATAH (8-Bit) ADDATA (2-Bit) time clock Clock
Figure 11-3. Converter Timing Diagram CONVERSION TIMING conversion process requires steps clock edges) convert each clocks step-up conversion. Therefore, total clocks required complete 10-bit conversion: With 10MHz clock frequency, clock cycle (4/fosc). each conversion requires clocks, conversion rate calculated follows: clocks/bit 10-bits set-up time clock) clocks clock 10MHz, clock time 4/fosc (assuming ADCON.2-.1
INTERNAL CONVERSION PROCEDURE Analog input must remain between voltage range AVSS AVREF. Configure analog input pins input mode making appropriate settings P2CONH, P2CONL P0CONH registers. Before conversion operation starts, must first select twelve input pins (AD0-AD11) writing appropriate value ADCON register. When conversion been completed, clocks have elapsed), flag "1", that check made verify that conversion successful. converted digital value loaded output register, ADDATAH (High 8-bit) ADDATAL (Low 2-bit), then module enters idle state. digital conversion result read from ADDATAH ADDATA registers.
11-4
KS86C4204/C4208/P4208
CONVERTER
Reference Voltage Input
AVREF
Analog Input
AD0-AD11
XOUT
KS86C4204/ C4208/P4208
AVSS
NOTES: symbol signifies offset resistor with value from Ohms. recommended that oscillator SS/VSS must connected separately with power.
Figure 11-4. Recommended Converter Circuit Highest Absolute Accuracy
11-5
CONVERTER
KS86C4204/C4208/P4208
PROGRAMMING PROGRAMMING Configuring 10-bit Converter
VECTOR INITIAL:
0000H 00H, INT_4208 0100H KS86C4208 only interrupt vector
SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H
Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00-BF (After decrease, push data)
MAIN:
CALL
Sub_ADC
Sub_ADC: CONV_LOOP:
MAIN
P0CONH, #55H P0PUR, #00H ADCON, #10000001B
P0.7~0.4: input enable pull-up disable Select P0.4, Conversion start
ADCON, #00001000B CONV_LOOP ADDATAH ADDATAL
Check Conversion completed High 8-bit result 2-bit result
11-6
KS86C4204/C4208/P4208
ZERO-CROSSING DETECTION CIRCUIT
OVERVIEW
ZERO-CROSSING DETECTION CIRCUIT
Zero-crossing detection circuit Samsung's KS86C4204/C4208/P4208, generates digital signal synchronism with signal input. provides timing signal operations which synchronized with line. zero crossing detection circuit digitizes signal receives from power supply. setting bits port control register (P1CON), enable zero-crossing detection. Zero-crossing detector shown Figure 12-1.
ZCMOD .3-2
Input
P1.0
P1CON.1-0 Edge Detection
IRQ0 (ZCINT)
0.1µF Timer Counter Clear Enable
ZCMOD.4
Normal Input
NOTE:
abbreviation noise filter.
Figure 12-1. Zero-Crossing Detector Diagram
ZERO-CROSSING DETECTION CIRCUIT
KS86C4204/C4208/P4208
ZERO-CROSSING DETECTOR CONTROL REGISTER zero crossing detector control register, ZCMOD, used select interrupt mode (interrupt falling edge, rising edge both). Reset clears ZCMOD `00H', configures interrupt selection mode falling edge disables interrupt. interrupt pending must cleared writing ZCMOD.0
ZERO CROSSING DETECOR CONTROL REGISTERS FFH,
used operation enable bit: Disable operation Enable operation
interrupt pending bit: interrupt pending (when read) Clear pending (when write) Interrupt pending (when read) interrupt enable bit: Disable interrupt Enable interrupt
Interrupt mode selection bits: Interrupt falling edge Interrupt rising edge Interrupt both edge used
Figure 12-2. Zero-Crossing Detector Control Register (ZCMOD)
12-2
KS86C4204/C4208/P4208
ZERO-CROSSING DETECTION CIRCUIT
ZERO CROSS DETECTOR circuit detects zero-cross point waveform. Three types detection selected, point from positive negative, point from negative positive, both. zero cross detection circuit noise filter circuit detected zero cross point used clear timer counter (T1CON.3
1/fzc
input
VAZC
VAZ(P-P)
ZCINT
Figure 12-3. Zero-Crossing Waveform Diagram
12-3
ZERO-CROSSING DETECTION CIRCUIT
KS86C4204/C4208/P4208
PROGRAMMING Configuring VECTOR 0000H 00H, INT_4208 0100H KS86C4208 only interrupt vector
INITIAL:
SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H
Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00-BF (After decrease, push data)
P1CON, #00000001B ZCMOD, #00010010B
P1.0 input enable Input sine wave P1.0 operation/interrupt enable
MAIN:
CALL
SUB_ROUTINE
SUB_ROUTINE:
MAIN
12-4
KS86C4204/C4208/P4208
ZERO-CROSSING DETECTION CIRCUIT
PROGRAMMING TIP1 Configuring (Continued)
INT_4208:
ZCMOD #00000011B #00000011B INT_ZCD
interrupt routine
INT_ZCD:
ZCMOD, #11111110B
pending clear
IRET
12-5
ZERO-CROSSING DETECTION CIRCUIT
KS86C4204/C4208/P4208
NOTES
12-6
KS86C4204/C4208/P4208
12-BIT
OVERVIEW
12-BIT (PULSE WIDTH MODULATION)
This microcontroller 12-bit circuit. operation circuit controlled single control register, PWMCON. counter 12-bit incrementing counter. used 12-bit circuits. start counter enable circuits, PWMCON.2 "1". counter stopped, retains current count value; when re-started, resumes counting from retained count value. When there need clear counter PWMCON.3 "1". select clock counter PWMCON.6-.7. Clocks which select Fosc/256, Fosc/64, Fosc/8, Fosc/1.
FUNCTION DESCRIPTION
12-bit circuits have following components: 6-bit comparator extension cycle circuit 6-bit reference data registers (PWM0, PWM1) 6-bit extension data registers (PWM0EX, PWM1EX) output pins (P0.7/PWM0, P1.3/PWM1) counter counter 12-bit incrementing counter comprised lower 6-bit counter upper 6-bit counter. determine module's base operating frequency, lower byte counter compared data register value. order achieve higher resolutions, bits upper counter used modulate "stretch" cycle. control "stretching" output duty cycle specific intervals, 6-bit extended counter value compared with 6-bit value (bits 7-2) that write module's extension register.
12-BIT
KS86C4204/C4208/P4208
data extension registers (duty) data registers, located FCH, determine output value generated each 12-bit circuit. These registers, read/write addressable. 8-bit data register PWM0 PWM1, which only bits used. 8-bit extension registers PWM0EX (FBH) PWM1EX (FDH), which only bits used program required output, load appropriate initialization values into 6-bit data registers (PWM0, PWM1) 6-bit extension registers (PWM0EX, PWM1EX). start counter, resume counting, PWMCON.2 "1". reset operation disables output. current counter value retained when counter stops. When counter starts, counting resumes retained value. clock rate timing characteristics both 12-bit output channels identical, based Fosc clock frequency. counter clock value determined setting PWMCON.6-.7. Table 13-1. Control Data Registers Register Name data registers control registers Mnemonic PWM0, PWM1 PWM0EX, PWM1EX PWMCON Address FAH, FBH, Function 6-bit basic cycle frame value 6-bit extension ("stretch") value counter stop/start (resume), Fosc clock settings
function Description output signal toggles level whenever lower 6-bit counter matches reference value stored module's data register (PWM0, PWM1). value PWM0 PWM1 register zero, overflow lower counter causes output toggle High level. this way, reference value written data register determines module's base duty cycle. value 6-bit extension counter compared with extension settings 6-bit extension data registers (PWM0EX, PWM1EX). This 6-bit extension counter value, together with extension logic module's extension register then used "stretch" duty cycle output. "stretch" value extra clock period specific intervals, cycles (see Table 13-2). example, value extension register '04H', 32nd cycle will pulse longer than other cycles. base duty cycle duty 32nd cycle will therefore "stretched" approximately duty. example, write extension register, odd-numbered pulses will cycle longer. write extension register, pulses will stretched cycle except 64th pulse. output goes output buffer then corresponding output pin. this way, obtain high output resolution high frequencies.
13-2
KS86C4204/C4208/P4208
12-BIT
Table 13-2. output "stretch" Values Extension Registers PWM0EX PWM0EX "Stretched" Cycle Number used used
Clock: 4MHz PWM0 PWM1 Register Values: 250ns
250ns
250ns
Figure 13-1. 12-Bit Basic Waveform
13-3
12-BIT
KS86C4204/C4208/P4208
Clock: 4MHz
PWM0 PWM1 Register Values:
500ns
PWM0EX PWM1EX Register Values: (Extended Value 04H)
32th
64th
32th
64th
4MHz
750ns
Figure 13-2. 12-Bit Extended Waveform
13-4
KS86C4204/C4208/P4208
12-BIT
CONTROL REGISTER (PWMCON) control register module, PWMCON, located register address FEH. PWMCON used 12-bit modules. settings PWMCON register control following functions: counter clock selection data reload interval selection counter clear counter stop/start resume) operation counter overflow (upper 6-bit counter overflow) interrupt control reset clears PWMCON bits logic zero, disabling entire module.
CONTROL REGISTERS(PWMCON) FEH, Reset:
input clock selection bits: fosc/256 fosc/64 fosc/8 fosc/1 PWM1 data reload interval selection bit: Reload from 12-bit counter overflow Reload from 6-bit counter overflow PWM0 data reload interval selection bit: Reload from 12-bit counter overflow Reload from 6-bit counter overflow
12-bit Interrupt pending bit: interrupt pending Clear pending condition (when write) Interrupt pending counter interrupt enable bit: Disable interrupt Enable interrupt counter enable bit: Stop counter Start (resume countering)
counter clear bit: effect Clear 12-bit counter
Figure 13-3. PWM/Capture Module Control Register (PWMCON)
13-5
12-BIT
KS86C4204/C4208/P4208
6-Bit Basic Register PWM0, PWM1 Reload (overflow lower 6-bit counter) 6-Bit Buffer
fosc/256 fosc/64 fosc/8 fosc/1 PWMCON.6-7 Lower 6-Bit Counter Upper 6-Bit Counter Pending PWMCON.0 PWMCON.1 PWMCON.2 Extension Control Logic OVFINT 6-Bit Comparator When PWM0 PWM1 Counter When PWM0 PWM1 Counter PWMDATA Counter P1.3/PWM1 P0.7/PWM0
(1,3,.,61,63)
6-Bit Extension Registers (PWM0EX, PWM1EX)
Figure 13-4. PWM/Capture Module Functional Block Diagram
13-6
KS86C4204/C4208/P4208
12-BIT
PROGRAMMING Programming Module Sample Specifications VECTOR 0000H 00H, INT_4208 0100H SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00-BF (After decrease, push data) KS86C4208 only interrupt vector
INITIAL:
P0CONH, #0C0H PWM0EX, PWM0, #20H PWMCON, #00000100B
P0.7 PWM0 output Extension register setting Data register setting Start counting Half dutyPWM wave P0.7
MAIN:
CALL
SUB_ROUTINE
SUB_ROUTINE:
MAIN
13-7
12-BIT
KS86C4204/C4208/P4208
NOTES
13-8
KS86C4204/C4208/P4208
SERIAL INTERFACE
OVERVIEW
SERIAL INTERFACE
Serial module, interface with various types external devices that require serial data transfer. components each function block are: 8-bit control register (SIOCON) Clock selection logic 8-bit data buffer (SIODATA) 8-bit prescaler (SIOPS) 3-bit serial clock counter Serial data pins (SI, External clock input (SCK) module transmit receive 8-bit serial data frequency determined corresponding control register settings. ensure flexible data transmission rates, select internal external clock source. PROGRAMMING PROCEDURE program module, follow these basic steps: Configure pins port (SO, SCK, loading appropriate value P1CONL Register. Load 8-bit value SIOCON control register properly configure serial module. this operation, SIOCON.2 must enable data shifter. interrupt generation, serial interrupt enable (SIOCON.1) "1". When transmit data serial buffer, write data SIODATA SIOCON.3 shift operation starts. When shift operation (transmit/receive) completed, pending (SIOCON.0) interrupt request generated.
SERIAL INTERFACE
KS86C4204/C4208/P4208
SERIAL CONTROL REGISTERS (SIOCON) control registers serial interface, SIOCON, located F0H. control settings module. Clock source selection (internal external) shift clock Interrupt enable Edge selection shift operation Clear 3-bit counter start shift operation Shift operation (transmit) enable Mode selection (transmit/receive receive-only) Data direction selection (MSB first first) reset clears SIOCON value "00H". This configures corresponding module with internal clock source SCK, selects receive-only operating mode, clears 3-bit counter. data shift operation interrupt disabled. selected data direction MSB-first.
CONTROL REGISTERS(SIOCON) F0H,R/W, Reset:
shift clock select bit: Internal clock (P.S clock) External clock (SCK) Data direction control bit: MSB-first mode LSB-first mode mode selction bit: Rececive-only mode Transmit/receive mode Shift clock edge selction bit: falling edges, rising edges rising edges, falling edges
Interrupt pending bit: interrupt pending Clear pending condition (when write) Interrupt pending SIOinterrupt enable bit: Disable interrupt Enable interrupt shift operation enable bit: Disable shifter clock counter Enable shfter clock counter
counter clear shift start bit: action Clear 3-bit counter start shifting
Figure 14-1. Serial Interface Control Register (SIOCON)
14-2
KS86C4204/C4208/P4208
SERIAL INTERFACE
PRESCALER REGISTER (SIOPS) control register serial interface module, SIOPS located F1H. value stored prescaler registers, SIOPS, lets determine clock rate (baud rate) follows: Baud rate Input clock(Xin/2) 2(pre-scaler value external input clock
PRE-SCALER REGISTERS(SIOPS) F1H,R/W
Baud rate IN/4)/(SIOPS
Figure 14-2. Pre-scaler Register (SIOPS)
3-Bit Counter Clear SIOCON.3
SIOCON.0 Pending
SIOCON.7 (Shift Clock Source Select)
SIOCON.1 (Interrupt Enable)
SIOCON.4 (Edge Select) SIOPS(F1H)
SIOCON.2 (Shift Enable)
SIOCON.5 (Mode Select) SIOCON.6 (LSB/MSB First Mode Select)
XIN/2
8-Bit Prescaler Prescaler Value 1/(SIOPS
Toggle
8-Bit Shift Buffer (SIODATA)
Data
Figure 14-3. Functional Block Diagram
14-3
SERIAL INTERFACE
KS86C4204/C4208/P4208
IRQS SIOCON.3
Transmit Complete
Figure 13-4. Serial Timing Transmit-Receive Mode falling, SIOCON.4
IRQS SIOCON.3
Transmit Complete
Figure 14-5. Serial Timing Transmit-Receive Mode rising, SIOCON.4
14-4
KS86C4204/C4208/P4208
SERIAL INTERFACE
Shift Clock Data Input
Data Output
High Impedance
IRQ5
Start
Transmit Complete
Figure 14-6. Serial Timing Receive-Only Mode
PROGRAMMING
VECTOR INITIAL:
0000H 00H, INT_4208 0100H SYM, #00H BTCON, #10100010B CLKCON, #00011000B #0C0H Global/Fast interrupt disable Watch-dog disable non-divided clock 4208 00~BF (After decrease, push data) KS86C4208 only interrupt vector
P0CONL, #10010101B
0.2~0.0 setting
SIOCON, #00100110B SIOPS,
Enable SIO/Interrupt setting baud rate
14-5
SERIAL INTERFACE
KS86C4204/C4208/P4208
PROGRAMMING (Continued)
MAIN:
CALL
SUB_SIO
Data transmit routine
SUB_SIO:
MAIN SIODATA, TRANSBUF SIOCON, #00001000B 1-byte transmission Shift start (8-bit transmit)
INT_4208: INT_SIO:
KS86C4208 just interrupt vector SIOCON #00000011B #00000011B INT_SIO SIOCON, #11111110
SIOCON's pending INT. enable check Pending clear
IRET
14-6
KS86C4204/C4208/P4208
IIC-BUS INTERFACE
OVERVIEW
IIC-BUS INTERFACE
KS86C4204/C4208/P4208 microcontrollers support multi-master IIC-bus serial interface. dedicated serial data line (SDAT) serial clock line (SCLK) carry information between masters peripheral devices which connected IIC-bus. SDAT SCLK lines bi-directional. multi-master IIC-bus mode, multiple KS86C4204/C4208/P4208 microcontrollers receive transmit serial data from slave devices. master KS86C4204/C4208/P4208 which initiates data transfer over IICbus responsible terminating transfer. Standard arbitration functions supported. control multi-master IIC-bus operations, write values following registers: IIC-bus control register, ICCR IIC-bus control/status register, ICSR IIC-bus Tx/Rx data shift register, IDSR IIC-bus address register, When IIC-bus free, SDAT SCLK lines both High level. High-to-Low transition SDAT initiates Start condition. Low-to-High transition SDAT while SCLK remains steady High level initiates Stop condition. Start Stop conditions always generated master. 7-bit address value first data byte that onto after Start condition initiated determines which slave device master selects. determines direction transfer (read write). Every data byte that onto SDAT line must total eight bits. number bytes which sent received transfer operation unlimited. Data always sent most-significant (MSB) first every byte must immediately followed acknowledge (ACK) bit.
IIC-BUS INTERFACE
KS86C4204/C4208/P4208
MULTI-MASTER IIC-BUS CONTROL REGISTER (ICCR) multi-master IIC-bus control register, ICCR, located address F2H. read/write addressable. ICCR settings control following IIC-bus functions: acknowledge signal (ACK) enable suppress IIC-bus clock source selection (fosc/16 fosc/512) Transmit/receive interrupt enable disable Transmit/receive interrupt pending control 4-bit prescaler serial transmit clock (SCLK) KS86C4204/C4208/P4208 interrupt structure, IIC-bus Tx/Rx interrupt assigned level IRQ2, vector F8H. enable this interrupt, ICCR.5 "1". Program software then poll IIC-bus Tx/Rx interrupt pending (ICCR.4) detect IIC-bus receive transmit requests. When acknowledges interrupt request from IIC-bus, interrupt service routine must clear interrupt pending condition writing ICCR.4. frequency determined IIC-bus clock source selection (fosc/16 fosc/512) 4-bit prescaler value ICCR register (see Figure 15-1).
MULTI-MASTER IIC-BUS CONTROL REGISTERS (ICCR) F2H,
IIC-bus acknowledge (ACK) enable bit: Disable generation Enable generation IIC-bus clock source selection bit: fosc/16 fosc/512
IIC-bus transmit (Tx) clock prescaler: IIC-bus transmit clock (SCLK) frequency determined clock source selection (ICCR.6) this 4-bit prescaler value, according following formula: clock (SCL) IICLK/(ICCR.3-ICCR.0)
where IICLK fosc/16 (ICCR
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