ATL60/ATLS60 Gate Array/Embedded Array Description. ATL60 ATLS60

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ATL60/ATLS60 Gate Array/Embedded Array Description. ATL60 ATLS60

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ATL60GA-3.6-03/02
ATL60/ATLS60 Gate Array/Embedded Array
Description. ATL60 ATLS60 Array Organizations: Tables Design Design Systems Supported Design Tools Design Flow Definition Requirements ATL60 Gate Array Design Flow Design Options VHDL/Verilog-HDL ASIC Design Translation. Design Entry FPGA Conversions Macro Cores. AVR(8-bit RISC) Microcontroller (8515). ARM7TDMIEmbedded Microcontroller Core OakDSPCore. Volt Characteristics: Table. Volt Characteristics: Table. Volt Characteristics: Table. Buffer Characteristics: Table Buffers Options Characteristics Source CMOS Power Dissipation 1-10 Power Calculation. 1-10 ATL60 Power Estimation Worksheet. 1-10 Power Estimation Worksheet Examples. 1-11 Timing Derating Factors 1-17 ATL60 Volt Derating Factors. 1-17 ATL60 Volt Derating Factors. 1-17 Power/Ground 1-18 Power/Ground Rules. 1-18 Fixed Power/Ground Pads 1-18
ATL60GA-3.6-03/02
Description
ATL60 Embedded Arrays fabricated using 0.6µm drawn gate, triple level metal process. Extensive cell libraries available support major software tools. with Atmel ASIC families, customer involvement satisfaction integral steps design flow. variety Design Testability techniques wide packaging options available. ATLS60 version utilizes fine pitch staggered bond pads achieve smallest size possible given count. ATLS60 only available limited number PQFP packages.
ATL60 Array Organization
Device Number Gates Routable Gates Count Pins Gate(1) Speed
ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60/1100
4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000
3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000
ATLS60 Array Organization
Device Number Gates Routable Gates Count Pins Gate(1) Speed
ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256
Note:
12,500 20,400 30,200 44,600 55,300 96,500 113,500 148,200
8,000 13,000 17,500 26,000 32,500 57,000 67,500 88,000
Nominal Input NAND Gate with
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Design
Design Systems Supported
Atmel supports several major software systems with complete macro cell libraries, well utilities netlist verification accurate delay simulations. CadenceVerilog-XLis Atmel's golden simulator. MentorQuickSim IIand SynopsysVSSare signoff level simulators.
following design systems supported:
System Cadence
Design Flow
Atmel provides four methods implementing gate array design, while maintaining same basic design flow each them. This flow involves both itic acceptance steps, seen from chart below. Database Acceptance occurs when Atmel receives accepts complete design database. Preliminary esign Review follow Caden simulation verification Atmel. This includes functional well timing performance evaluation. Upon completion this critical step, Atmel performs physical place-and-route. Additional simulations performed, based physical design, including generation back annotation report provide customer with most accurate timing information available. Final Design Review last step design flow prior generation masks. After this acceptance step completed, masks generated released, prototype parts, ceramic packages, delivered.
Tools Opus- Schematic Capture Veritime- Static Timing Verilog Simulator High Level Design Floor Planning ViewDRAW- Schematic Capture ViewSIM Simulator MotiveTM- Static Timing Neted- Schematic Capture QuickSIMII- Simulator Autologic- Synthesis Quick Path- Static Timing VSS- Simulator VHDL Simulation- Vital Libraries Design Compiler- Synthesis Test Compiler- Scan Insertion ATPG ACEPlus- Schematic Capture Veribest- Simulator VHDL Simulation- Vital Libraries Leonardo- Synthesis TestGen- Scan Insertion ATPG
1016A
Viewlogic
Mentor
Synopsys
Definition Requirements
corner pads each reserved programmable Power Ground only. other buffer pins fully programmable Input, Output, Bidirectional, Clock-into-Array, Power Ground.
VeribestModel TechExemplarSunrise
ATL60GA-3.6-03/02
ATL60 Gate Array Design Flow
Design Options
VHDL/Verilog-HDL
Atmel accept Register Transfer Level (RTL) designs VHDL (MIL-STD-454, IEEE 1076) VerilogHDLformat. Atmel fully supports Synopsys VHDLsimulation well synthesis. VHDL Verilog-HDL Atmel's preferred database format Gate Array/ Embedded Array design.
FPGA Conversions
Atmel successfully translated existing FPGA/PLD designs from most major vendors (Xilinx ActelTM, AlteraTM, AMDand Atmel) into gate arrays. There four primary reasons convert from FPGA/PLD gate array. Conversion high volume devices single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing onboard space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, gate array provide lower cost answer long-term volume production.
ASIC Design Translation
Atmel successfully translated existing designs from most major ASIC vendors (LSI LogicTM, MotorolaTM, SMOSTM, OkiTM, NECTM, FujitsuTM, AMIand others) into gate arrays. These designs have been optimized speed gate count modified logic memory, replicated pin-for-pin compatible, dropin replacement.
Design Entry
Design entry performed customer using Atmel provided macro cell library. complete netlist vector must provided Atmel. Upon acceptance this data set, Atmel continues with standard design flow.
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Macro Cores
AVR(8-bit RISC) Microcontroller (8515)
RISC Microcontroller true 8-bit RISC Architecture, ideally suited embedded control applications. offered gate level, soft macro ATL60 family. supports powerful instructions. pre-fetches instruction during prior instruction execution, enabling execution instruction clock cycle. Fast Access RISC register file consists general purpose working registers. These registers eliminate data transfer delay traditional program code intensive accumulator architectures. incorporate program memory (ROM) data memory (SRAM). Also included several optional peripherals: UART, 8-bit timer/ counter, timer/counter, external internal interrupts programmable watchdog timer. control signals facilitate exploitation fast local access modes offered industry standard dynamic SRAMs. ARM7TDMI core includes several optional peripheral macros. options offered Real Time Clock, Controller, USART, External Interface, Interrupt, Timer Advanced Power Management Controller.
OakDSPCoreAtmel's embedded OakDSPCore 16-bit, generalpurpose low-power, low-voltage high-speed Digital Signal Processor (DSP). designed mid-to-high-end telecommunications consumer electronics applications, where lowpower portability major requirements. Among applications supported digital cellular telephones, fast modems, advanced facsimile machines hard disk drives. available core Atmel's Gate Array cell library, utilized engine DSP-based Gate Array/Embedded Array. specified with several levels modularity SRAM, ROM, blocks, allowing efficient DSP-based Gate Array/Embedded Array development. aimed achieving best cost-performance factor given (small) silicon area. element system-on-chip, takes into account such requirements program size, data memory size, glue logic, power management, etc. core consists three main execution units operating parallel: Computation/Bit-Manipulation Unit (CBU), Data Addressing Arithmetic Unit (DAAU) Program Control Unit (PCU). Core also contains SRAM addressing units, Program Control Logic (PCL). other peripheral blocks, which application specific, defined part user-specific logic, implemented around core same silicon die. enhanced general microprocessor functions meet application requirements. programming model instruction aimed straightforward generation efficient compact code.
ARM7TDMIEmbedded Microcontroller Core
ARM7TDMI (Advanced RISC Machines) powerful 32-bit processor offered embedded core ATL60 series arrays. ARM7TDMI member Advanced RISC Machines (ARM) family general purpose 32-bit microprocessors, which offer high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related decode mechanism much simpler than those microprogrammed Complex Instruction Computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective chip. Pipelining employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. memory interface been designed allow performance potential realized without incurring high costs memory system. Speed critical control signals pipelined allow system control functions implemented standard low-power logic, these
ATL60GA-3.6-03/02
Absolute Maximum Ratings*
Operating Temperature -55°C +125°C Storage Temperature -65°C +150°C Voltage with Respect Ground .-0.6V VDD+0.75V1 Maximum Operating Voltage 6.0V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Note: Minimum voltage -0.6V which undershoot -2.0V pulses less than Maximum output voltage 0.75V which overshoot +7.0V pulses less
than
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, 4.5V 5.5V (unless otherwise noted).
Symbol Parameter Test Condition Units
Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current P01(2mA Buffer)(1) Input Voltage CMOS Input Voltage Input High Voltage CMOS Input High Voltage Switching Threshold CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage Output High Voltage Output buffer stages drive capability with stage
VIN=VDD, DD=5.5V VIN=VSS, DD=5.5V VIN=VSS, DD=5.5V VIN=VDD VSS, DD=5.5V VIN=0, VDD=5V, VOUT=VDD VIN=VDD=5V, VOUT=VSS
VDD=5.0V, 25°C VDD=5.0V, 25°C IOL=as rated VDD=4.5V
IOH=as rated VDD=4.5V
Note: This specification Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Volt Characteristics
Applicable over recommended operating range from -55°C +125°C, 2.7V 3.6V (unless otherwise noted).
Symbol Parameter Test Condition Units
Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current P01(1mA Buffer) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage. Output High Voltage Output buffer stages drive capability with stage.
VIN=VDD, VDD=3.6V VIN=VSS, VDD=3.6V VIN=VSS, VDD=3.6V VIN=VDD VSS, VDD=3.6V VDD=3.3V, VOUT=VDD VDD=3.3V, VOUT=VSS 0.7xVDD VDD=3.0V, 25°C IOL=as rated VDD=2.7V 0.11
IOH=as rated VDD=2.7V
0.7xVDD
Volt Characteristics
Applicable over recommended operating range from +70°C, (unless otherwise noted).
Symbol Parameter Test Condition Units
Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current P01(0.5 Buffer)(1) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with 0.5mA stage. Output High Voltage Output buffer stages drive capability with -0.5mA stage.
VIN=VDD, DD=2.2 VIN=VSS, DD=2.2V VIN=VSS, DD=2.2V VIN=VDD VSS, DD=2.2V VDD=2.0V, OUT=VDD VDD=2.0V, OUT=VSS 0.8xVDD VDD=3.0 25°C IOL=as rated VDD=1.8
IOH=as rated VDD=1.8
0.8xVDD
Note: This specification Buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
ATL60GA-3.6-03/02
Buffer Characteristics
Symbol Parameter Test Condition Units
COUT CI/O
Schmitt Trigger
Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bi-Directional Positive Threshold CMOS Positive Threshold Negative Threshold CMOS Negative Threshold Hysteresis CMOS Hysteresis CMOS Positive Threshold CMOS Negative Threshold CMOS Hysteresis
5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 3.3V 25°C, 3.3V 25°C, 3.3V
Buffers
Programmable output drive IOL, 5.0V 3.3V) ATL60 series input/output ring contains buffer circuitry capable sourcing sinking currents responds CMOS logic levels. locations this ring accommodate bidirectional Tri-Statecells.
Options
Input, Output, Bi-directional, Tri-StateOutput, Internal Clock Driver Oscillator Output Drive Value Programmable from increments CMOS Operation Schmitt Trigger (Bi-directional, Input) Inverting Non-inverting Input Buffers (Bi-directional, Input) Pull-Up Resistor 372K (Low values invalidate specification) Pull-Down Resistor 124K (Low values invalidate specification)
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Characteristics
Delay
Delay Fanout
Prop Delay (ns)
Prop Delay (ns)
Prop Delay (ps)
Volts Volts Volts
Volts Volts
Fanout
input NAND Temp
input NAND Temp
Delay Temperature
Output Buffer Load
Prop Delay (ns) Prop Delay (ps)
Prop Delay (ns)
Temperature Volts Volts input NAND
Volts Volts
Capacitive Load (pF)
Output Buffer Temp
ATL60GA-3.7-10/98 ATL60GA-3.6-03/02
Source CMOS Power Dissipation
There primary components standard CMOS power consumption. major portion power dissipation related charging discharging gate interconnect capacitance during switching. directly varies with capacitance load, square supply voltage, frequency V**2 Quiescent stand-by power dissipation comes primarily from parasitic leakage paths. through reverse bias junctions inherent CMOS second subthreshold source drain current transistors their state. Quiescent Power 0.025 W/Gate (typical) Atmel provides methodology calculating both components separately. power factors given following calculations accurate within percent.
Flip Flop Power Equation:
(uW) [7.0(1-DC) (15.7 .45X/2)*DC] Fc(MHz) (uW) 3.3V [2.5(1-DC) (5.5 0.20X/2)*DC] Fc(MHz)
Where; Duty Cycle cycles data changes/# clock cycles Clock frequency average output load FF(logic+wire)in unit loads number Peak current volt recommended that Gate Array/Embedded Array have least power ground each peak current.
Gate Power Estimation:
(uW) (.84 .45X) *Fc(MHz) (uW) 3.3V (.46 0.20X) *Fc(MHz)
Power Calculation
Switching power divided into sequential cell (FF) power, combinational cell power, POWER. Flip flops latches have internal clock buffering, therefore dissipate power when clock active, even data changing. This shown below (duty cycle). other power numbers assume 100% duty cycle, that cell output switches every time input switches.
Where; total gates less duty cycle (typically .20)
Power:
(uW) 12.5 (uW) 3.3V
Where; average output load number outputs Output frequency Duty Cycle
Volt Parameters
Duty Cycle 100% Peak Current (Ip) Load Factor Load Factor 15.7 0.45 0.45 12.5 Gates Units uW/MHz uW/MHz uW/MHz/Unit Load uW/MHz/Pf
ATL60 Power Estimation Worksheet
following pages Power Estimation Worksheets otal consumption. Worksheet Examples have been provided used reference chip power calculation. directions below explain worksheets. each clock domain, fill Flip Flop Power Estimation Worksheet associated Gate Power Workstation.
0.84
16-30
Volt Parameters
Duty Cycle 100% Peak Current (Ip) Load Factor Load Factor 0.20 0.20 Gates Units uW/MHz uW/MHz uW/MHz/Unit Load uW/MHz/Pf
Complete Power Consumption Worksheet. results sheets whole chip power estimation. estimated power calculate transistor junction temperature. junction temperature simulations.
16-30
1-10
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Power Estimation Worksheet Examples
Assume following design: volt ,100K used gates with clock domains. Domain gates 1500 Flip Flops running 50MHz, with duty cycle average output load 3U.L. data frequency 25MHz with duty cycle average gate loading 3U.L. Domain gates Flip Flops running 12MHz with duty cycle average load 4U.L. data frequency 6MHz having duty cycle average gate loading 4U.L. There Output buffers Bi-directional buffers with frequency 20MHz, duty cycle average capacitive load 40pf. Note that with duty cycle mean estimated percentage that Flip Flop logic gate transitions relative clock data frequency. example, Flip Flop transitions Flip Flop clock frequency duty cycle would 100%. more typical value would 0.3. Likewise combinational logic. Data transition through logic practice might only transition cycles, leading duty cycle 0.2.
Flip Flop Power Estimation Worksheet Example Domain
Description Variables Values
Number Flip Flop Flip Flop Clock Frequency Duty Cycle (Flip Flop output transitions/clock cycles) Average Loading, wire capacitance Flip Flop
1500 50MHz
Volt
[7(1-DC)+(15.7+.45X/2)*DC]N*Fc Power Consumed Flip Flops 736mW
Gate Power Estimation Worksheet Example Domain
Description Variables Values
Number Gates (not including Flip Flop) Data Frequency (typically 1/2Fc) Duty Cycle (%of that data changes, typically 0.4) Average Loading, wire capacitance gate
25MHz
Volt
(.84+.45X)*G*DC*Fd (.84+.45*3)*60,000*0.2*25 Power Consumed Gates 657mW typical value Unit Loads
1-11
ATL60GA-3.6-03/02
Flip Flop Power Estimation Worksheet Example Domain
Description Variables Values
Number Flip Flop Flip Flop Clock Frequency Duty Cycle (Flip Flop output transitions/clock cycles) Average Loading, wire capacitance Flip Flop
1000 12MHz
Volt
[7(1-DC)+(15.7+.45X/2)*DC]N*Fc Power Consumed Flip Flops 130mW
Gate Power Estimation Worksheet Example Domain
Description Variables Values
Number Gates (not including Flip Flop) Data Frequency (typically 1/2Fc) Duty Cycle that data changes, typically 0.4) Average Loading, wire capacitance gate
6MHz
Volt
(.84+.45X)*G*DC*Fd (.84+.45*4)*40,000*0.4*6 Power Consumed Gates 253mW Typical Value Unit Loads
1-12
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Power Estimation Worksheet Example
Description Variables Values
Number Outputs/Bidis State Buffers Data Frequency Duty Cycle that data changes, typically 0.5) Average Capacitive Loading (pf)
20MHz
Volt
(16+12.5P)*N*Fd*DC (16+12.5*40)*90*20*0.4 Total Power Consumed
Estimated Chip Power
Domain
Flip Flop Power Gate Power 736mW 657mW 130mW 253mW
Domain
Flip Flop Power Gate Power
Power
372mW Total 2.15Watt
1-13
ATL60GA-3.6-03/02
ATL60 Flip Flop Power Estimation Worksheet
Description Variables Values
Number Flip Flop Flip Flop Clock Frequency Duty Cycle (Flip Flop output transitions/clock cycles) Average loading, wire capacitance Flip Flop
Volt
Power Consumed Flip Flops
Volt
Power Consumed Flip Flops
1-14
ATL60 Gate Arrays
ATL60GA-3.6-03/02
ATL60 Combinational Gate Power Estimation Worksheet
Description Variables Values
Number Gate (not including Flip Flop) Data Frequency (typically Duty Cycle that data changes, typically 0.4) Average loading, wire capacitance gate
Volt
P=(.84+0.45X)*G*DC*Fd Process Consume Gates
Volt
P=(.46+0.20X)*G*DC*Fd Power Consumed Gates typical value Unit Loads
1-15
ATL60GA-3.6-03/02
ATL60 Power Estimation Worksheet
Description Variables Values
Number Outputs/Bidis State Buffers Data Frequency Duty Cycle that data changes, typically 0.5) Average Capacitive Loading (pf)
Volt
P=(16+12.5*P)*N*Fd*DC Total Power Consumed
Volt
P=(7+5.4*P)*N*Fd*DC Total Power Consumed
1-16
ATL60 Gate Arrays
ATL60GA-3.6-03/02
Timing Derating Factors
Cell timing generated from comprehensive transistor level circuit simulation over variations temperature, voltage, loading process variations. Cell Library section includes pin-to-pin timing. Delays represented mx+b form, where intrinsic delay through cell (zero load), output load load factor. delay expressed nanoseconds. Load factors nanoseconds picofarad output buffers nanoseconds unit load internal cells. unit load channel channel transistor gate. Cell Library section contains numbers each input output path, output rising output falling, under nominal conditions. sequential logic, hold times used, worst case values military environment. measurements, timing measured from rising falling edge data (50% rising edge clock (50% DD). Hold measurements taken from rising edge clock rising falling edge data pin. hold times negative, value zero. Simulation libraries contain individual derating each cell, provid most accurate delay numbers possible. tables below show total derating ctors milita industrial rcial environments.
ATL60 Volt Derating Factors
Process Derating Factors
Best Case Worst Case
0.748
1.265
Combined Derating Factors Voltage, Temperature, Process
Conditions Best Case Worst Case
Military Industrial Commercial
(4.5 Volts Volts) (-55°C 125°C)
0.550 0.60 0.67
1.600 1.45 1.40
ATL60 Volt Derating Factors
Process Derating Factors
Best Case Worst Case
0.748
1.265
Combined Derating Factors Voltage, Temperature, Process
Conditions Best Case Worst Case
Military Industrial Commercial
(2.7 Volts 3.9Volts) (-55°C 125°C)
0.55 0.61 0.67
1.75 1.53 1.49
1-17
ATL60GA-3.6-03/02
Power/Ground
Simultaneous switching outputs result large transient currents. Since board, package, chip ground wiring finite impedance, this current produces transient increase local ground voltage, known ground bounce. buffer site containing input buffer experiences sufficient ground bounce, input data erroneously detected buffer. Ground bounce also adversely affect speed performance both input output buffers. Several steps taken help alleviate ground bounce problems. only minimum drive buffers necessary achieve required output switching speeds. Atmel allows output drive single programmed increments from 2-24 Adding extra power ground pins will lessen ground bounce. Power ground distribution provided dedicated pins each corner die, plus additional power ground pins that placed location side. dedicated corner pins supply power ground both ring internal array. Corner pins either power ground. custom package designs, these pins connect inductance resistance power ground paths external package pins. maximum, power ground together handle simultaneous switching output current. example, buffers would require minimum power ground pin. Power ground pins supply both input output buffers, separate input output buffers specified. Generally, simultaneously switching inputs outputs should grouped separately with additional supply pins between groups. Choice input buffers also impacts number power ground pins required. buffer with switching point 2.0V more susceptible ground bounce noise than CMOS buffer. Unless other requirements dictate level inputs, CMOS buffer switching 2.5V will offer more noise immunity. excessively noisy environments, Schmitt Trigger input available. Rigorous solution ground bounce problem requires simulation board, package chip together, with accurate models inductance, resistance capacitance power distribution buffer loads. Atmel will provide transistor level simulation results specific applications required.
Power/Ground Rules
simultaneous switching current between power ground pins maximum allowed Group inputs together outputs together, with supply pins between groups Group bi-directional buffers with common Tri-Statecontrol
Fixed Power/Ground Pads
corner pins fixed power ground.
other pins fully programmable
1-18
ATL60 Gate Arrays

ATL60/ATLS60 Gate Array/Embedded Array Description. ATL60 ATLS60

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