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single-chip CMOS microcontroller been designed highperformance using (Samsung Arrangeable Microcontrollers). Samsung's newest 4-bit core notable energy consumption operating voltage. select from three sizes: bytes. Except difference size, features functions KS57C5204 KS57C5208 identical KS57C5304, KS57C5308, KS57C5312 identical. With it's DTMF generator, watchdog timer function, versatile 8-bit timer/counters, KS57C5204/C5208 /C5304/C5308/C5312 offers excellent design solution wide variety telecommunication applications. pins available 42-pin SDIP 44-pin package KS57C5204/C5208, pins available 30-pin SDIP 32-pin package KS57C5304/C5308/C5312 assign I/O. vectored interrupts KS57C5204/C5208 four vectored interrupts KS57C5304/C5308/C5312 provide fast response internal external events. addition, advanced CMOS technology provides power consumption wide operating voltage range.
KS57C5204/C5208 microcontroller also available (One Time Programmable) version, KS57P5208. KS57C5304/C5308/C5312 microcontroller also available (One Time Programmable) version, KS57P5308/P5312. KS57P5208/P5308/P5312 microcontroller on-chip 8K-byte (P5208/P5308) 12K-byte (P5312) one-time-programable EPROM instead masked ROM. KS57P5208 comparable KS57C5204/C5208, both function configuration. Also, KS57P5308/P5312 comparable KS57C5304/C5308/C5312, both function configuration.
FEATURES
Memory 4-bit 4,096 8-bit (KS57C5204/C5304) 8,192 8-bit (KS57C5208/C5308) 12,288 8-bit (KS57C5312) format Interrupts external interrupt vectors (KS57C5204/C5208) external interrupt vectors (KS57C5304/C5308/C5312) internal interrupt vectors quasi-interrupts
Pins Input only: pins (KS57C5204/C5208) pins (KS57C5304/C5308/C5312) I/O: pins (KS57C5204/C5208) pins (KS57C5304/C5308/C5312) N-channel open-drain I/O: pins
Power-Down Modes Idle: Only clock stops Stop: System clock stops
Memory-Mapped Structure Data memory bank
Oscillation Sources Crystal, ceramic main system clock Main system clock frequency: 0.4-6.0 (typical) clock divider circuit
DTMF Generator dual-tone frequencies tone dialing
8-Bit Basic Timer Programmable interval timer Watchdog timer Instruction Execution Times 0.95, 1.91, 15.3 4.19 1.12, 2.23, 17.88 3.58 0.67, 1.33, 10.7
8-Bit Timer/Counters Programmable 8-bit timer External event counter function Arbitrary clock frequency output
Operating Temperature
Watch Timer Real-time time interval generation Four frequency outputs
Operating Voltage Range
Package Types SDIP, (KS57C5204/C5208) SDIP, (KS57C5304/C5308/C5312)
Sequential Carrier Supports 16-bit serial data transfer arbitrary
BLOCK DIAGRAM
INT0, INT1, INT2, INT4 8-Bit Timer/ Counter 8-Bit Timer/ Counter P6.0-P6.3/ KS0-KS3 P7.0-P7.3/ KS4-KS7 P8.0 P8.3 P9.0 P9.2 Port Port
RESET
XOUT Watchdog Timer
Interrupt Control Block
Clock
Stack Pointer
Basic Timer Watch Timer Input Port P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 P3.2 P3.3 P4.0/BTCO P4.1-4.3 P5.0-P5.3
Internal Interrupts Instruction Decoder Arithmetic Logic Unit
Program Counter
Program Status Word Port Flags Port
Port Port
Port 768x4-Bit Data Memory Program Memory KS57C5204/C5304: 4KBytes KS57C5208/C5308: 8KBytes KS57C5312: 12KBytes Port DTMF Generator
DTMF
NOTE:
KS57C5304/C5308/C5312 does P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, INT1, INT2, INT4, P8.0-P8.3, P9.0-P9.2.
Figure 1-1. Simplified Block Diagram
ASSIGNMENTS
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 XOUT TEST P4.0/BTCO P4.RESET
P3.2 P3.3 P4.2
P9.2 P9.1 P9.0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2 P5.1 P5.0 P8.3 P8.2 P8.1 P8.0 P4.3
Figure 1-2. KS57C5204/C5208 Assignment Diagram (42-SDIP)
KS57C5204/C5208 (42-SDIP-600)
Figure 1-3. KS57C5204/C5208 Assignment Diagram (44-QFP)
P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 XOUT TEST P4.0/BTCO
DTMF P9.0 P9.1 P9.2 P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO
P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0 P5.3 P5.2
KS57C5204 /C5208 (44-QFP-1010B)
P5.0 P8.3 P8.2 P8.1 P8.0 P4.3 P4.2 P3.3 P3.2
RESET
KS57C5304/C5308/C5312 (30-SDIP-400)
XOUT TEST P4.0/BTCO P4.RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 1-4. KS57C5304/C5308/C5312 Assignment Diagram (30-SDIP)
XOUT TEST P4.0/BTCO P4.RESET
P4.2 P4.3 P5.0 P5.1 P5.2 P5.3 P6.0/KS0 P6.1/KS
P3.1/TCL1 P3.0/TCL0 P2.3/BUZ P2.2/CLO P2.1/TCLO1 P2.0/TCLO0 P1.0/INT0 DTMF P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2
Figure 1-5. KS57C5304/C5308/C5312 Assignment Diagram (32-SOP)
KS57C5304/C5308/C5312 (32-SOP-450A)
DESCRIPTIONS Table 1-1. KS57C5204/C5208 Descriptions Name P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 P3.0 P3.1 P3.2 P3.3 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3 Reset Type Value Description 4-bit input port. 1-bit 4-bit read test possible. Each pull-up resistors assignable software. 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. N-channel open-drain push-pull output selected software (1-bit unit) Ports paired support 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit port. 1-bit 4-bit read/write test possible. Individual pins software configurable input output. 4-bit pull-up resistors software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. Number (39) (40) (41) (42) (43) (44) (13) (14) (10) (11) (15) (17) 27-30 (22-25) Share INT0 INT1 INT2 INT4 TCLO0 TCLO1 TCL0 TCL1 Circuit Type
BTCO
P6.0-P6.3 P7.0-P7.3
31-34 (26-29) 35-38 (30-33)
KS0-KS3 KS4-KS7
P8.0-P8.3 P9.0-P9.2
23-26 (18-21) 40-42 (35-37)
Table 1-1. KS57C5204/C5208 Descriptions (Continued) Name Reset Type Value DTMF output. Basic timer clock output External interrupts. triggering edge INT0 INT1 selectable. Quasi-interrupt with detection rising edges External interrupt with detection rising falling edges. Timer/counter clock output Timer/counter clock output Clock output kHz, kHz, kHz, frequency output watch timer clock frequency 4.19 buzzer sound External clock input timer/counter External clock input timer/counter Quasi-interrupt inputs with falling edge detection Description Number (34) (10) (39) (40) (41) (42) (43) (44) Share P4.0 P1.0 P1.1 P1.2 P1.3 P2.0 P2.1 P2.2 P2.3 Circu Type
DTMF BTCO INT0 INT1 INT2 INT4 TCLO0 TCLO1
TCL0 TCL1 KS0-KS3 KS4-KS7
RESET
31-34 (26-29) 35-38 (30-33) (12) (16,
P3.0 P3.1 P6.0-P6.3 P7.0-P7.3
Power supply Ground
RESET
signal
XOUT TEST
Crystal, ceramic oscillator signal main system clock. (For external clock input, input XIN's reverse phase XOUT) Chip test input pin, Hold when device operating. connection
NOTE: Parentheses indicate number package.
Table 1-2. KS57C5304/C5308/C5312 Descriptions Name P1.0 Type Description 1-bit input port. 1-bit 4-bit read test possible. Each pull-up resistors assignable. 4-bit port. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. N-channel open-drain push-pull output selected software (1-bit unit). Ports paired enable 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write test possible. Each individual assignable input output. 4-bit pull-up resisters software assignable input pins automatically disabled output pins. Ports paired enable 8-bit data transfer. Number (25) Share INT0 Circuit Type
P2.0 P2.1 P2.2 P2.3
(26) (27) (28) (29)
TCLO0 TCLO1
P3.0 P3.1 P4.0 P4.1 P4.2 P4.3 P5.0-P5.3
(30) (31) (10) 10-13 (11-14)
TCL0 TCL1 BTCO
P6.0-P6.3 P7.0-P7.3
14-17 (15-18) 18-21 (19-22)
KS0-KS3 KS4-KS7
Table 1-2. KS57C5304/C5308/C5312 Descriptions (Continued) Name DTMF INT0 TCLO0 TCLO1 Type DTMF output. External interrupt input. triggering edge INT0 selectable. Timer/counter clock output Timer/counter clock output Clock output kHz, kHz, kHz, frequency output watch timer clock frequency 4.19 buzzer sound External clock input timer/counter External clock input timer/counter Basic timer clock output Power supply Ground Crystal, ceramic oscillator signal main system clock. (For external clock input, input XIN's reverse phase XOUT) connection Chip test input pin, Hold when device operating.
RESET
Description
Number (23) (25) (26) (27) (28) (29)
Share P1.0 P2.0 P2.1 P2.2 P2.3
Circuit Type
TCL0 TCL1 BTCO XOUT TEST
RESET
(30) (31) (32) 14-17 (15-18) 18-21 (19-22)
P3.0 P3.1 P4.0
P6.0-P6.3 P7.0-P7.3
signal
KS0-KS3 KS4-KS7
Quasi-interrupt inputs with falling edge detection
NOTE: Parentheses indicate number 32-SOP package.
1-10
CIRCUIT DIAGRAMS
P-Channel Pull-Up Resistor
N-Channel
Schmitt Trigger
Figure 1-6. Circuit Type
Figure 1-8. Circuit Type
Pull-Up Resistor P-Channel Resistor Enable Data P-Channel Output DIsable Schmitt Trigger N-Channel
Figure 1-7. Circuit Type
Figure 1-9. Circuit Type
Pull-up Resistor Pull-up Enable Data Output DIsable P-Channel
Pull-up Resistor Pull-up Resistor Enable
Circuit Type
Data
P-Channel
Output Disable
N-Channel
Figure 1-10. Circuit Type
Figure 1-12. Circuit Type
Pull-up Resistor Pull-up Enable Data Output Disable P-Channel
Circuit Type
DTMF
Output Disable
Schmitt Trigger
Figure 1-11. Circuit Type
Figure 1-13. Circuit Type
1-12
SPACES
ADDRESS SPACES
PROGRAM MEMORY (ROM)
maps mask programmable factory. standard configuration, device's 4,096 8-bit (KS57C5204/C5304) 8,192 8-bit (KS57C5208/C5308) 12,288 8-bit (KS57C5312) program memory have three areas that directly addressable program counter (PC): 16-byte area vector addresses 16-byte general-purpose area 96-byte instruction reference area 3,968-byte general-purpose area (KS57C5204/C5304) 8,064-byte general-purpose area (KS57C5208/C5308) 12,106-byte general-purpose area (KS57C5312) General-Purpose Program Memory program memory areas allocated general-purpose use: area bytes size other 3,968 bytes (KS57C5204/C5304), 8,064 bytes (KS57C5208/C5308), 12,106 bytes (KS57C5312). Vector Addresses 16-byte vector address area used store vector addresses required execute system resets interrupts. Start addresses interrupt service routines stored this area, along with values enable memory bank (EMB) enable register bank (ERB) flags that used initialize corresponding service routines. 16-byte area used alternately general-purpose ROM. Instructions Locations 0020H-007FH used reference area (look-up table) 1-byte instructions. instruction reduces byte size instruction operands. reference 2-byte instruction, 1-byte instructions, three-byte instructions which stored look-up table. Unused look-up table addresses used general-purpose ROM.
ADDRESS SPACES
Table 2-1. Program Memory Address Ranges Area Function Vector address area General-purpose program memory instruction look-up table area General-purpose program memory Address Ranges 0000H-000FH 0010H-001FH 0020H-007FH 0080H-0FFFH 0080H-1FFFH 0080H-2FFFH Area Size Bytes) 3,968 (KS57C5204/C5304) 8,064 (KS57C5208/C5308) 12,106 (KS57C5312)
GENERAL-PURPOSE MEMORY AREAS 16-byte area locations 0010H-001FH 3,968-byte (KS57C5204/C5304) area locations 0080H-0FFFH, 8,064-byte (KS57C5208/C5308) area locations 0080H-1FFFH, 12,106-byte (KS57C5312) area locations 0080H-2FFFH used general-purpose program memory. Unused locations vector address area instruction look-up table areas used general-purpose program memory. However, care must taken overwrite live data when writing programs that specialpurpose areas ROM. VECTOR ADDRESS AREA 16-byte vector address area used store vector addresses executing interrupts. starting addresses interrupt service routines stored this area, along with enable memory bank (EMB) enable register bank (ERB) flag values that needed initialize service routines. 16-byte vector addresses organized follows: PC13 PC12 PC11 PC10
vector address area specific programs, instruction VENTn. programming tips next page explain this.
NOTE: used KS57C5204/C5304 value always "0". used KS57C5208/C5308 value always "0".
SPACES
0000H Vector Address Area Bytes) 000FH 0010H General- Purpose Area Bytes) 001FH 0020H Instruction Reference Area Bytes) 007FH 0080H KS57C5204/5304 (3,968 Byte) 0FFFH 1000H KS57C5208/5308 (8,064 Byte) 1FFFH KS57C5312 (12,106 Byte) 2FFFH General-Purpose Area NOTE: General-Purpose Area General-Purpose Area 0000H 0002H 0004H 0006H 0008H 000AH 000CH 000EH
RESET
INTB/INT4(note) INT0 INT1(note) implemonted (Reseved future use) INTT0 INTT1 implemented (Reseved future use)
KS57C5304/5308/5312 does INT1 INT4 interrupts.
Figure 2-1. Address Structure
Figure 2-2. Vector Address
ADDRESS SPACES
PROGRAMMING Defining Vectored Interrupts
following examples show several ways define vectored interrupt instruction reference areas program memory: When vector interrupts used: VENT0 VENT1 VENT2 VENT3 VENT5 VENT6 0000H 1,0,RESET 0,0,INTB 0,0,INT0 0,0,INT1 (note) Jump RESET address Jump INTB address Jump INT0 address Jump INT1 address
0,0,INTT0 0,0,INTT
Jump INTT0 address Jump INTT1 address
When specific vectored interrupt such INT0, INTT0 used, unused vector interrupt locations must skipped with assembly instruction that jumps will address correct locations: VENT0 VENT1 VENT3 VENT6 0000H 1,0,RESET 0,0,INTB 0006H 0,0,INT1 (note) 000CH 0,0,INTT1 0010H Jump RESET address Jump INTB address INT0 interrupt used Jump INT1 address INTT0 interrupt used Jump INTT1 address
INT0 interrupt used corresponding vector interrupt area fully utilized, written instruction Example malfunction will occur: VENT0 VENT1 VENT3 VENT5 VENT6 0000H 1,0,RESET 0,0,INTB 0,0,INT1 (note) Jump RESET address Jump INTB address Jump INT1 address INT0
0,0,INTT0 0,0,INTT1 0010H
used vector address Jump INTT1 address INTT0
this example, when INTT0 interrupt generated, corresponding vector area VENT5 INTT0, VENT6 INTT1. This causes INTT0 interrupt jump incorrectly INTT1 address causes malfunction occur.
NOTE: KS57C5304/C5308/C5312 does INT1 interrupt.
SPACES
INSTRUCTION REFERENCE AREA Using 1-byte instructions, easily reference instructions with larger byte sizes that stored addresses 0020H-007FH program memory. This 96-byte area called instruction reference area, look-up table. Locations look-up table contain one-byte instructions, single two-byte instruction, three-byte instruction such (jump) CALL. starting address instruction referencing must always even number. reference CALL instruction, must written reference area two-byte format: this format TJP; CALL, TCALL. instructions execute instructions larger than byte. There three ways instruction: Using 1-byte instruction execute 2-byte 1-byte instructions, Branching location referencing branch instruction stored look-up table, Calling subroutines location referencing call instruction stored look-up table.
PROGRAMMING Using Look-Up Table
Here example instruction look-up table: JMAIN KEYCK WATCH INCHL BTSF TCALL INCS 0020H MAIN KEYFG CLOCK @HL,A MAIN KEYFG check call CLOCK (HL)
EA,#00H 0080
#00H
MAIN
KEYCK JMAIN WATCH INCHL
BTSF KEYFG (1-byte instruction) KEYFG jump MAIN (1-byte instruction) KEYFG call CLOCK (1-byte instruction) @HL,A INCS EA,#00H (1-byte instruction)
ADDRESS SPACES
DATA MEMORY (RAM)
OVERVIEW standard configuration, 4-bit data memory five areas: 4-bit working register area 4-bit general-purpose area (also used stack area) 4-bit general-purpose area 4-bit area peripheral hardware make easier reference, data memory area four memory banks bank bank bank bank select memory bank instruction (SMB) used select bank want select working data memory. Data stored locations 8-bit addressable. Initialization values data memory area defined hardware must therefore initialized program software following RESET. However, when RESET signal generated power-down mode, data memory contents held.
000H 01FH 020H
Working Registers Bits) General-purpose Registers Stack Area (224 Bits) Bank
0FFH 100H
General-purpose Registers (256 Bits) 1FFH 200H General-purpose Registers (256 Bits) 2FFH F80H
Bank
Bank
Memory-mapped Aeeress Registers (128 Bits)
Bank
FFFH
Figure 2-3. Data Memory (RAM)
SPACES
Memory Banks Bank (000H-0FFH) lowest nibbles bank (000H-01FH) used working registers; next nibbles (020H-0FFH) used both stack area general-purpose data memory. stack area implementing subroutine calls returns, interrupt processing. nibbles bank (100H-1FFH) general-purpose use. nibbles bank (200H-2FFH) general-purpose microcontroller uses bank memory-mapped peripheral I/O. Fixed locations each peripheral hardware register: port latches, timers, peripherals controls, etc. mapped into this area.
Bank Bank Bank
(100H-1FFH) (200H-2FFH) (F80H-FFFH)
Data Memory Addressing Modes enable memory bank (EMB) flag controls addressing mode data memory banks When flag logic zero, addressable area restricted specific locations, depending whether direct indirect addressing used. With direct addressing, access locations 000H-07FH bank bank With indirect addressing, only bank (000H-0FFH) accessed. When flag logic one, four data memory banks accessed according current value. 8-bit addressing, 4-bit registers addressed register pair. Also, when using 8-bit instructions address locations, remember even-numbered register address instruction operand. Working Registers working register area data memory bank further divided into four register banks (bank Each register bank eight 4-bit registers paired 4-bit registers 8-bit addressable. Register used 4-bit accumulator register pair 8-bit extended accumulator. carry flag also used 1-bit accumulator. Register pairs used address pointers indirect addressing. limit possibility data corruption incorrect register addressing, advisable register bank main program banks interrupt service routines.
ADDRESS SPACES
Table 2-2. Data Memory Organization Addressing Addresses 000H-01FH 020H-0FFH 100H-1FFH 200H-2FFH F80H-FFFH Register Areas Working registers Stack general-purpose registers General-purpose registers General-purpose registers Peripheral hardware registers Bank Value Value
PROGRAMMING Clearing Data Memory Banks Clear banks data memory area: RAMCLR BITS INCS INCS HL,#00H A,#0H @HL,A RMCL1 HL,#10H @HL,A RMCL0 (100H-1FFH) clear
RMCL
(010H-0FFH) clear
RMCL0
SPACES
WORKING REGISTERS Working registers, mapped address 000H-01FH data memory bank used temporarily store intermediate results during program execution, well pointer values used indirect addressing. Unused registers used general-purpose memory. Working register data manipulated 1-bit units, 4-bit units using paired registers, 8-bit units.
000H 001H 002H 003H 004H 005H Data Memory Bank 006H 007H 008H 00FH 010H 017H 018H 01FH Register Bank Register Bank Register Bank Working Register Bank
Figure 2-4. Working Register
ADDRESS SPACES
Working Register Banks addressing purposes, working register area divided into four register banks bank bank bank bank these banks selected working register bank register bank selection instruction (SRB setting status register bank enable flag (ERB). Generally, working register bank used main program, banks interrupt service routines. Following this convention helps prevent possible data corruption during program execution contention register bank addressing. Table 2-3. Working Register Organization Addressing Setting Settings NOTE: applicable.
Selected Register Bank Always bank Bank Bank Bank Bank
Paired Working Registers Each register banks subdivided into eight 4-bit registers. These registers, named either manipulated individually using 4-bit instructions, together register pairs 8-bit data manipulation. names 8-bit register pairs each register bank Registers always become lower nibble when registers addressed 8-bit pairs. This makes total eight 4-bit registers four 8-bit double registers each four working register banks.
(MSB)
(LSB)
(MSB)
(LSB)
Figure 2-5. Register Pair Configuration
2-10
SPACES
Special-Purpose Working Registers Register used 4-bit accumulator double register 8-bit accumulator. carry flag also used 1-bit accumulator. 8-bit double registers used data pointers indirect addressing. When register serves data pointer, instructions LDI, LDD, XCHI, XCHD make very efficient working registers program loop counters letting transfer value register increment decrement using single instruction.
1-Bit Accumulator
4-Bit Accumulator
8-Bit Accumulator
Figure 2-6. 1-Bit, 4-Bit, 8-Bit Accumulator
Recommendation Multiple Interrupt Processing more than four interrupts being processed time, avoid possible loss working register data using PUSH instruction save register contents stack before service routines executed same register bank. When routines have executed successfully, restore register contents from stack working memory using instruction.
ADDRESS SPACES
PROGRAMMING Selecting Working Register Area
following examples show correct programming method selecting working register area: When "0": VENT2 INT0 1,0,INT0 PUSH PUSH PUSH PUSH PUSH INCS IRET EA,#00H 80H,EA HL,#40H WX,EA YZ,EA Jump INT0 address PUSH current SMB, Instruction does execute because PUSH register contents stack PUSH register contents stack PUSH register contents stack PUSH register contents stack
register contents from stack register contents from stack register contents from stack register contents from stack current SMB,
instructions execute alternately with PUSH instructions. instruction used interrupt service routine, PUSH instruction must used store restore current values, shown Example below. When "1": VENT2 INT0 1,1,INT0 PUSH INCS IRET EA,#00H 80H,EA HL,#40H WX,EA YZ,EA Jump INT0 address Store current SMB, Select register bank because
Restore SMB,
2-12
SPACES
STACK OPERATIONS
STACK POINTER (SP) stack pointer (SP) 8-bit register that stores address used access stack, area data memory aside temporary storage stack addresses. read written 8-bit control instructions. When addressing must always remain cleared logic zero. F80H F81H
There basic stack operations: writing stack (push), reading from stack (pop). push decrements increments that always points address last data written stack. program counter contents program status word stored stack area prior execution CALL PUSH instruction, during interrupt service routines. Stack operation LIFO (Last In-First Out) type. stack area located general-purpose data memory bank During interrupt subroutine, value saved stack area. When routine completed, stack pointer referenced restore PSW, next instruction executed. address stack registers bank (addresses 000H-0FFH) regardless current value enable memory bank (EMB) flag select memory bank (SMB) flag. Although general-purpose register areas used stack operations, careful avoid data loss simultaneous same register(s). Since reset value stack pointer defined firmware, recommend that initialize stack pointer program code location 00H. This sets first register stack area 0FFH. NOTE subroutine call occupies nibbles stack; interrupt requires six. When subroutine nesting interrupt routines used continuously, stack area should accordance with maximum number subroutine levels. this, estimate number nibbles that will used subroutines interrupts stack area correspondingly.
PROGRAMMING Initializing Stack Pointer
initialize stack pointer (SP): When "1": When "0": EA,#00H SP,EA Memory addressing area (00H-7FH, F80H-FFFH) EA,#00H SP,EA Select memory bank accumulator always cleared Stack area initial address (0FFH) (SP)
2-13
ADDRESS SPACES
PUSH OPERATIONS Three kinds push operations reference stack pointer (SP) write data from source register stack: PUSH instructions, CALL instructions, interrupts. each case, decreased number determined type push operation then points next available stack location. PUSH Instructions PUSH instruction references write 4-bit data nibbles stack. 4-bit stack addresses referenced stack pointer: upper register value another lower register. After PUSH executed, decreased points next available stack location. CALL Instructions When subroutine call issued, CALL instruction references write PC's contents 4-bit stack locations. Current values enable memory bank (EMB) flag enable register bank (ERB) flag also pushed stack. Since 4-bit stack locations used CALL, nest subroutine calls number levels permitted stack. Interrupt Routines interrupt routine references push contents program status word (PSW) stack. 4-bit stack locations used store this data. After interrupt executed, decreased points next available stack location. During interrupt sequence, subroutines nested number levels which permitted stack area.
PUSH (After PUSH,
SP-2) SP-6 SP-5 SP-4 SP-3
CALL (After CALL PC11-PC8
(note)
SP-6) SP-6
(note)
INTERRUPT (When acknowledged, SP-6) PC11-PC8
(note) (note)
PC13 PC12
SP-5 SP-4 SP-3 SP-2 SP-1
PC13 PC12
PC3-PC0 PC7-PC4
PC3-PC0 PC7-PC4
SP-2 SP-1
Lower Register Upper Register
SP-2 SP-1
NOTE:
KS57C5204/C5304 does PC12 PC13. KS57C5208/C5308 does PC13.
Figure 2-7. Push-Type Stack Operations
2-14
SPACES
OPERATIONS each push operation there corresponding operation write data from stack back source register registers: PUSH instruction instruction; CALL, instruction SRET; interrupts, instruction IRET. When operation occurs, incremented number determined type operation points next free stack location. Instructions instruction references write data stored 4-bit stack locations back register pairs register. value lower 4-bit register popped first, followed value upper 4-bit register. After executed, incremented points next free stack location. SRET Instructions subroutine call signaled return instruction, SRET. SRET uses reference 4-bit stack locations used CALL write this data back EMB, ERB. After SRET executed, incremented points next free stack location. IRET Instructions interrupt sequence signaled instruction IRET. IRET references locate 4bit stack addresses used interrupt write this data back PSW. After IRET executed, incremented points next free stack location.
SP+1 SP+2
SP+2) SP+1 SP+2 SP+3 SP+4 SP+5 SP+6
SRET SP+6) PC11-PC8
(note) (note)
SP+1 SP+2 SP+3 SP+4 SP+5 SP+6
IRET SP+6)
Lower Register Upper Register
PC11-PC8
(note) (note)
PC13 PC12
PC13 PC12
PC3-PC0 PC7-PC4
PC3-PC0 PC7-PC4
NOTE:
KS57C5204/C5304 does PC12 PC13. KS57C5208/C5308 does PC13.
Figure 2-8. Pop-Type Stack Operations
2-15
ADDRESS SPACES
SEQUENTIAL CARRIER (BSC)
sequential carrier (BSC) 16-bit general register that manipulated using 8-bit control instructions. RESET clears values logic zero. Using BSC, specify sequential addresses locations using 1-bit indirect addressing (memb.@L). (Bit addressing independent current value.) This way, programs process 16-bit data moving location sequentially then incrementing decreasing value register. data also manipulated using direct addressing. 8-bit manipulations, 4-bit register, BSC0 BSC2, must specified upper lower 8-bits manipulated, separately. values register BSC2.@L, address location assignment FC2H.0. register content BSC2.@L, address location assignment FC3H.3. Table 2-4. Register Organization Name BSC0 BSC1 BSC2 BSC3 Address FC0H FC1H FC2H FC3H BSC0.3 BSC1.3 BSC2.3 BSC3.3 BSC0.2 BSC1.2 BSC2.2 BSC3.2 BSC0.1 BSC1.1 BSC2.1 BSC3.1 BSC0.0 BSC1.0 BSC2.0 BSC3.0
PROGRAMMING Using Register Output 8-Bit Data
sequential carrier (BSC) register output 8-bit data (59H) P2.3 pin: BITS INCS EA,#59H BSC2,EA L,#8H C,BSC2.@L P2.3,C
BSC2 BSC3 P2.3
2-16
SPACES
PROGRAM COUNTER (PC)
13-bit program counter (PC) stores addresses instruction fetches during program execution. Whenever interrupt occurs, bits PC11 (KS57C5204/C5304) bits PC12 (KS57C5208/C5308) bits PC13 (KS57C5312) through vector address. Usually, incremented number bytes instruction being fetched. exception 1byte instruction which used reference instructions stored ROM.
PROGRAM STATUS WORD (PSW)
program status word (PSW) 8-bit word that defines system status program execution status which permits interrupted process resume operation after interrupt request been serviced. values mapped follows: FB0H FB1H
manipulated 1-bit 4-bit read/write 8-bit read instructions, depending specific bits being addressed. addressed during program execution regardless current value enable memory bank (EMB) flag. Part saved stack prior execution subroutine call hardware interrupt. After interrupt been processed, values popped from stack back address. When RESET generated, values according RESET vector address, carry flag left undefined current value retained). bits IS0, IS1, SC0, SC1, cleared logical zero. Table 2-5. Program Status Word Descriptions Identifier IS1, SC2, SC1, Description Interrupt status flags Enable memory bank flag Enable register bank flag Carry flag Program skip flags Addressing Read/Write
2-17
ADDRESS SPACES
INTERRUPT STATUS FLAGS (IS0, IS1) bits contain current interrupt execution status values. manipulate flags directly using 1-bit control instructions manipulating interrupt status flags conjunction with interrupt priority register (IPR), process multiple interrupts anticipating next interrupt execution sequence. interrupt priority control circuit determines settings order control multiple interrupt processing. When both interrupt status flags "0", interrupts allowed. priority with which interrupts processed then determined IPR. When interrupt occurs, pushed stack part automatically incremented next status. Then, when interrupt service routine ends with IRET instruction, values restored PSW. Table shows effects flag settings. Table 2-6. Interrupt Status Flag Settings Value Value Status Currently Executing Process Effect Settings Interrupt Request Control interrupt requests serviced Only high-priority interrupt determined interrupt priority register (IPR) serviced more interrupt requests serviced applicable; these settings undefined
Since interrupt status flags addressed write instructions, programs exert direct control over interrupt processing status. Before interrupt status flags addressed, however, must first execute instruction inhibit additional interrupt routines. When manipulation been completed, execute instruction re-enable interrupt processing.
PROGRAMMING Setting Flags Interrupt Processing
following instruction sequence shows flags control interrupt processing: INTB BITR BITS Disable interrupt Allow interrupts according priority level Enable interrupt
2-18
SPACES
FLAG (EMB) flag used enable whether memory bank selected register valid not. this way, controls addressing mode data memory banks When flag "0", data memory address space restricted bank addresses 000H-07FH memory bank regardless register contents. When flag "1", general-purpose areas bank accessed using appropriate value.
PROGRAMMING Using Flag Select Memory Banks
flag settings memory bank selection: When "0": When "1": A,#9H 90H,A 34H,A 90H,A 34H,A 20H,A 90H,A Select memory bank (190H) bank selected (134H) bank selected Select memory bank (090H) bank selected (034H) bank selected Select memory bank Program error, assembler does detect (F90H) bank selected A,#9H 90H,A 34H,A 90H,A 34H,A 20H,A 90H,A Non-essential instruction since (F90H) bank selected (034H) bank selected Non-essential instruction since (F90H) bank selected (034H) bank selected Non-essential instruction, since (020H) bank selected (F90H) bank selected
2-19
ADDRESS SPACES
FLAG (ERB) 1-bit register bank enable flag (ERB) determines range addressable working register area. When flag "1", working register area from register banks selected according register bank selection register (SRB). When flag "0", register bank selected working register area, regardless current value register bank selection register (SRB). When internal RESET generated, program memory address 0000H written flag. This automatically initializes flag. When vectored interrupt generated, respective address table program memory written flag, setting correct flag status before interrupt service routine executed. During interrupt routine, value automatically pushed stack area along with other bits. Afterwards, popped back FB0H.0 location PSW. initial flag settings each vectored interrupt defined using VENTn instructions.
PROGRAMMING Using Flag Select Register Banks
flag settings register bank selection: When "0": When "1": EA,#34H HL,EA YZ,EA WX,EA Register bank selected Bank #34H Bank Bank Register bank selected Bank BANK2 Register bank selected Bank Bank EA,#34H HL,EA YZ,EA WX,EA Register bank selected (since "0", configured bank Bank #34H Bank Register bank selected Bank Register bank selected Bank
2-20
SPACES
SKIP CONDITION FLAGS (SC2, SC1, SC0) skip condition flags SC2, SC1, indicate current program skip conditions reset automatically during program execution. Skip condition flags only addressed 8-bit read instructions. Direct manipulation SC2, SC1, bits allowed. CARRY FLAG carry flag used save result overflow borrow when executing arithmetic instructions involving carry (ADC, SBC). carry flag also used 1-bit accumulator performing Boolean operations involving bit-addressed data memory. overflow borrow condition occurs when executing arithmetic instructions with carry (ADC, SBC), carry flag "1". Otherwise, value "0". When RESET occurs, current value carry flag retained during power-down mode, when normal operating mode resumes, value undefined. carry flag directly manipulated predefined 1-bit read/write instructions, independent other bits PSW. Only instructions, instructions listed Table 2-7, affect carry flag. Table 2-7. Valid Carry Flag Manipulation Instructions Operation Type Direct manipulation BTST transfer (operand)
(1),C
Instructions
Carry Flag Manipulation carry flag Clear carry flag (reset carry flag) Invert carry flag value (complement carry flag) Test carry skip Load carry flag value specified Load contents specified carry flag Rotate Right through carry flag
C,(operand) Data transfer Boolean manipulation
BAND C,(operand)
specified with contents carry flag save result carry flag specified with contents carry flag save result carry flag specified with contents carry flag save result carry flag Save carry flag stack with other bits Restore carry flag from stack with other bits
C,(operand) BXOR C,(operand) Interrupt routine Return from interrupt INTn IRET
NOTES: operand three addressing formats: mema.a, memb.@L, DA.b. 'INTn' refers specific interrupt being executed instruction.
ADDRESS SPACES
PROGRAMMING Using Carry Flag 1-Bit Accumulator
carry flag logic one: #0C3H #0AAH #0C3H #0AAH #1H,
EA,#0C3H HL,#0AAH EA,HL
Logical-AND address with P3.3 output result P5.0: BAND H,#3H C,@H+0FH.3 C,P3.3 P5.0,C upper four bits address register value P3.3 Output result from carry flag P5.0
2-22
MODES
ADDRESSING MODES
enable memory bank flag, EMB, controls addressing modes data memory. When flag logic one, address entire area; when flag cleared logic zero, addressable area restricted specific locations. flag works connection with select memory bank instruction, SMBn. will recall that SMBn instruction used select bank setting always contained upper four bits 12-bit address. this reason, both addressing modes (EMB "1") apply specifically memory bank indicated instruction, restrictions addressable area within banks Direct indirect 1-bit, 4-bit, 8-bit addressing methods used. Several locations addressable times, regardless current flag setting. Here guidelines keep mind regarding data memory addressing: When address peripheral hardware locations bank mnemonic memory-mapped hardware component used operand place actual address location. Always even-numbered address operand 8-bit direct indirect addressing. With direct addressing, address instruction operand; with indirect addressing, instruction specifies register which contains operand's address.
ADDRESSING MODES
Areas 000H 01FH 020H 07FH 080H
Addressing Mode
DA.b
@H+DA.b
mema.b
memb.@L
Working Registers
Bank (General Registers Stack)
0FFH 100H
Bank (General Registers)
1FFH 200H
Bank (General Registers)
2FFH F80H Bank (Peripheral Hardware Registers) FB0H FBFH FC0H FF0H
FFFH
NOTES: means don't care. Blank columns indicate areas that addressable, given addressing method enable memory bank (EMB) flag setting shown column headers.
Figure 3-1. Address Structure
MODES
INITIALIZATION VALUES flag bits automatically values RESET vector address interrupt vector address. When RESET generated internally, program memory address 0000H written flag, initializing automatically. When vectored interrupt generated, respective vector address table written EMB. This automatically sets flag status interrupt service routine. When interrupt serviced, value automatically saved stack then restored when interrupt routine completed. beginning program, initial flag values each vectored interrupt must using VENT instruction. reset manipulation instructions (BITS, BITR) despite current setting.
PROGRAMMING Initializing Flags
following assembly instructions show initialize flag settings: VENT0 VENT1 VENT2 VENT3 VENT5 VENT6
0000H 1,0,RESET 0,1,INTB 0,1,INT0 0,1,INT1(note)
address assignment branch RESET branch INTB branch INT0 branch
0,1,INTT0 0,1,INTT
branch INTT0 branch INTT
RESET
BITR
NOTE: KS57C5304/C5308/C5312 does INT1 interrupt.
ADDRESSING MODES
ENABLE MEMORY BANK SETTINGS When enable memory bank flag logic one, address data memory bank specified select memory bank (SMB) value using 8-bit instructions. both direct indirect addressing modes. addressable areas when follows: When enable memory bank flag logic zero, addressable area defined independently value, restricted specific locations depending whether direct indirect address mode used. "0", addressable area restricted locations 000H-07FH bank locations F80H-FFFH bank direct addressing. indirect addressing, only locations 000H-0FFH bank addressable, regardless value. address peripheral hardware register (bank using indirect addressing, flag must first value "15". When RESET occurs, flag value contained address 0000H. EMB-Independent Addressing time, several areas data memory addressed independently current status flag. These exceptions described Table 3-1. 000H-0FFH 100H-1FFH 200H-2FFH F80H-FFFH
Table 3-1. Addressing Affected Value Address 000H-0FFH Addressing Method 4-bit indirect addressing using register pairs; 8-bit indirect addressing using 1-bit direct addressing 1-bit indirect addressing using register Affected Hardware applicable PUSH PSW, IEx, IRQx, BITS BITR Program Examples A,@WX
FB0H-FBFH FF0H-FFFH FC0H-FFFH
BAND C,P3.@L
MODES
SELECT BANK REGISTER (SB) select bank register (SB) used assign memory bank register bank. 8-bit register consists 4-bit select register bank register (SRB) 4-bit select memory bank register (SMB), shown Figure 3-2. During interrupts subroutine calls, register contents saved stack 8-bit units PUSH instruction. later restore value using instruction.
Register
Figure 3-2. Values Register Select Register Bank (SRB) Instruction select register bank (SRB) value specifies which register bank used working register bank. value 'SRB instruction, where four register banks selected combination flag status value that using 'SRB instruction. current value retained until another register requested program software. PUSH instructions used save restore contents during interrupts subroutine calls. RESET clears 4-bit value logic zero. Select Memory Bank (SMB) Instruction select four available data memory banks, must execute instruction specifying number memory bank want 15). example, instruction 'SMB selects bank 'SMB selects bank (And remember enable selected memory bank making appropriate flag setting. upper four bits 12-bit data memory address stored register. value specified software RESET does occur) current value retained. RESET clears 4-bit value logic zero. PUSH instructions save restore contents register from stack area during interrupts subroutine calls.
ADDRESSING MODES
DIRECT INDIRECT ADDRESSING 1-bit, 4-bit, 8-bit data stored data memory locations addressed directly using specific register address instruction operand. Indirect addressing specifies memory location that contains required direct address. KS57 instruction supports 1-bit, 4-bit, 8-bit indirect addressing. 8-bit indirect addressing, even-numbered address must always used instruction operand. 1-BIT ADDRESSING Table 3-2. 1-Bit Direct Indirect Addressing Operand Notation DA.b Addressing Mode Description Direct: indicated address (DA), memory bank selection, specified number (b). Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 1-bit addressable peripherals (SMB IS0, IS1, EMB, ERB, IEx, IRQx, Pn.m BSCn.x Pn.m
mema.b Direct: indicated addressable area (mema) number (b). Indirect: lower bits register indicated upper bits area (memb) upper bits register Indirect: indicated lower four bits address (DA), memory bank selection, register identifier.
NOTE: applicable.
000H-FFFH FB0H-FBFH FF0H-FFFH
Bank
memb.@L
FC0H-FFFH
Bank
DA.b
000H-0FFH 000H-FFFH
Bank
1-bit addressable peripherals (SMB
MODES
PROGRAMMING 1-Bit Addressing Modes
1-Bit Direct Addressing "0": AFLAG BFLAG CFLAG BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 AFLAG BFLAG CFLAG BFLAG P3.0
34H.3 F85H.3 (BMOD.3) FBAH.0 (IRQW) skip Else FBAH.0 (IRQW) F85H.3 (BMOD.3) FF3H.0 (P3.0)
"1": AFLAG BFLAG CFLAG BITS BITS BTST BITS BITS 34H.3 85H.3 0BAH.0 AFLAG BFLAG CFLAG BFLAG P3.0
34H.3 85H.3 0BAH.0 skip Else 0BAH.0 085H.3 FF3H.0 (P3.0)
1-Bit Indirect Addressing "0": AFLAG BFLAG CFLAG BTSTZ BITS 34H.3 85H.3 0BAH.0 H,#0BH @H+CFLAG CFLAG
#0BH 0BAH.0 0BAH.0 skip Else 0BAH.0 FBAH.0 (IRQW)
"1": AFLAG BFLAG CFLAG BTSTZ BITS 34H.3 85H.3 0BAH.0 H,#0BH @H+CFLAG CFLAG
#0BH 0BAH.0 0BAH.0 skip Else 0BAH.0 0BAH.0
ADDRESSING MODES
4-BIT ADDRESSING Table 3-3. 4-Bit Direct Indirect Addressing Operand Notation Addressing Mode Description Direct: 4-bit address indicated address (DA) memory bank selection Indirect: 4-bit address indicated memory bank selection register Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 4-bit addressable peripherals (SMB
000H-FFFH 000H-0FFH
Bank
000H-FFFH
4-bit addressable peripherals (SMB
Indirect: 4-bit address indicated register Indirect: 4-bit address indicated register
000H-0FFH 000H-0FFH
Bank Bank
NOTE: applicable.
PROGRAMMING 4-Bit Addressing Modes
4-Bit Direct Addressing "0": ADATA BDATA A,P3 ADATA,A BDATA,A
Non-essential instruction, since (P3) Non-essential instruction, since (046H) (F8EH)
"1": ADATA BDATA A,P3 ADATA,A BDATA,A
(P3) (046H) (08EH)
MODES
PROGRAMMING 4-Bit Addressing Modes (Continued)
4-Bit Indirect Addressing (Example "0", compare bank locations 040H-046H with bank locations 060H-066H: ADATA BDATA CPSE SRET DECS HL,#BDATA WX,#ADATA A,@WL A,@HL COMP
Non-essential instruction, since bank (040H-046H) bank (060H-066H) skip
COMP
"1", compare bank locations 040H-046H bank locations 160H-166H: ADATA BDATA CPSE SRET DECS HL,#BDATA WX,#ADATA A,@WL A,@HL COMP
COMP
bank (040H-046H) bank (160H-166H) skip
ADDRESSING MODES
PROGRAMMING 4-Bit Addressing Modes (Concluded)
4-Bit Indirect Addressing (Example "0", exchange bank locations 040H-046H with bank locations 060H-066H: ADATA BDATA XCHD HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
Non-essential instruction, since bank (040H-046MH) Bank (060H-066H)
TRANS
"1", exchange bank locations 040H-046H bank locations 160H-166H: ADATA BDATA XCHD HL,#BDATA WX,#ADATA A,@WL A,@HL TRANS
TRANS
bank (040H-046H) Bank (160H-166H)
3-10
MODES
8-BIT ADDRESSING Table 3-4. 8-Bit Direct Indirect Addressing Instruction Notation Addressing Mode Description Direct: 8-bit address indicated address even number) memory bank selection Indirect: 8-bit address indicated memory bank selection register (the 4-bit register value must even number) Flag Setting Addressable Area 000H-07FH F80H-FFFH Memory Bank Bank Bank Hardware Mapping 8-bit addressable peripherals (SMB
000H-FFFH 000H-0FFH
Bank
000H-FFFH
8-bit addressable peripherals (SMB
ADDRESSING MODES
PROGRAMMING 8-Bit Addressing Modes
8-Bit Direct Addressing "0": ADATA BDATA EA,P4 ADATA,EA BDATA,EA
Non-essential instruction, since (P5), (P4) (046H) (047H) (F8EH) (F8FH)
"1": ADATA BDATA EA,P4 ADATA,EA BDATA,EA
(P5), (P4) (046H) (047H) (08EH) (08FH)
8-Bit Indirect Addressing "0": ADATA 146H HL,#ADATA EA,@HL Non-essential instruction, since (046H), (047H)
"1": ADATA 146H HL,#ADATA EA,@HL
(146H), (147H)
3-12
MEMORY
support program control peripheral hardware, addresses peripherals memory-mapped bank RAM. Memory mapping lets mnemonic operand instruction place specific memory location. Access bank controlled select memory bank (SMB) instruction enable memory bank flag (EMB) setting. flag "0", bank addressed using direct addressing, regardless current value. 1-bit direct indirect addressing used specific locations bank regardless current value.
HARDWARE REGISTERS
Table contains detailed information about mapping peripheral hardware bank (register locations F80H-FFFH). quick-reference source when writing application programs. gives following information: Register address Register name (mnemonic program addressing) values (both addressable non-manipulable) Read-only, write-only, read write addressability 1-bit, 4-bit, 8-bit data manipulation characteristics
MEMORY
Table 4-1. Memory Bank Memory Bank Address F80H F81H F85H F86H F87H F88H F89H F90H F91H F92H F93H F94H F95H F96H F97H F98H F99H F9AH FA0H FA1H FA4H FA5H Locations FA6H-FA7H mapped. FA8H FA9H Locations FAAH-FAFH mapped. FB0H FB1H FB2H
Addressing Mode 1-Bit 4-Bit 8-Bit
Register
Locations F82H-F84H mapped. BMOD BCNT WMOD TMOD0 TOE1 TCNT0 TREF0 WDMOD WDFLAG TMOD1 WDTCF TCNT1 TOE0 TOL1 TOL0
Locations F8AH-F8FH mapped.
Locations F9BH-F9FH mapped.
Locations FA2H-FA3H mapped.
TREF
Table 4-1. Memory Bank (Continued) FB3H FB4H FB5H FB6H FB8H FBAH FBBH FBCH FBEH FBFH FC0H FC1H FC2H FC3H FD0H FD2H FD3H FDAH FDBH FDCH FDDH FDEH PUMOD2 PUMOD1 PNE1 BSC0 BSC1 BSC2 BSC3 Locations FC4H-FCFH mapped. CLMOD DTMR PNE4.3 PNE5.3 PUR1.3 PUR5 PUR9 PM2.3 PM3.3 PMG2 PMG3
PCON IMOD0 IMOD1 IMOD2
IRQ4 IRQ1
IET1 IET0
IRQB IRQW IRQT1 IRQT0 IRQ0 IRQ2
Locations FB7H mapped. Locations FB9H mapped.
Locations FBDH mapped.
PNE4.2 PNE5.2 PUR1.2 PUR4 PUR8 PM2.2 PM3.2
PNE4.1 PNE5.1 PUR1.1 PUR3 PUR7
PNE4.0 PNE5.0 PUR1.0 PUR2 PUR6
Locations FD1H mapped.
Locations FD4H-FD9H mapped.
Locations FDFH-FE7H mapped. FE8H FE9H FEAH FEBH FECH FEDH PMG1 PM2.1 PM3.1 PM4.1 PM5.1 PM6.1 PM7.1 PM2.0 PM3.0 PM4.0 PM5.0 PM6.0 PM7.0
PM4.3 PM5.3 PM6.3 PM7.3
PM4.2 PM5.2 PM6.2 PM7.2
MEMORY
Table 4-1. Memory Bank (Continued) FEEH FEFH PMG4 PM8.3
PM8.2 PM9.2
PM8.1 PM9.1
PM8.0 PM9.0
Locations FF0H mapped. FF1H FF2H FF3H FF4H FF5H FF6H FF7H FF8H FF9H Port Port Port Port Port Port Port Port Port
NOTES WMOD register must logic carry flag read written specific manipulation instructions only. KS57C5304/C5308/C5312 does INT1 INT4 interrupts. KS57C5304/C5308/C5312 does PMG4, P1.1-P1.3, P3.2-P3.3,
REGISTER DESCRIPTIONS
this section, register descriptions presented consistent format familiarize with memorymapped locations bank RAM. Figure describes features register description format. Register descriptions arranged alphabetical order. Programmers this section quick-reference source when writing application programs. Counter registers, buffer registers, reference registers, well stack pointer port latches, included these descriptions. More detailed information about these registers used included Part this manual, "Hardware Descriptions," context corresponding peripheral hardware module descriptions.
Register used addressing Register
Name individual related Register name Associated hardware module Register location bank
CLMOD Clock Output Control Register
Identifier RESET Value Read/Write Addressing
CLMOD.3
FB2H
Enable/Disable Clock Output Control Disable interrupt processing globally Enable interrupt processing globally
CLMOD.2
Always logic zero
CLMOD.1-.0
Clock Source Frequency Selection Control Bits Select clock source Select system clock fxx/8 (524kHz 4.19 MHz) Operation generates negative number (MSB "1") Operation generates negative number (MSB "1")
Read-only Write-only Read/write Type addressing that must used address (1-bit, 4-bit, 8-bit)
Description effect specific settings
identifier used addressing number order
value immediately following RESET
Figure 4-1. Register Description Format
MEMORY
BMOD
Identifier
RESET
Basic Timer Mode Register
F85H
Value
Read/Write Addressing BMOD.3
Basic Timer Restart Restart basic timer, then clear IRQB flag, BCNT BMOD.3 logic zero
BMOD.2-.0
Input Clock Frequency Signal Stabilization Interval Control Bits Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: Input clock frequency: Signal stabilization interval: fx/212 (1.02 kHz) 220/fx (250 fx/29 (8.18 kHz) 217/fx (31.3 fx/27 (32.7 kHz) 215/fx (7.82 fx/25 (131 kHz) 213/fx (1.95
NOTES: Signal stabilization interval time required stabilize clock signal oscillation after stop mode terminated interrupt. stabilization interval also interpreted "Interrupt Interval Time". When RESET occurs, oscillation stabilization time 31.3 (217/fx) 4.19 MHz. `fx' system clock rate, given clock frequency 4.19 MHz.
CLMOD
Identifier
RESET
Clock Output Mode Register
FD0H
Value
Read/Write Addressing CLMOD.3
Enable/Disable Clock Output Control Disable clock output Enable clock output
CLMOD.2
Always logic zero
CLMOD.1-.0
Clock Source Frequency Selection Control Bits Select clock source fx/4, fx/8 fx/64 (1.05 MHz, 65.5 kHz) Select system clock fx/8 (524 kHz) Select system clock fx/16 (262 kHz) Select system clock fx/64 (65.5kHz)
NOTE: `fx' system clock, given clock frequency 4.19 MHz.
MEMORY
DTMR
Identifier
RESET
DTMF Mode Register
DTMF
FD3H, FD2H
Value
Read/Write Addressing DTMR.7-.4
DTMR Values Keyboard Inputs Function
Function Function Function
DTMR.3
Always logic zero
DTMR.2-.
Tone Selection Bits Dual-tone enable Dual-tone enable (alternate setting) Single-column tone enable Single-low tone enable
DTMR.0
DTMF Operation Enable/Disable Disable DTMF operation Enable DTMF operation
IMOD0
Identifier
RESET
External Interrupt (INT0) Mode Register
Bits Always logic zero
FB4H
Value
Read/Write Addressing IMOD0.3-.2
IMOD0.1-.0
External Interrupt Mode Control Bits Interrupt requests triggered rising signal edge Interrupt requests triggered falling signal edge Interrupt requests triggered both rising falling signal edges Interrupt request flag (IRQx) cannot logic
MEMORY
IMOD1-
Identifier
RESET
External Interrupt (INT1) Mode Register (note)
Bits Always logic zero
FB5H
Value
Read/Write Addressing IMOD1.3-.
IMOD1.0
External Interrupt Edge Detection Control Rising edge detection Falling edge detection
NOTE: KS57C5304/C5308/C5312 does IMOD1.
4-10
IMOD2
Identifier
RESET
External Interrupt (INT2) Mode Register
Bits Always logic zero
FB6H
Value
Read/Write Addressing IMOD2.3-.2
IMOD2.1-.0
External Interrupt Edge Detection Selection Interrupt request INT2 triggered rising edge (KS57C5204/C5208 only) Interrupt request KS4-KS7 triggered falling edge Interrupt request KS2-KS7 triggered falling edge Interrupt request KS0-KS7 triggered falling edge
MEMORY
IE0, IRQ0,
Identifier
RESET
INT0, Interrupt Enable/Request Flags
IRQ1
(note)
FBEH
IRQ0
(note)
Value
Read/Write Addressing (note)
INT1 Interrupt Enable Flag Disable interrupt requests INT1 Enable interrupt requests INT1
IRQ1 (note)
INT1 Interrupt Request Flag Generate INT1 interrupt (This cleared hardware when rising falling edge detected INT1 pin.)
INT0 Interrupt Enable Flag Disable interrupt requests INT0 Enable interrupt requests INT0
IRQ0
INT0 Interrupt Request Flag Generate INT0 interrupt (This cleared automatically hardware when rising falling edge detected INT0 pin.)
NOTE: KS57C5304/C5308/C5312 does IE1, IRQ1, INT1 pin.
4-12
IE2, IRQ2
Identifier
RESET
INT2 Interrupt Enable/Request Flags
Bits Always logic zero IRQ2
FBFH
Value
Read/Write Addressing .3-.2
INT2 Interrupt Enable Flag Disable INT2 interrupt requests INT2 (note) KS0-KS7 pins Enable INT2 interrupt requests INT2 (note) KS0-KS7 pins
IRQ2
INT2 Interrupt Request Flag Generate INT2 quasi-interrupt (This cleared automatically hardware when rising edge detected INT2 (note) when falling edge detected KS0-KS7 pins. Since INT2 quasi-interrupt, IRQ2 flag must cleared software.)
NOTE: KS57C5304/C5308/C5312 does INT2 pin.
4-13
MEMORY
IE4, IRQ4 INT4 Interrupt Enable/Request Flags (note) IEB, IRQB INTB Interrupt Enable/Request Flags
Identifier
RESET
FB8H FB8H
(note)
IRQ4
(note)
IRQB
Value
Read/Write Addressing (note)
INT4 Interrupt Enable Flag Disable interrupt requests INT4 Enable interrupt requests INT4
IRQ4 (note)
INT4 Interrupt Request Flag Generate INT4 interrupt (This cleared automatically hardware when rising falling signal edge detected INT4 pin.)
INTB Interrupt Enable Flag Disable INTB interrupt requests Enable INTB interrupt requests
IRQB
INTB Interrupt Request Flag Generate INTB interrupt (This cleared automatically hardware when reference interval signal received from basic timer.)
NOTE: KS57C5304/C5308/C5312 does IE4, IRQ4, INT4 pin.
4-14
IET0, IRQT0
Identifier
RESET
INTT0 Interrupt Enable/Request Flags
Bits Always logic zero IET0 IRQT0
FBCH
Value
Read/Write Addressing .3-.2
IET0
INTT0 Interrupt Enable Flag Disable INTT0 interrupt requests Enable INTT0 interrupt requests
IRQT0
INTT0 Interrupt Request Flag Generate INTT0 interrupt (This cleared automatically hardware when contents TCNT0 TREF0 registers match.)
4-15
MEMORY
IET1, IRQT1
Identifier
RESET
INTT1 Interrupt Enable/Request Flags
Bits Always logic IET1 IRQT1
FBBH
Value
Read/Write Addressing .2-.3
INTT1 Interrupt Enable Flag Disable INTT1 interrupt requests Enable INTT1 interrupt requests
IRQT
INTT1 Interrupt Request Flag Generate INTT1 interrupt (This cleared automatically hardware when contents TCNT1 TREF1 registers match.)
4-16
IEW, IRQW
Identifier
RESET
Intw Interrupt Enable/Request Flags
Bits Always logic zero IRQW
FBAH
Value
Read/Write Addressing .3-.2
INTW Interrupt Enable Flag Disable INTW interrupt requests Enable INTW interrupt requests
IRQW
INTW Interrupt Request Flag Generate INTW interrupt (This when timer interval seconds 3.19 milliseconds watch timer frequency 32.768 kHz.)
NOTE: Since INTW quasi-interrupt, IRQW flag must cleared software.
4-17
MEMORY
Identifier
RESET
Interrupt Priority Register
FB2H
Value
Read/Write Addressing
Interrupt Master Enable (MSB) Disable interrupt processing Enable processing interrupt service requests
IPR.2-.0
Interrupt Priority Assignment Bits Normal interrupt processing according default priority settings Process INTB INT4 (note) interrupts highest priority Process INT0 interrupts highest priority Process INT1 (note) interrupts highest priority Process INTT0 interrupts highest priority Process INTT1 interrupts highest priority
NOTES: KS57C5304/C5308/C5312 does INT1 INT4 interrupts. During normal interrupt processing, interrupts processed order which they occur. more interrupts occur simultaneously, processing order determined default interrupt priority settings shown below. Using settings, select specific interrupts high-priority processing event contention. When high-priority (IPR) interrupt been processed, waiting interrupts handled according their default priorities. default priorities follows (`1' highest priority; lowest priority): INTB, INT4 INT0 INT1 INTT0 INTT1
4-18
PCON
Identifier
RESET
Power Control Register
FB3H
Value
Read/Write Addressing PCON.3-.2
Operating Mode Control Bits Enable normal operating mode Initiate idle power-down mode Initiate stop power-down mode
PCON.1-.0
Clock Frequency Selection Bits Select fx/64 Select fx/8 Select fx/4
NOTE: `fx' system clock.
4-19
MEMORY
Identifier
RESET
Program Status Word
FB1H, FB0H
Value
Read/Write Addressing
Carry Flag overflow borrow condition exists overflow borrow condition does exist
SC2-SC0
Skip Condition Flags skip condition exists; direct manipulation these bits allowed skip condition exists; direct manipulation these bits allowed
IS1,
Interrupt Status Flags Service interrupt requests Service only high-priority interrupt(s) determined interrupt priority register (IPR) service more interrupt requests Undefined
Enable Data Memory Bank Flag Restrict program access data memory bank (F80H-FFFH) locations 000H-07FH bank only Enable full access data memory banks
Enable Register Bank Flag Select register bank working register area Select register banks working register area accordance with select register bank (SRB) instruction operand
NOTES: value carry flag after RESET occurs during normal operation undefined. RESET occurs during power-down mode (IDLE STOP), current value carry flag retained. carry flag only addressed specific 1-bit manipulation instructions. Section detailed information.
4-20
PMG1
Identifier
RESET
Port Mode Flags (Group Ports
PM3.3
(note)
PM2.3 PM2.2
FE9H, FE8H
PM2.1 PM2.0
PM3.2
(note)
PM3.1
PM3.0
Value
Read/Write Addressing PM3.3 (note)
P3.3 Mode Selection Flag P3.3 input mode P3.3 output mode
PM3.2 (note)
P3.2 Mode Selection Flag P3.2 input mode P3.2 output mode
PM3.
P3.1 Mode Selection Flag P3.1 input mode P3.1 output mode
PM3.0
P3.0 Mode Selection Flag P3.0 input mode P3.0 output mode
PM2.3
P2.3 Mode Selection Flag P2.3 input mode P2.3 output mode
PM2.2
P2.2 Mode Selection Flag P2.2 input mode P2.2 output mode
PM2.
P0.1 Mode Selection Flag P2.1 input mode P2.1 output mode
PM2.0
P2.0 Mode Selection Flag P2.0 input mode P2.0 output mode
NOTE: KS57C5304/C5308/C5312 does PM3.2-PM3.3.
MEMORY
PMG2
Identifier
RESET
Port Mode Flags (Group Ports
PM5.3 PM5.2 PM5.1 PM5.0 PM4.3
PM4.2
FEBH, FEAH
PM4.1 PM4.0
Value
Read/Write Addressing PM5.3
P5.3 Mode Selection Flag P5.3 input mode P5.3 output mode
PM5.2
P5.2 Mode Selection Flag P5.2 input mode P5.2 output mode
PM5.
P5.1 Mode Selection Flag P5.1 input mode P5.1 output mode
PM5.0
P5.0 Mode Selection Flag P5.0 input mode P5.0 output mode
PM4.3
P4.3 Mode Selection Flag P4.3 input mode P4.3 output mode
PM4.2
P4.2 Mode Selection Flag P4.2 input mode P4.2 output mode
PM4.
P4.1 Mode Selection Flag P4.1 input mode P4.1 output mode
PM4.0
P4.0 Mode Selection Flag P4.0 input mode P4.0 output mode
4-22
PMG3
FECH
Identifier
RESET
Port Mode Flags (Group Ports
FEDH,
PM7.3 Value
PM7.2
PM7.1
PM7.0
PM6.3
PM6.2
PM6.1
PM6.0
Read/Write Addressing PM7.3
P7.3 Mode Selection Flag P7.3 input mode P7.3 output mode
PM7.2
P7.2 Mode Selection Flag P7.2 input mode P7.2 output mode
PM7.
P7.1 Mode Selection Flag P7.1 input mode P7.1 output mode
PM7.0
P7.0 Mode Selection Flag P7.0 input mode P7.0 output mode
PM6.3
P6.3 Mode Selection Flag P6.3 input mode P6.3 output mode
PM6.2
P6.2 Mode Selection Flag P6.2 input mode P6.2 output mode
PM6.
P6.1 Mode Selection Flag P6.1 input mode P6.1 output mode
PM6.0
P6.0 Mode Selection Flag P6.0 input mode P6.0 output mode
4-23
MEMORY
PMG4
Identifier
RESET
Port Mode Flags (Group Ports (note)
Always logic zero PM9.2 PM9.1 PM9.0 PM8.3
PM8.2
FEFH, FEEH
PM8.1 PM8.0
Value
Read/Write Addressing
PM9.2
P9.2 Mode Selection Flag P9.2 input mode P9.2 output mode
PM9.
P9.1 Mode Selection Flag P9.1 input mode P9.1 output mode
PM9.0
P9.0 Mode Selection Flag input mode output mode
PM8.3
P8.3 Mode Selection Flag P8.3 input mode P8.3 output mode
PM8.2
P8.2 Mode Selection Flag P8.2 input mode P8.2 output mode
PM8.
P8.1 Mode Selection Flag P8.1 input mode P8.1 output mode
PM8.0
P8.0 Mode Selection Flag P8.0 input mode P8.0 output mode
NOTE: KS57C5304/C5308/C5312 does PMG4.
4-24
Identifier
RESET
Port Open-Drain Enable Register
PNE5.3 PNE5.2 PNE5.1 PNE5.0 PNE4.3
FDBH, FDAH
PNE4.1 PNE4.0
PNE4.2
Value
Read/Write Addressing PNE5.3
P5.3 Output mode Control Push-pull output N-channel open-drain output
PNE5.2
P5.2 Output mode Control Push-pull output N-channel open-drain output
PNE5.
P5.1 Output mode Control Push-pull output N-channel open-drain output
PNE5.0
P5.0 Output mode Control Push-pull output N-channel open-drain output
PNE4.3
P4.3 Output mode Control Push-pull output N-channel open-drain output
PNE4.2
P4.2 Output mode Control Push-pull output N-channel open-drain output
PNE4.
P4.1 Output mode Control Push-pull output N-channel open-drain output
PNE4.0
P4.0 Output mode Control Push-pull output N-channel open-drain output
4-25
MEMORY
PUMOD1
Identifier
RESET
Pull-Up Resistor Mode Register PUR5 PUR4 PUR3 PUR2 PUR1.3
(note)
PUR1.2
(note)
FDDH, FDCH
PUR1.(note)
PUR1.0
Value
Read/Write Addressing PUR5
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR4
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR3
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR2
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR1.3 (note)
Connect/Disconnect P1.3 Pull-Up Resistor Control Disconnect P1.3 pull-up resistor Connect P1.3 pull-up resistor
PUR1.2 (note)
Connect/Disconnect P1.2 Pull-Up Resistor Control Disconnect P1.2 pull-up resistor Connect P1.2 pull-up resistor
PUR1.1 (note)
Connect/Disconnect P1.1 Pull-Up Resistor Control Disconnect P1.1 pull-up resistor Connect P1.1 pull-up resistor
PUR1.0
Connect/Disconnect P1.0 Pull-Up Resistor Control Disconnect P1.0 pull-up resistor Connect P1.0 pull-up resistor
NOTE: KS57C5304/C5308/C5312 does PUR1.1-PUR1.3.
4-26
PUMOD2
Identifier
RESET
PULL-UP RESISTOR MODE REGISTER
PUR9
(note)
FDEH
PUR8
(note)
PUR7
PUR6
Value
Read/Write Addressing PUR9 (note)
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR8 (note)
Connect/Disconnect Port Pull-Down Resistor Control Disconnect port pull-down resistor Connect port pull-down resistor
PUR7
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
PUR6
Connect/Disconnect Port Pull-Up Resistor Control Disconnect port pull-up resistor Connect port pull-up resistor
NOTE: KS57C5304/C5308/C5312 does PUR8 PUR9.
4-27
MEMORY
TMOD0
Identifier
RESET
Timer/Counter Mode Register
Always logic zero
T/C0
F91H, F90H
Value
Read/Write Addressing TMOD0.7
TMOD0.6-.4 TMOD0.3
Timer/Counter Input Clock Selection Bits External clock input TCL0 rising edge External clock input TCL0 falling edge Internal system clock fx/210 (4.09 kHz) Select clock: fx/26 (65.5 kHz) Select clock: fx/24 (262 kHz) Select clock: (4.19 MHz)
Clear Counter Resume Counting Control Clears TCNT0 IRQT0. TOL0 remained resume counting immediately (This cleared automatically when counting starts.)
TMOD0.2
Enable/Disable Timer/Counter Disable timer/counter retain TCNT0 contents Enable timer/counter
TMOD0.
Always logic zero
TMOD0.0
Always logic zero
4-28
TMOD1
Identifier
RESET
Timer/Counter Mode Register
Always logic zero
T/C2
FA1H, FA0H
Value
Read/Write Addressing TMOD1.7
TMOD1.6
Timer/Counter Input Clock Selection Bits External clock input TCL1 rising edge External clock input TCL1 falling edge Internal system clock fx/212 (1.02 kHz) Select clock: fx/210 (4.09 kHz) Select clock: fx/28 (16.4 kHz) Select clock: fx/26 (65.5 kHz)
TMOD1.3
Clear Counter Resume Counting Control Clears TCNT1 IRQT1. TOL1 remained resume counting immediately (This cleared automatically when counting starts.)
TMOD1.2
Enable/Disable Timer/Counter Disable timer/counter retain TCNT1 contents Enable timer/counter
TMOD1.
Always logic zero
TMOD1.0
Always logic zero
4-29
MEMORY
Identifier
RESET
Timer Output Enable Flag Register
TOE1 TOE0
F92H
Value
Read/Write Addressing
Timer/Counter Output Enable Flag Disable timer/counter output TCLO1 Enable timer/counter output TCLO1
TOE0
Timer/Counter Output Enable Flag Disable timer/counter output TCLO0 Enable timer/counter output TCLO0
Basic Timer Output Enable Flag Disable basic timer output BTCO Enable basic timer output BTCO
Always logic zero
4-30
WDMOD
Identifier
RESET
Watchdog Timer Mode Register
F99H, F98H
Value
Read/Write Addressing WDMOD
Watchdog Timer Enable/Disable Control other value Disable watchdog timer function Enable watchdog timer function
MEMORY
WDFLAG
Identifier
RESET
Watchdog Timer Counter Clear Flag Register F9AH
WDTCF
Value
Read/Write Addressing WDTCF
Watchdog Timer Counter Clear Flag Clears watchdog timer counter
.2-.0
Bits Always logic zero
NOTE: After watchdog timer cleared writing "1", this cleared automatically.
4-32
WMOD
Identifier
RESET
Watch Timer Mode Register
F89H, F88H
Value
Read/Write Addressing WMOD.7
Enable/Disable Buzzer Output Disable buzzer (BUZ) signal output Enable buzzer (BUZ) signal output
WMOD.6
Always logic zero
WMOD.5-.4
Output Buzzer Frequency Selection Bits fw/16 buzzer (BUZ) signal output kHz) fw/8 buzzer (BUZ) signal output kHz) fw/4 buzzer (BUZ) signal output kHz) fw/2 buzzer (BUZ) signal output kHz)
WMOD.3
Always logic zero
WMOD.2
Enable/Disable Watch Timer Disable watch timer clear frequency dividing circuits Enable watch timer
WMOD.
Watch Timer Speed Control Normal speed; IRQW seconds High-speed operation; IRQW 3.91
WMOD.0
Always logic zero
NOTE: System clock 4.19 assumed.
4-33
MEMORY
NOTES
4-34
Oscillator Circuits Interrupts Power-Down
RESET
Ports Timers Timer/Counters DTMF Generator Electrical Data Mechanical Data KS57P5208/P5308/P5312 Development Tools
OSCILLATOR CIRCUITS
Basic timer
OSCILLATOR CIRCUITS
microcontrollers have oscillator circuit, system clock circuit, (fx). peripheral hardware operates system clock frequency supplied through this circuit. Specifically, clock pulse required following peripheral modules:
Timer/counter Watch timer Clock output circuit Clock Control Registers power control register, PCON, used select normal operating mode power-down modes stop idle. Bits PCON register manipulated STOP IDLE instruction engage stop idle power-down mode. system clock frequencies divided manipulating PCON bits select following frequencies selected system clock.
OSCILLATOR CIRCUITS
Main System Oscillator Circuit
DTMF generator
XOUT
1-1/4096 Frequency dividing Circuit 1/16 Watch Timer Basic Timer Timer/Counter Clock Output Circuit
Oscillator Stop
Selector
Clock stop signal (IDLE mode)
PCON.0 PCON.1 IDLE STOP PCON.2 PCON.3 Oscillator Control Circuit Wait release signal Internal RESET signal Power-down release signal
PCON.3, clear
Figure 6-1. Clock Circuit Diagram
OSCILLATOR CIRCUITS
System Oscillator Circuits
XOUT XOUT
Figure 6-2. Crystal/Ceramic Oscillator
Figure 6-3. External Oscillator
OSCILLATOR CIRCUITS
POWER CONTROL REGISTER (PCON) power control register, PCON, 4-bit register that used select clock frequency control operating power-down modes. PCON addressed directly 4-bit write instructions indirectly instructions IDLE STOP. FB3H PCON.3 PCON.2 PCON.1 PCON.0
PCON bits addressed STOP IDLE instructions, respectively, engage IDLE STOP power-down modes. IDLE STOP modes initiated these instruction despite current value enable memory bank flag (EMB). manipulating bits PCON register, system clock frequency divided
RESET sets PCON register values logic zero: PCON.1 PCON.0 divide frequency PCON.3
PCON.2 enable normal operating mode. Table 6-1. Power Control Register (PCON) Organization PCON Settings PCON.3 PCON.2 Normal operating mode Idle power-down mode Stop power-down mode Resulting Clock Frequency fx/64 fx/8 fx/4 Resulting Operating Mode
PCON Settings PCON.1 PCON.0
PROGRAMMINGNG Setting Clock
clock 1.05 4.19 MHz: BITS A,#3H PCON,A
OSCILLATOR CIRCUITS
INSTRUCTION CYCLE TIMES unit time that equals machine cycle varies depending oscillator clock signal divided system clock. Table shows corresponding cycle times microseconds. Table 6-2. Instruction Cycle Times Clock Rates Selected Clock fx/64 fx/8 fx/4 Resulting Frequency 65.5 524.0 1.05 Oscillation Source 4.19 Cycle Time (µsec) 15.3 1.91 0.95
CLOCK OUTPUT MODE REGISTER (CLMOD) clock output mode register, CLMOD, 4-bit register that used enable disable clock output select clock source frequency. CLMOD addressable 4-bit write instruction only. FD0H
RESET
CLMOD.3
CLMOD.
CLMOD.0
clears CLMOD logic zero, which automatically selects clock clock source (without initiating clock oscillation), disable clock output. CLOMD.3 enable/disable clock output control bit; CLOMD.1 CLOMD.0 used select four possible clock sources frequencies: normal clock, fx/8, fx/16, fx/64. Table 6-3. Clock Output Mode Register (CLMOD) Organization CLMOD Setting CLMOD.1 CLMOD.0 Clock Source clock (fx/4, fx/8, fx/64) fx/8 fx/16 fx/64 Resulting Clock Output Frequency 1.05 MHz,524 kHz, 65.5 65.5
CLMOD.3 Clock output disable Clock output enable
Result CLMOD.3 Setting
NOTE: Frequencies assume that 4.19 MHz.
OSCILLATOR CIRCUITS
CLOCK OUTPUT CIRCUIT clock output circuit, used output clock pulses pin, following components: 4-bit clock output mode register (CLMOD) Clock selector output latch Port mode flag output (P2.2)
CLMOD.3 CLMOD.2 CLMOD.1 CLMOD.0 CLOCK SELECTOR P2.2 Output Latch PM2.2
CLOCKS (CPU clock, fx/8, fx/16, fx/64)
Figure 6-4. Output Circuit Diagram
CLOCK OUTPUT PROCEDURE procedure outputting clock pulses summarized follows: Disable clock output clearing CLMOD.3 logic zero. clock output frequency (CLMOD.1, CLMOD.0). Load output latch (P2.2). P2.2 mode flag output mode. Enable clock output setting CLMOD.3 logic one.
PROGRAMMING Clock Output
output clock BITS BITR EA,#04H PMG1,EA P2.2 A,#8H CLMOD,A
Output mode Clear P2.2 output latch
INTERRUPTS
INTERRUPTS
interrupt control circuit five functional components: Interrupt enable flags (IEx) Interrupt request flags (IRQx) Interrupt mask enable register (IME) Interrupt priority register (IPR) Power-down release signal circuit Three kinds interrupts supported: Internal interrupts generated on-chip processes External interrupts generated external peripheral devices Quasi-interrupts used edge detection clock sources
Table 7-1. Interrupt Types Corresponding Port Pin(s) Interrupt Type External interrupts Internal interrupts Quasi-interrupts Interrupt Name INT0, INT1 (note), INT4 (note) INTB, INTT0, INTT1 INT2 INTW Corresponding Port P1.0, P1.1 (note), P1.3 (note) applicable P1.2 (note), KS0-KS7 applicable
NOTE: KS57C5304/5308/C5312 does interrupts INT1, INT4, INT2 pin.
INTERRUPTS
VECTORED INTERRUPTS Interrupt requests processed vectored interrupts hardware, they generated program software. vectored interrupt generated when following flags register settings, corresponding specific interrupt (INTn) logic one: Interrupt enable flag (IEx) Interrupt master enable flag (IME) Interrupt request flag (IRQx) Interrupt status flags (IS0, IS1) Interrupt priority register (IPR) conditions satisfied execution requested service routine, start address interrupt loaded into program counter program starts executing service routine from this address. flags memory banks registers stored vector address area during interrupt service routines. flags stored beginning program with VENT instruction. initial flag values determine vectors resets interrupts. Enable flag values saved during main routine, well during service routines. changes that made enable flag values during service routine stored vector address. When interrupt occurs, enable flag values before interrupt initiated saved along with program status word (PSW), enable flag values interrupt fetched from respective vector address. Then, necessary, modify enable flags during interrupt service routine. When interrupt service routine returned main routine IRET instruction, original values saved stack restored main program continues program execution with these values. Software-Generated Interrupts generate interrupt request from software, program manipulates appropriate IRQx flag. When interrupt request flag value set, retained until other conditions vectored interrupt have been met, service routine initiated. Multiple Interrupts manipulating interrupt status flags (IS0 IS1), control service routine initialization thereby process multiple interrupts simultaneously. more than four interrupts being processed time, avoid possible loss working register data using PUSH instruction save register contents stack before service routines executed same register bank. When routines have executed successfully, restore register contents from stack working memory using instruction. Power-Down Mode Release interrupt used release power-down mode (stop idle). Interrupts power-down mode release initiated setting corresponding interrupt enable flag. Even flag cleared zero, power-down mode will released interrupt request signal when interrupt enable flag been set. such cases, interrupt routine will executed since "0".
INTERRUPTS
Interrupt generated (INT
Request flag (IRQx)
Retain value until
Generate corresponding vector interrupt release power-down mode
IS1, IS1, High-priority interrupt IS1, IS1,
Retain value until IME=
Retain value until interrupt service routine completed
Store contents stack area; contents corresponding vector address
both interrupt sources shared vector address used?
IRQx flag value remains
Reset corresponding IRQx flag
Jump interrupt start address
Jump interrupt start address
Verify interrupt source clear IRQx with BTSTZ instruction
Figure 7-1. Interrupt Execution Flowchart
INTERRUPTS
IMOD
IMOD0
IET1 IET0 INTB IRQB IRQ4
INT4 INT0 INT1 INTT0 INTT1 INTW INT2 SELECTOR KS0-KS7
IRQ0 IRQ1 IRQT0 IRQT1 IRQW IRQ2
IMOD2
Power-Down Mode Release Signal Interrupt Control Unit
Edge Detection Circuit
Vector Interrupt Generator
Figure 7-2. Interrupt Control Circuit Diagram (KS57C5204/5208)
INTERRUPTS
IMOD0
IET1 IET0 INTB IRQB IRQ0 IRQT0 IRQT1 IRQW IRQ2
INT0
INTT0 INTT1 INTW
KS0-KS7
SELECTOR
IMOD2
Power-Down Mode Release Signal Interrupt Control Unit
Edge Detection Circuit
Vector Interrupt Generator
Figure 7-3. Interrupt Control Circuit Diagram (KS57C5304/5308/C5312)
INTERRUPTS
Multiple Interrupts interrupt controller service multiple interrupts ways: two-level interrupts, where either interrupt requests only those highest priority serviced, multi-level interrupts, when interrupt service routine lower-priority request accepted during execution higher priority routine. Two-Level Interrupt Handling Two-level interrupt handling standard method processing multiple interrupts. When bits (FB0H.3 FB0H.2, respectively) both logic zero, program execution mode normal interrupt requests serviced (see Figure 7-3). Whenever interrupt request accepted, incremented ("0" "0"), values stored stack along with other bits. After interrupt routine been serviced, modified values automatically restored from stack IRET instruction. manipulated directly 1-bit write instructions, regardless current value enable memory bank flag (EMB). Before modify interrupt status flag, however, must first disable interrupt processing with instruction. When "1", interrupt service routines inhibited except highest priority interrupt currently defined interrupt priority register (IPR).
Normal Program Processing (Status Disable Enable High Level Interrupt Generated
High Level Interrupt Processing (Status High Level Interrupt Processing (Status
High Level Interrupt Generated
Figure 7-4. Two-Level Interrupt Handling
INTERRUPTS
Multi-Level Interrupt Handling With multi-level interrupt handling, lower-priority interrupt request executed while high-priority interrupt being serviced. This done manipulating interrupt status flags, (see Table 7-2). When interrupt requested during normal program execution, interrupt status flags "0", respectively. This setting allows only highest-priority interrupts serviced. When high-priority request accepted, both interrupt status flags then cleared software that request priority level serviced. this way, high- low-priority requests serviced parallel (see Figure 7-4).
Table 7-2. Manipulation Multi-Level Interrupt Handling Process Status Before interrupt requests serviced. Only high-priority interrupts determined current settings register serviced. additional interrupt requests will serviced. Value undefined Effect Setting After
Normal Program Processing (Status Disable Enable High Level Interrupt Generated
Single Interrupt 2-Level Interrupt
Disable Modify Status Enable High Level Interrupt Generated
Status
3-Level Interrupt
Status High Level Interrupt Generated Status Status
Status
Figure 7-5. Multi-Level Interrupt Handling
INTERRUPTS
INTERRUPT PRIORITY REGISTER (IPR) 4-bit interrupt priority register (IPR) used control multi-level interrupt handling. reset value logic zero. Before modified 4-bit write instructions, interrupts must first disabled instruction. FB2H IPR.2 IPR.1 IPR.0
manipulating settings, choose process interrupt requests with same priority level, select type interrupt high-priority processing. low-priority interrupt itself interrupted high-priority interrupt, another low-priority interrupt. high-priority interrupt cannot interrupted other interrupt source. Table 7-3. Standard Interrupt Priorities Interrupt INTB, INT4 INT0 INT(note) (note)
Default Priority
INTT0 INTT
IPR, interrupt master enable flag (IME), enables disables interrupt processing. Even interrupt request flag corresponding enable flag set, service routine cannot executed until flag logic one. flag directly manipulated instructions, regardless current enable memory bank (EMB) value. Table 7-4. Interrupt Priority Register Settings IPR.2 IPR.1 IPR.0 Result Setting Normal interrupt handling according default priority settings Process INTB INT4 (note) interrupts highest priority Process INT0 interrupts highest priority Process INT1 (note) interrupts highest priority Process INTT0 interrupts highest priority Process INTT1 interrupts highest priority
NOTES: During normal interrupt processing, interrupts processed order which they occur. more interrupts occur simultaneously, processing order determined default interrupt priority settings shown Table 7-3. Using settings, select specific interrupts high-priority processing event contention. When high-priority (IPR) interrupt been processed, waiting interrupts handled according their default priorities. KS57C5304/C5308/C5312 does INT1 INT4 interrupts.
INTERRUPTS
Programming Setting Interrupt Priority
following instruction sequence sets INT1 interrupt high priority: BITS IPR.3 (IME) A,#3H IPR,A IPR.3 (IME)
EXTERNAL INTERRUPT MODE REGISTERS (IMOD0, IMOD1) following components used process external interrupts INT0 INT1 (note) pin: Edge detection circuit mode registers, IMOD0 IMOD1 (note) mode registers used control triggering edge input signal. IMOD0 IMOD1 (note) settings choose either rising falling edge incoming signal interrupt request trigger. INT4 (note) interrupt exception since input signal generates interrupt request both rising falling edges. FB4H FB5H IMOD0.1 IMOD0.0 IMOD1.0(NOTE)
IMOD0 IMOD1 (note) bits addressable 4-bit write instructions. RESET clears IMOD values logic zero, selecting rising edges trigger incoming interrupt requests. Table 7-5. IMOD0 IMOD1 Register Organization IMOD0 IMOD0.1 IMOD1 (note) IMOD0.0 IMOD1.0 Effect IMOD0 Settings Rising edge detection Falling edge detection Both rising falling edge detection IRQ0 flag cannot Effect IMOD1 Settings Rising edge detection Falling edge detection
NOTE: KS57C5304/C5308/C5312 does INT1 INT4 interrupts.
INTERRUPTS
EXTERNAL INTERRUPT MODE REGISTERS (CONTINUED)
INT0
Edge Detection
IRQ0
INT(note)
Edge Detection
IRQ(note)
IMOD0 P1.1(note) P1.0
IMOD(note)
Figure 7-6. Circuit Diagram INT0 INT1 Pins
When modifying IMOD0 IMOD1 registers, possible accidentally interrupt request flag. avoid unwanted interrupts, take these precautions when writing your programs: Disable interrupts with instruction. Modify IMOD0 IMOD1 register. Clear relevant interrupt request flags. Enable interrupt setting appropriate flag. Enable interrupts with instructions.
NOTE: KS57C5304/C5308/C5312 does INT1 P1.1.
7-10
INTERRUPTS
EXTERNAL INTERRUPT MODE REGISTER (IMOD2) mode register external interrupts KS0-KS7 pins, IMOD2, addressable only 4-bit write instructions. RESET clears IMOD2 bits logic zero. FB6H IMOD2.1 IMOD2.0
When IMOD2 cleared logic zero, INT2 uses rising edge incoming signal interrupt request trigger. rising edge detected INT2 pin, when falling edge detected pins KS0KS7, IRQ2 flag logic release signal power-down mode generated. more pins which configured interrupt (KS0-KS7) input output) state, interrupt occurred. Table 7-6. IMOD2 Register Settings IMOD2 IMOD2.1 NOTE: KS57C5304/C5308/C5312 does INT2 pin.
IMOD2.0
Effect IMOD2 Settings Select rising edge INT2 (note) Select falling edge KS4-KS7 Select falling edge KS2-KS7 Select falling edge KS0-KS7
INTERRUPTS
2(note) P7.3/KS7 P7.2/KS6 P7.1/KS5 P7.0/KS4 P6.3/KS3 P6.2/KS2 P6.1/KS1 P6.0/KS0
Rising Edge Detection
Falling Edge Detection Circuit
Clock Selector IMOD2
IRQ2
NOTES: generate interrupt falling edge KS0-KS7, KS0-KS7 pins must configured input mode. Particularly, KS4-KS7 must always configured input mode. KS57C5304/C5308/C5312 does INT2 pin.
Figure 7-7. Circuit Diagram INT2 KS0-KS7 Pins
7-12
INTERRUPTS
PROGRAMMING Using INT2 Input Interrupt
When INT2 interrupt used interrupt, selected interrupt source must input: When KS0-KS7 selected (eight pins): BITS IMOD2, #00H PMG3, PUMOD2,
(IMOD2) #3H, KS0-KS7 falling edge select input mode Enable pull-up resistors
When KS2-KS7 selected (six pins): BITS IMOD2, #03H PMG3, PUMOD2,
(IMOD2) #2H, KS2-KS7 falling edge select P6.2-P6.3 input mode Enable pull-up resistors
When KS4-KS7 selected (four pins), must specified strobe signal input: BITS IMOD2, #0FH PMG3, PUMOD2,
(IMOD2) #1H, KS4-KS7 falling edge select
Enable pull-up resistor
7-13
INTERRUPTS
INTERRUPT FLAGS There three types interrupt flags: interrupt request interrupt enable flags that correspond each interrupt, interrupt master enable flag, which enables disables interrupt processing. Interrupt Master Enable Flag (IME) interrupt master enable flag, IME, enables disables interrupt processing. Therefore, even when IRQx flag corresponding flag enabled, interrupt service routine executed until flag logic one. flag located register (IPR.3). directly manipulated instructions, regardless current value enable memory bank flag (EMB). Interrupt Enable Flags (IEx) flags, when logical one, enable specific interrupt requests serviced. When interrupt request flag logic one, interrupt will serviced until corresponding flag also enabled. Interrupt enable flags read, written, tested directly 1-bit instructions (BITS BITR) 4-bit instructions. flags addressed directly their specific addresses, despite current value enable memory bank (EMB) flag. Table 7-7. Interrupt Enable Interrupt Request Flag Addresses Address FB8H FBAH FBBH FBCH FBEH FBFH
IPR.2
IPR.
IPR.0
Effect Settings Inhibit interrupts Enable interrupts
IRQ4 IRQ1
IET1 IET0
IRQB IRQW IRQT1 IRQT0 IRQ0 IRQ2
NOTES: refers generically interrupt enable flags. IRQx refers generically interrupt request flags. interrupt disable mode. interrupt enable mode. KS57C5304/5308/C5312 does IE1, IE4, IRQ1, IRQ4 interrupts.
7-14
INTERRUPTS
Interrupt Request Flags (IRQx) Interrupt request flags, read/write addressable 1-bit 4-bit instructions. IRQx flags addressed directly their specific addresses, regardless current value enable memory bank (EMB) flag. When specific IRQx flag logic one, corresponding interrupt request generated. flag then automatically cleared logic zero when interrupt been serviced. Exceptions watch timer interrupt request flags, IRQW, external interrupt flag IRQ2, which must cleared software after interrupt service routine executed. IRQx flags also used execute interrupt requests from software. summary, follow these guidelines using IRQx flags: IRQx request interrupt when interrupt meets condition interrupt generation. IRQx hardware then cleared hardware when interrupt been serviced (with exception IRQW IRQ2). IRQx software, interrupt also generated. When interrupts share same service routine start address, interrupt processing occur ways: When only interrupt enabled, IRQx flag cleared automatically when interrupt been serviced. When interrupts enabled, request flag automatically cleared that user opportunity locate source interrupt request. this case, IRQx setting must cleared manually using BTSTZ instruction.
Table 7-8. Interrupt Request Flag Conditions Priorities Interrupt Source INTB INT4 INT0 INT1 INTT0 INTT1 INT2
Internal External
Pre-condition IRQx Flag Setting Reference time interval signal from basic timer Both rising falling edges detected INT4 Rising falling edge detected INT0 Rising falling edge detected INT1 Signals TCNT0 TREF0 registers match Signals TCNT1 TREF1 registers match Rising edge detected INT2 else falling edge detected KS0-KS7 pins Time interval secs 3.91 msecs
Interrupt Priority
Flag Name IRQB IRQ4 IRQ0 IRQ1 IRQT0 IRQT1 IRQ2 IRQW
INTW
NOTES: quasi-interrupt INT2 only used testing incoming signals. KS57C5304/C5308/C5312 does INT2 pin, INT1, INT4 interrupts.
7-15
INTERRUPTS
INTB
PROGRAMMING Enabling INTB INT4 Interrupts
simultaneously enable INTB INT4 interrupts: BTSTZ IRET BITR IRET IRQB INT4 IRQB INT4 interrupt; yes, INTB interrupt processed
INT4
IRQ4
INT4 processed
7-16
POWER-DOWN
POWER-DOWN
microcontroller power-down modes reduce power consumption: idle stop. Idle mode initiated IDLE instruction stop mode instruction STOP. (Several instructions must always follow IDLE STOP instruction program.) idle mode, clock stops while peripherals oscillation source continue operate normally. When RESET occurs during normal operation during power-down mode, reset operation initiated enters idle mode. When standard oscillation stabilization time interval (31.3 4.19 MHz) elapsed, normal operation resumes. stop mode, system clock oscillation halted (assuming currently operating), peripheral hardware components powered-down. effect stop mode specific peripheral hardware components CPU, basic timer, timer/counters, watch-timer external interrupt requests, detailed Table 8-1. NOTE stop mode using external clock source because input must restricted internally reduce current leakage. Idle stop modes terminated either RESET, interrupt which enabled corresponding interrupt enable flag, IEx. When power-down mode terminated RESET input, normal reset operation executed. Assuming that both interrupt enable flag interrupt request flag "1", power-down mode released immediately upon entering power-down mode. When interrupt used release power-down mode, operation differs depending value interrupt master enable flag (IME): flag "0", program execution started immediately after instruction which issues request enter power-down mode. interrupt request flag remains logic one. flag "1", instructions executed after power-down mode release. Then, vectored interrupt initiated. However, when release signal caused INT2 INTW, operation identical condition. That vector interrupt generated.
POWER-DOWN
Table 8-1. Hardware Operation During Power-Down Modes Operation Clock oscillator Basic timer Timer/counter Timer/counter Watch timer External interrupts Power-down mode release signal Stop Mode (STOP) System clock oscillation stops Basic timer stops Operates only TCL0 selected counter clock Operates only TCL1 selected counter clock Watch timer operation stopped INT0, INT1, INT2, INT4 acknowledged operations disabled Interrupt request signals enabled interrupt enable flag RESET input Idle Mode (IDLE) clock oscillation stops (system clock oscillation continues) Basic timer operates (with IRQB each reference interval) Timer/counter operates Timer/counter operates Watch timer operates INT0, INT1, INT2, INT4 acknowledged operations disabled Interrupt request signals enabled interrupt enable flag RESET input
NOTE: KS57C5304/C5308/C5312 does INT1 INT4 interrupts.
POWER-DOWN
IDLE MODE TIMING DIAGRAMS
Idle Instruction
RESET
Oscillation Stabilization (36.6 ms/3.58 MHz)
Normal Mode
Idle Mode
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-1. Timing When Idle Mode Released RESET
Idle Instruction Mode Release Signal Normal Mode Idle Mode Interrupt Acknowledge (IME
Normal Mode
Clock Signal
Normal Oscillation
Figure 8-2. Timing When Idle Mode Released Interrupt
POWER-DOWN
STOP MODE TIMING DIAGRAMS
Stop Instruction
RESET
Oscillation Stabilization (36.6 ms/3.58 MHz)
Normal Mode
Stop mode Oscillation Stops
Idle Mode
Normal Mode
Clock Signal
Oscillation Resumes
Figure 8-3. Timing When Stop Mode Released RESET
Stop Instruction Mode Release signal Normal Mode Stop mode Oscillation Stops
Oscillation Stabilization (BMOD Setting) (IME=1) Idle Mode Normal Mode
Clock Signal
Oscillation Resumes
Figure 8-4. Timing When Stop Mode Release Interrupt
POWER-DOWN
PORT CONFIGURATION POWER-DOWN following method describes configure port pins reduce power consumption during power-down modes (stop, idle): Condition microcontroller configured external device:
Connect unused port pins according information Table 8-2. Disable pull-up resistors output pins making appropriate modifications pull-up resistor mode register, PUMOD. Reason: output goes when pull-up resistor enabled, there unexpected surges current through pull-up. Disable pull-up resistors input pins configured levels order check current input option. Reason: input level port when pull-up resistor enabled, will draw unnecessarily large current. Condition microcontroller configured external device external device's source turned power-down mode.
Connect unused port pins according information Table 8-2. Disable pull-up resistors output pins making appropriate modifications pull-up resistor mode register, PUMOD. Reason: output goes when pull-up resistor enabled, there unexpected surges current through pull-up. Disable pull-up resistors input pins configured levels order check current input option. Reason: input level port when pull-up resistor enabled, will draw unnecessarily large current. Disable pull-up resistors input pins connected external device making necessary modifications PUMOD register. Configure output pins that connected external device level. Reason: When external device's source turned off, microcontroller's output pins high level, supplied external device through input pin. This causes device operate level this case, total current consumption would reduced. Determine correct output state necessary block current pass according with external transistors (PNP, NPN).
POWER-DOWN
RECOMMENDED CONNECTIONS UNUSED PINS reduce overall power consumption, please configure unused pins according guidelines described Table 8-2. Table 8-2. Unused Connections Reduced Power Consumption Pin/Share Names P1.0/INT0 INT2 P1.3/INT4 P2.0/TCLO0 P2.1/TCLO1 P2.2/CLO P2.3/BUZ P3.0/TCL0 P3.1/TCL1 P3.2 P3.3 P4.0/BTCO P4.1-P4.3 P5.0-P5.3 P6.0/KS0-P6.3/KS3 P7.0/KS4-P7.3/KS7 P8.0-P8.3 P9.0-P9.2 DTMF Connect Input mode: Connect Output mode: connection Recommended Connection
connection Connect
NOTE: P1.1/INT1, P1.2/INT2, P1.3/INT4, P3.2, P3.3, used KS57C5304/C5308/C5312.
RESET
Carry flag
RESET
When RESET signal input during normal operation power-down mode, hardware reset operation initiated enters idle mode. Then, when standard oscillation stabilization interval 36.6 3.58 elapsed, normal system operation resumes. Regardless when RESET occurs during normal operating mode during power-down mode most hardware register values reset values described Table below. current status several register values however, always retained when RESET occurs during idle stop mode; RESET occurs during normal operating mode, their values undefined. Current values that retained this case follows:
General-purpose registers
Oscillation Stabilization (36.6 ms/3.58 MHz)
RESET
Input Normal Mode Power-Down Mode Reset Operation
Idle Mode
Operating Mode
Figure 9-1. Timing Oscillation Stabilization After RESET
RESET
HARDWARE REGISTER VALUES AFTER RESET Table gives detailed information about hardware register values after RESET occurs during power-down mode during normal operation. Table 9-1. Hardware Register Values after RESET Hardware Component Subcomponent Program counter (PC)
RESET Occurs During Power-Down Mode
RESET
Occurs During Normal Operation
Lower five bits address 0000H transferred PC12-8, contents 0001H PC7-0.
Lower five bits address 0000H transferred PC12-8, contents 0001H PC7-0.
Program Status Word (PSW): Carry flag Skip flag (SC0-SC2) Interrupt status flags (IS0, IS1) Bank enable flags (EMB, ERB) Values retained address 0000H program memory transferred flag, address flag. Undefined Undefined address 0000H program memory transferred flag, address flag. Undefined
Stack pointer (SP) Data Memory (RAM): General registers General-purpose registers Bank selection registers (SMB, SRB) register (BSC0-BSC) Clocks: Power control register (PCON) Clock output mode register (CLMOD) Interrupts: Interrupt request flags (IRQx) Interrupt enable flags (IEx) Interrupt priority flag (IPR) Interrupt master enable flag (IME) INT0 mode register (IMOD0) INT1 mode register (IMOD1) INT2 mode register (IMOD2)
Values retained Values retained
Undefined Undefined
NOTES: value 0F8H-0FDH retained when RESET signal input. KS57C5304/C5308/C5312 does IMOD1.
RESET
Table 9-1. Hardware Register Values after RESET (Continued) Hardware Component Subcomponent Ports: Output buffers Output latches Port mode flags (PMG) Pull-up resistor mode (PUMOD1/2) Port open-drain enable register (PNE1) Basic Timer: Count register (BCNT) Mode register (BMOD) Output enable flag (BOE) Timer/Counters Count registers (TCNT0/1) Reference registers (TREF0/1) Mode registers (TMOD0/1) output enable flags (TOE0/1) output latch (TOL0/1) Watch Timer: Watch timer mode register (WMOD) Watchdog Timer mode register (WDMOD) clear flag (WDTCF) DTMF Generator: DTMF mode register (DTMR) FFH/FFH FFH/FFH Undefined Undefined
RESET Occurs During Power-Down Mode
RESET
Occurs During Normal Operation
RESET
NOTES
PORTS
Port Mode Flags
PORTS
KS57C5204/C5208 input port eight ports. KS57C5304/C5308/C5312 input port ports. addresses ports mapped bank RAM. contents port latches read, written, tested corresponding address using manipulation instructions. KS57C5204/C5208 four input pins configurable pins maximum number pins. KS57C5304/C5308/C5312 input configurable pins maximum number pins.
Port mode flags (PM) used configure ports (port mode group ports (port mode group ports (port mode group port (port mode group KS57C5204/C5208 only) input output mode setting clearing corresponding buffer. flags grouped four 8-bit registers, addressable 8-bit write instructions only. PUMOD Control Register pull-up mode registers, PUMOD1 8-bit 4-bit registers, respectively, used assign internal pullup resistors software specific ports. When configurable ports through serves output pin, assigned pull-up resistor automatically disabled, even though pin's pull-up resistor enabled corresponding setting pull-up resistor mode register (PUMOD). PUMOD1 addressable 8-bit write instructions only, PUMOD2 addressable 4-bit write instructions only. RESET clears PUMOD register values logic zero, automatically disconnecting software-assignable port pullup resistors. Table 10-1. Port Overview Port Pins Names P1.0 P1.1-P1.3 (note) P2.0-P2.3 P3.0-P3.1 P3.2-P3.3 (note) Address FF1H Function Description 4-bit input port. 1-bit 4-bit read test possible. 1-bit pull-up resistors software assignable 4-bit ports. 1-bit 4-bit read/write/test possible. Ports pins individually software configurable input output. 4-bit Pull-up resistors software assignable; pull-up registers automatically disabled output pins. Ports paired 8-bit data transfer.
FF2H FF3H
PORTS
Table 10-1. Port Overview (Continued) Port Pins Names P4.0-P4.3 P5.0-P5.3 Address FF4H FF5H Function Description 4-bit ports. 1-bit 4-bit read/write/test possible. Port pins individually software configurable input output. 4-bit pull-up resistors software assignable; pull-up registers automatically disable output pins. N-Ch open drain push-pull output selected software. Ports paired 8-bit data transfer. 4-bit ports. 1-bit 4-bit read/write/test possible. Port pins individually software configurable input output. 4-bit pull-up resistors software assignable; pull-up registers automatically disabled output pins. Ports paired 8-bit data transfer. 4-bit port. 1-bit 4-bit read/write test possible. Ports pins individually software configurable input output. 4-bit pull-up resistors software assignable; pull-up registers automatically disable output pins. Ports paired 8-bit data transfer.
P6.0-P6.3 P7.0-P7.3
FF6H FF7H
(note)
P8.0-P8.3 P9.0-P9.2
FF8H FF9H
NOTE: KS57C5304/C5308/C5312 does P1.1-P1.3, P3.2-P3.3, ports.
Table 10-2. Port Status During Instruction Execution Instruction Type 1-bit test 1-bit input 4-bit input 8-bit input 1-bit output 4-bit output 8-bit output Example BTST BITR P2.3 C,P1.0 A,P7 EA,P4 P2.3 P2,A P6,EA Input Mode Status Input test data each Output Mode Status Input test data output latch
Output latch contents undefined Transfer accumulator data output latch
Output status modified Transfer accumulator data output
10-2
PORTS
PORT MODE FLAGS FLAGS) Port mode flags (PM) used configure ports input output mode setting clearing corresponding buffer. convenient program reference, flags organized into four groups PMG1, PMG2, PMG3, PMG4 shown Table 10-3. flags addressable 8-bit write instructions only. When flag "0", port input mode; when "1", port enabled output. RESET clears port mode flags logic zero, automatically configuring corresponding ports input mode. Table 10-3. Port Mode Group Flags Group PMG1 Address FE8H FE9H PMG2 PMG3
PM2.3 PM3.3 PM4.3 PM5.3 PM6.3 PM7.3 PM8.3
PM2.2 PM3.2 PM4.2 PM5.2 PM6.2 PM7.2 PM8.2 PM9.2
PM2.1 PM3.1 PM4.1 PM5.1 PM6.1 PM7.1 PM8.1 PM9.
PM2.0 PM3.0 PM4.0 PM5.0 PM6.0 PM7.0 PM8.0 PM9.0
FEAH FEBH FECH FEDH FEEH FEFH
PMG4
NOTES "0", corresponding input mode. "1", output mode: port flags cleared following RESET. KS57C5304/C5308/C5312 does PM3.2, PM3.3, PMG4.
PROGRAMMING Configuring Ports Input Output
Configure P2.3 output port other ports input ports: BITS EA,#0F8H PMG1,EA EA,#00H PMG2,EA PMG3,EA PMG4,EA
P2.3, Output, P2.0-P2.2 Input Input, Input Input
NOTE: KS57C5304/C5308/C5312 does P1.1-P1.3, P3.2-P3.3, P8.9.
10-3
PORTS
PULL-UP RESISTOR MODE REGISTER (PUMOD) pull-up resistor mode registers (PUMOD1 8-bit registers used assign internal pull-up resistors software specific ports. When configurable ports through used output pin, assigned pull-up resistor automatically disabled, even though pin's pull-up enabled corresponding PUMOD setting. PUMOD1 addressable 8-bit write instructions only. PUMOD2 addressable 4bit write instructions only. RESET clears PUMOD register values logic zero, automatically disconnecting software-assignable port pullup resistors. Table 10-4. Pull-Up Resistor Mode Register (PUMOD) Organization PUMOD PUMOD1 PUMOD2 Address FDCH FDDH FDEH PUR1.3 PUR5 PUR9
PUR1.2 PUR4 PUR8
PUR1.1 PUR3 PUR7
PUR1.0 PUR2 PUR6
NOTES: When "1", pull-up resistors assigned corresponding port: PUR3 port PUR2 port KS57C5304/C5308/C5312 does PUR1.1-PUR1.3, PUR8, PUR9.
PROGRAMMING Enabling Disabling Port Pull-Up Resistors
P2-P5 enable pull-up resistors, disable pull-up resistors. BITS EA,#0F0H PUMOD1,EA
P2-P5 enable
N-CHANNEL OPEN-DRAIN MODE REGISTER (PNE1) n-channel, open-drain mode register (PNE1) used configure ports n-channel open-drain push-pull outputs. When PNE1 register "1", corresponding output configured n-channel open-drain; when "0", output configured push-pull. PNE1 register consists 8-bit register. PNE1 addressed 8-bit write instructions only. Table 10-5. N-Channel Open Drain Mode Register (PNE1) Organization Register PNE1 Address FDAH FDBH PNE4.3 PNE5.3 PNE4.2 PNE5.2 PNE4.1 PNE5.1 PNE4.0 PNE5.0
10-4
PORTS
PORT CIRCUIT DIAGRAM
INT0 INT1 INT2 INT4
PUR1.0 PUR1.1 PUR1.2 PUR1.3
P1.0/INT0 P1.1/INT1 P1.2/INT2 P1.3/INT4
NOTE:
KS57C5304/C5308/C5312 does P1.1-P1.3.
Figure 10-1. Port Circuit Diagram
10-5
PORTS
PORT CIRCUIT DIAGRAM
port number 7,8, PURx PMx.3 PURx PMx.2 PURx PMx.1 PURx PMx.0
Px.0 Px.1 Px.2 Px.3
Output Latch
NOTES: When port acts output, pull-up resistor automatically disabled, even though port's pull-up resistor enabled settings pull-up resistor mode register (PUMOD). KS57C5304/C5308/C5312 does P3.2, P3.3,
Figure 10-2. Port Circuit Diagram
10-6
PORTS
PORT CIRCUIT DIAGRAM
P-CH PUMOD1.a
P-CH Output Latch
Px.b
N-CH
PMx.b
Figure 10-3. Port Circuit Diagram
10-7
PORTS
NOTES
10-8
TIMERS TIMER/COUNTERS
Watch timer (WT)
TIMERS TIMER/COUNTERS
microcontroller four timer timer/counter modules: 8-bit basic timer (BT) 8-bit timer/counters (TC0, TC1)
8-bit basic timer (BT) microcontroller's main interval timer. generates interrupt request fixed time interval when appropriate modification made mode register. When contents basic timer counter register BCNT overflows, pulse output basic timer output pin, BTCO. basic timer also functions 'watchdog' timer used determine clock oscillation stabilization time when stop mode released interrupt after RESET. 8-bit timer/counters (TC0, TC1) programmable timer/counters that used primarily event counting clock frequency modification output. watch timer (WT) module consists 8-bit watch timer mode register, clock selector, frequency divider circuit. Watch timer functions include real-time watch-time measurement, system clock interval timing, buzzer output generation.
TIMERS TIMER/COUNTERS
BASIC TIMER (BT)
OVERVIEW 8-bit basic timer (BT) functional components: Clock selector logic 4-bit mode register (BMOD) 8-bit counter register (BCNT) Output enable flag (BOE) 8-bit watchdog timer mode register (WDMOD) Watchdog timer counter clear flag (WDTCF) basic timer generates interrupt requests precise intervals, based frequency system clock. Timer pulses output from basic timer's counter register BCNT output BTCO when overflow occurs counter register BCNT. basic timer "watchdog" timer monitoring system events output stabilize clock oscillation when stop mode released interrupt following RESET. settings basic timer mode register BMOD turns module off, selects input clock frequency, controls interrupt stabilization intervals. Interval Timer Function basic timer's primary function measure elapsed time intervals. standard time interval equal basic timer clock pulses. restart basic timer, setting required: mode register BMOD should logic one. input clock frequency interrupt stabilization interval selected loading appropriate values BMOD.2-BMOD.0. 8-bit counter register, BCNT, incremented each time clock signal detected that corresponds frequency selected BMOD. BCNT continues incrementing counts clocks until overflow occurs 255). overflow causes interrupt request flag (IRQB) logic signal that designated time interval elapsed. Then, interrupt request generated, BCNT cleared logic zero, counting continues from 00H. Watchdog Timer Function basic timer also used "watchdog" timer signal occurrence system program operation error. this purpose, instruction that clear watchdog timer (BITS WDTCF) should executed proper points program within given period.
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