1394a-2000 Integrated Host Controller IEEE 1394a 2000 IEEE 1394-1
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VT6307
1394a-2000 Integrated Host Controller
IEEE 1394a 2000 IEEE 1394-1995 OHCI Link Layer Controller with Integrated Mbit 2-Port
Revision October 2002
TECHNOLOGIES, INC.
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Copyright 2002, Technologies, Incorporated. Printed United States. RIGHTS RESERVED. part this document reproduced, transmitted, transcribed, stored retrieval system, translated into language, form means, electronic, mechanical, magnetic, optical, chemical, manual otherwise without prior written permission Technologies Incorporated. VT6304, VT6305, VT6306 VT6307 only used identify product Technologies, Inc. registered trademark Technologies, Incorporated. Windows 98TM, Windows NTTM, Windows 2000TM, Windows XPTM, Plug Playare registered trademarks Microsoft Corp. PCIis registered trademark Special Interest Group. trademarks properties their respective owners.
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REVISION HISTORY
Document Release 1.10 Date 08/21/02 09/09/02 Revision Initials Initial public release Fixed Diagram VT6307S Added List 6307S Updated Description Updated Figure page Fixed title Figure Figure Table Table page Updated List page Updated Description Configuration Straps, Cable Interface Signals, Serial Configuration Memory Interface, Miscellaneous, Digital Power, Analog Power Ground page
10/01/02
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TABLE CONTENTS
REVISION HISTORY TABLE CONTENTS LIST FIGURES. LIST TABLES. OVERVIEW PINOUTS DIAGRAM LIST.8 DESCRIPTIONS REGISTERS REGISTER OVERVIEW.15 Function Registers Link Controller.15 Memory-Space Registers Link Controller Registers REGISTER DESCRIPTIONS Link Controller Configuration Registers (PCI Function
Configuration Space Header Controller-Specific Configuration Registers.20 Power Management Registers.21
Link Controller Memory-Space Registers
Autonomous Resources Management Registers Control Registers.25 Self-ID Control Registers Channel Mask Registers Interrupt Registers.27 Link Control Registers.29 Control Registers Cycle Timer Registers.30 Filter Registers.31 Asynchronous Transmit Receive Context Registers Isochronous Transmit Context Registers Isochronous Receive Context Registers.35
Registers
Register Overview.37 Register Field Descriptions Register Page Port Status.38 Register Page Vendor Identification.38 Register Page Vendor-Dependent.39
FUNCTIONAL DESCRIPTIONS.40 GENERAL DESCRIPTION Cable Interface CIRCUIT DESCRIPTION Pinless Clock Generation.41 Power Down Auto Power Save Data Transmission Revision October 2002 -iiTable Contents
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Data Reception TPBIAS Bias-Detector Connect-Detector Bias-Discharger.41 Twisted-Pair Bandgap Current Generation Power Off.42 Unimplemented Ports CMC, PC0, PC1, Strapping ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS.43 CHARACTERISTICS POWER CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ANALOG SIGNAL CHARACTERISTICS TPA/TPB Driver Characteristics.45 TPA/TPB Receiver Characteristics Characteristics PACKAGE MECHANICAL SPECIFICATIONS
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LIST FIGURES
FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE FIGURE CHIP INTERNAL BLOCK DIAGRAM.3 INTERNAL BLOCK DIAGRAM VT6307 1394A CONTROLLER PQFP DIAGRAM 14X20 (TOP VIEW) VT6307L 1394A CONTROLLER LQFP DIAGRAM 14X20 (TOP VIEW) VT6307S 1394A CONTROLLER LQFP DIAGRAM 14X14 (TOP VIEW).7 CABLE INTERFACE.40 MECHANICAL SPECIFICATIONS VT6307 RECTANGULAR 128-PIN PQFP PACKAGE MECHANICAL SPECIFICATIONS VT6307L RECTANGULAR 128-PIN LQFP PACKAGE MECHANICAL SPECIFICATIONS VT6307S SQUARE 128-PIN LQFP PACKAGE
LIST TABLES
TABLE TABLE TABLE TABLE TABLE TABLE TABLE TABLE LIST VT6307/VT6307L (ALPHABETICAL ORDER) LIST VT6307S (ALPHABETICAL ORDER) DESCRIPTIONS REGISTERS.15 REGISTER MAP.18 PACKET EVENT CODES.33 REGISTER PAGE FIELD DESCRIPTIONS REGISTER PAGE FIELD DESCRIPTIONS
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VT6307
1394A INTEGRATED HOST CONTROLLER 1394A-2000 1394-1995 OHCI LINK LAYER CONTROLLER WITH INTEGRATED 2-PORT MBIT
Single Chip Host Controller IEEE 1394-1995 Release IEEE 1394a-2000 Compatible with VT6306 1394a Host Controller Embedded 1394 Link Core generator checker receive transmit data On-chip isochronous asynchronous receive transmit FIFOs packets general receive plus
isochronous transmit plus asynchronous transmit) isochronous transmit contexts isochronous receive contexts 3-deep physical post-write queue 2-deep physical response queue Dual buffer mode enhancements Skip Processing enhancements Block Read Request handling Ack_tardy processing
OHCI Compliant Programming Interface Compliant with 1394 Open Specifications v1.0 v1.1 Descriptor based isochronous asynchronous channels receive transmit packets 32-Bit Power-Managed Interface Compliant with specification v2.2 High-performance mastering support Byte alignment little-endian (x86/PCI) environment Compliant with Power Management Specification v1.1 Supports power states D3hot, D3cold Supports CardBus interface Supports EEPROM 4-Wire Serial with GUID PROM Shadow EEPROM
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Features
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Integrated Mbit 2-Port Supports provisions IEEE 1394-1995 Standard High Performance Serial 1394a-2000 Fully interoperable with IEEE 1394-1995 devices Full 1394a-2000 Support includes: Arbitrated short reset Enhanced priority arbitration Connection debounce Multispeed packet concatenation accelerated arbitration Fly-by concatenation port disable, suspend, resume, through register write remote command packet Remote access packet Boundary node short reset PHY_ID wrap past Provides 1394a fully compliant cable ports Mbit second Host notification LinkOn events Logic performs initialization arbitration functions Encode decode functions included data-strobe bit-level encoding Incoming data resynchronized local clock. 24.576 crystal oscillator provide TX/RX data 100/200/400 Mbps Link-Layer Controller clock
49.152 MHz. Cable power presence monitoring. Programmable node power class information system power management Fully Compliant 1394a-2000 register Separate TPBIAS each port Cable ports monitor line conditions active connection remote node Automatic power down inactive circuit logic power application Self power reset pinless reduce passive component counts system Automatic configuration single-port, two-port, three-port applications; unused ports power down automatically Dedicated power supply pins separate from link core protection
3.3V Power Supply with Tolerant Inputs Power CMOS Process Three Package Types Available VT6307 128-Pin PQFP (14x20 body with lead pitch) VT6307L 128-Pin LQFP (14x20 body with lead pitch) VT6307S 128-Pin LQFP (14x14 body with lead pitch) Reference Designs Schematics Available
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OVERVIEW
VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity. implements Link layers IEEE 1394-1995 High Performance Serial specification release 1394a-2000. compliant with 1394 Open with engine support high performance data transfer 32-bit master host interface. VT6307 supports 100, Mbit/sec transmission integrated 2-port PHY. VT6307 services types data packets: asynchronous isochronous (real time). 1394 link core performs arbitration requesting, packet generation checking, cycle master operations. also root node capability performs retry operations. VT6307 ready provide industry-standard IEEE 1394 peripheral connections desktop mobile platforms. Support VT6307 built into Microsoft Windows Windows Windows 2000, Windows
Host Interface
SWAP Register (Control Status Interrupt)
Overview
Tx/Rx FIFO Iso/Asy
Cycle Monitor
Generator
2-Port
Figure Chip Internal Block Diagram
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Transmitter
Checker Receiver
Cycle Timer
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XCPS LREQ CTL0 CTL1 Link Interface
Received Data Decoder Retimer Bias Voltage Current Generator
TPBIAS0 TPBIAS1
TPA0+ TPA0-
Cable Port Arbitration Control State Machine Logic TPB0+ TPB0-
Cable Port
TPA1+ TPA1TPB1+ TPB1-
PowerDown RESET# Reset logic
Transmit Data Encoder
CrystaL Oscillator, System, Clock Generator
Figure Internal Block Diagram
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Overview
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PINOUTS
AD27 AD28 AD29 AD30 AD31 REQ# GNT# PCICLK PCIRST# INTA# XTPBIAS1 XTPA1P XTPA1M XTPB1P XTPB1M XTPBIAS0 XTPA0P XTPA0M XTPB0P XTPB0M XREXT
AD26 AD25 AD24 CBE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP#
VT6307 1394a Controller
PQFP-128
Parentheses indicate alternate function
XCPS PHYRST# CARDEN I2CEN
Figure VT6307 1394a Controller PQFP Diagram 14x20 (Top View)
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PERR# CBE1# AD15 AD14 AD13 AD12 AD11 AD10 CBE0# EECS EEDO EEDI EECK PME#
Diagram
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AD27 AD28 AD29 AD30 AD31 REQ# GNT# PCICLK PCIRST# INTA# XTPBIAS1 XTPA1P XTPA1M XTPB1P XTPB1M XTPBIAS0 XTPA0P XTPA0M XTPB0P XTPB0M XREXT
AD26 AD25 AD24 CBE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP#
VT6307L 1394a Controller
LQFP-128
Parentheses indicate alternate function
XCPS PHYRST# CARDEN I2CEN
Figure VT6307L 1394a Controller LQFP Diagram 14X20 (Top View)
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PERR# CBE1# AD15 AD14 AD13 AD12 AD11 AD10 CBE0# EECS EEDO EEDI EECK PME#
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AD29 AD30 AD31 REQ# GNT# PCICLK PCIRST# INTA# XTPBIAS1 XTPA1P XTPA1M XTPB1P XTPB1M XTPBIAS0 XTPA0P XTPA0M XTPB0P XTPB0M
AD28 AD27 AD26 AD25 AD24 CBE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR#
VT6307S 1394a Controller
LQFP-128
Parentheses indicate alternate function
XREXT XCPS PHYRST# CARDEN I2CEN PME#
Figure VT6307S 1394a Controller LQFP Diagram 14x14 (Top View)
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CBE1# AD15 AD14 AD13 AD12 AD11 AD10 CBE0# EECS EEDO EEDI EECK
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List
Table List VT6307/VT6307L (Alphabetical Order)
Name AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 Name CARDEN CBE0# CBE1# CBE2# CBE3# DEVSEL# EECS EEDI/SCL EEDI/SDA EEDO FRAME# GNT# Name I2CEN IDSEL INTA# IRDY# PCICLK PCIRST# PERR# PHYRST# PME# Name REQ# STOP# TRDY# XCPS XREXT XTPA0M XTPA0P XTPA1M XTPA1P XTPB0M XTPB0P XTPB1M XTPB1P XTPBIAS0 XTPBIAS1
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Table List VT6307S (Alphabetical Order)
Name AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
Name CARDEN CBE0# CBE1# CBE2# CBE3# DEVSEL# EECK/SCL EECS EEDI/SDA EEDO FRAME# GNT#
Name I2CEN IDSEL INTA# IRDY# PCICLK PCIRST# PERR# PHYRST# PME#
Name REQ# STOP# TRDY# XCPS XREXT XTPA0M XTPA0P XTPA1M XTPA1P XTPB0M XTPB0P XTPB1M XTPB1P XTPBIAS0 XTPBIAS1
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Descriptions
Table Descriptions
Interface
Signal Name AD[31:0] VT6307/L 97-101, 104106, 109-110, 112, 116-120, 57,10-14, 1719, 21-23, 27-28 107, 122, VT6307S Pin# 94-98, 101103, 106107, 109, 113-117, 7-11, 1416, 18-20, 24-25 104, 119, Signal Description Address Data Bus. standard address data lines. address driven with FRAME# assertion data driven received following cycles.
CBE[3:0]#
FRAME#
DEVSEL#
TRDY# IRDY# PREQ# PGNT# IDSEL INTA# PCICLK PCIRST#
PERR# STOP#
Command Byte Enable. command driven with FRAME# assertion. Byte enables corresponding supplied requested data driven following clocks. Frame. Assertion indicates address phase transfer. Negation indicates that more data transfer desired cycle initiator. Device Select. output, this signal asserted claim transactions through positive subtractive decoding. input, DEVSEL# indicates response VT6306-initiated transaction also sampled when decoding whether subtractively decode cycle. Target Ready. Asserted when target ready data transfer. Initiator Ready. Asserted when initiator ready data transfer. Request. Asserted master indicate arbiter that wants bus. Grant. Asserted indicate that access granted. Initialization Device Select. IDSEL used chip select during configuration read write cycles. Interrupt. asynchronous signal used request interrupt. Clock. Timing reference transactions Bus. Reset. When detected low, internal hardware reset performed. PCIRST# assertion deassertion asynchronous PCLK, however, recommended that deassertion synchronous guarantee clean bounce free edge. Parity. single parity provided over AD[31:0] C/BE[3:0]#. Parity Error. Parity error asserted when data parity error detected. Stop. Asserted target request master stop current transaction.
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1394 Interface
Signal Name PHYRST#
VT6307/L
VT6307S Pin#
Signal Description Reset. Used reset logic. This left unconnected there internal network that creates power-on reset interval. This also driven open-drain type driver.
Configuration Straps
Signal Name I2CEN VT6307/L VT6307S Pin# Default Signal Description Enable. Default 4-wire EEPROM interface Pull high digital power will enable 2-wire EEPROM interface using SCL/SDA CardBus Enable. Default mode. Pull high digital power will enable CardBus mode.
CARDBUSENA
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Cable Interface Signals
Signal Name XTPA0P XTPA0M XTPB0P XTPB0M XTPA1P XTPA1M XTPB1P XTPB1M XTPBIAS0 XTPBIAS1
VT6307/L
VT6307S Pin#
Signal Description Port Twisted Pair Positive. Port Twisted Pair Negative. Port Twisted Pair Positive. Port Twisted Pair Negative. Port Twisted Pair Positive. Port Twisted Pair Negative. Port Twisted Pair Positive. Port Twisted Pair Negative. Port Twisted Pair Bias Voltages. Provides 1.85V (typical) nominal bias proper operation twisted-pair cable drivers receivers, signaling remote nodes that cable connections active. High-impedance during chip reset power down. disabled remote packets software. Each these pins must decoupled with 0.33-uF capacitor ground. Cable Power Status. This normally connected cable power through voltage divider. internal comparator used detect presence cable power. External Resistor. 6.34K resistor ground required internal current source operation. Crystal Input. These pins must connected 24.576 parallel resonant fundamental mode crystal. Crystal Output.
XCPS
XREXT
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Serial Configuration Memory Interface
Signal Name EECS
VT6307/L
VT6307S Pin#
Signal Description EEPROM Chip Select. Chip select external serial EEPROM when used provide configuration data. Pull high EEPROM auto loading digital power will disable. EEPROM Data Out. EEPROM Data Data. EEPROM Clock Clock.
EEDO EEDI EECK
Miscellaneous
Signal Name PME# VT6307/L 51-57, 8488 VT6307S Pin# 4854, 81-85 Signal Description Power Management Event. Reserved.
Digital Power
Signal Name VT6307/L 35,102, 113, 114, VT6307S Pin# 110, 111, Signal Description Power. 3.3V ±0.3V.
Analog Power
Signal Name VT6307/L VT6307S Pin# Signal Description PHY. Digital Power. 3.3V ±0.3V. PHY. Analog Power 1394 Receive Channel 3.3V ±0.3V.
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Ground
Signal Name
VT6307/L
VT6307S Pin#
Signal Description
Ground. 100, 108, 94,103, 112, 118, 111, 115, Note combination high frequency decoupling capacitors suggested analog power ground pairs. Note grounds should connected primary circuit board ground plane (i.e., lowest impedance point available). Note VCCRAM should connected power plane.
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Table Registers
Function Registers Link Controller
REGISTERS
Register Overview
Configuration Space Header Registers following tables summarize configuration registers VT6307. These tables also document power-on default value ("Default") access type ("Acc") each register. Access type definitions used (Read/Write), (Read/Only), reserved used (essentially same RO), just (Read Write Clear individual bits). Registers indicated have some read/only bits that always read back fixed value (usually unused); registers designated have some read-only read write bits (see individual register descriptions details). Detailed register descriptions provided following section this document. offset default values shown hexadecimal unless otherwise indicated Offset 13-10 17-14 1B-18 1C-27 28-2B 2F-2C 30-33 35-3B Configuration Space Header Vendor Device Command Status Revision Programming Interface Class Code Base Class Code -reserved- (cache line size) Latency Timer Header Type -reserved- (Built Self Test) OHCI MMIO Base Address Base Address Base Address (PCI Mode) Base Address (Cardbus Mode) -reserved- (base address registers) Pointer (PCI Mode) Pointer (Cardbus Mode) Subsystem Read -reserved- (expan. base addr) Capabilities Pointer -reserved- (unassigned) Interrupt Line Interrupt Minimum Grant Maximum Latency Default 1106 3044 0000 0280 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0083 Nnnn nnnn
Controller-Specific Configuration Registers Offset Configuration Registers 43-40 Control 44-4F -reservedPower Management Registers Offset 53-52 55-54 58-FF Power Management Register Block Power Management Capabilities Next Pointer Power Management Capabilities Power Management Power Management Power Management Data -reservedDefault E002 0000 Default 0000 0000
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Register Overview
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Default 0001 0000 0001 0010 0000 0000 0000 0000 0000 0000 0000 0000 8000 0000 0000 0000 3133 3934 F000 0002 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Offset B3-B0 B7-B4 BB-B8 BC-DB F4-FF 120-123 124-17F Heading Initial Bandwidth Available Initial Channels Available Initial Channels Available -reservedFairness Control Link Control Link Control Clear Node Control Isochronous Cycle Timer -reservedAsync Request Filter High Async Request Filter High Clear Async Request Filter Async Request Filter Clear Physical Request Filter High Physical Request Filter High Clear Physical Request Filter Physical Request Filter Clear Physical Upper Bound -reservedAsync Request Xmit Context Async Request Xmit Context Async Request Xmit Command Async Response Xmit Context Async Response Xmit Context Async Response Xmit Async Request Context Async Request Context Async Request Command Async Response Context Async Response Context Async Response Command Default 0000 1333 FFFFFFFF FFFFFFFF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Memory-Space Registers Link Controller Offset Heading Version (OHCI Mode) Version (OHCI Mode) -reserved- (GUID ROM) Asynchronous Transmit Retries Data Compare Data Control Configuration Header 1394 1394 Options Global Unique High Global Unique 2C-33 -reserved34 Configuration Posted Write Address Posted Write Address High Vendor 44-4F -reserved50 Control Control Clear 58-5F -reserved60-63 -reserved64 Self-ID Buffer Pointer Self-ID Count 6C-6F -reserved70 Isoch Channel Mask High Isoch Channel Mask High Isoch Channel Mask Isoch Channel Mask Interrupt Event Interrupt Event Clear Interrupt Mask Interrupt Mask Clear Isoch Xmit Interrupt Event Isoch Xmit Interrupt Event Clear Isoch Xmit Interrupt Mask Isoch Xmit Interrupt Mask Clear Isoch Interrupt Event Isoch Interrupt Event Clear Isoch Interrupt Mask Isoch Interrupt Mask Clear
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Register Overview
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Default 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Offset 480-7FF Heading Isoch Context Isoch Context Isoch Context Command Isoch Context Match Isoch Context Isoch Context Isoch Context Command Isoch Context Match Isoch Context Isoch Context Isoch Context Command Isoch Context Match Isoch Context Isoch Context Isoch Context Command Isoch Context Match -reservedDefault 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Offset 280-3FF
Heading Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context Isoch Xmit Context -reserved-
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Register Overview
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Registers
Table Register
Offset 0000b Physical 0001b Count 0010b Total Ports always 111b 0011b Delay Speed 0100b Power Class Jitter Cont 0101b Multi Accel Tout Loop ISBR 0110b -reserved0111b Port Select Page Select 1000b Register (Page Select) 1001b Register (Page Select) 1010b Register (Page Select) 1011b Register (Page Select) 1100b Register (Page Select) 1101b Register (Page Select) 1110b Register (Page Select) 1111b Register (Page Select) Physical Address This Node Root Node Cable Power Status Root Hold-Off Initiate Reset Count Time Optimization Total Ports Speed Supports 98.304, 196.608, 393.216 Mbit/s Delay Worst Case Repeater Delay Link Control Cont Contender Jitter Repeater Delay Variation Watchdog Timer Enable ISBR Initiate Short (Arbitrated) Reset Loop Loop Detect Cable Power Fail Detect Tout Arbitration State Machine Timeout Port Event Detect Accel Arbitration Acceleration Enable Multi Multispeed Packet Concatenation Enable
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Register Overview
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Register Descriptions
Link Controller Configuration Registers (PCI Function 1394 host controller interface follows Open (OHCI) interface specification. There sets software accessible registers: configuration registers memory registers. configuration registers located function configuration space. memory registers located system memory space offsets from address stored Base Address Register. Configuration Space Header Offset Vendor Vendor (1106h Technologies) Offset Device Device (3044h VT6307 1394a Controller) Offset Command 15-10 Reserved always reads Fast Back-to-Back Enable fixed (disabled) SERR# Enable fixed (disabled) Wait Cycle Control fixed (disabled) Parity Error Response fixed (disabled) Palette Snoop fixed (disabled) Postable Memory Write Enablefixed (disabled) Special Cycle Enable fixed (disabled) Master Enable Disable. default Enable Memory Space Enable Disable. default Enable Access 1394 Memory Registers Space Enable fixed (disabled) Offset Status. Detected Parity Error.always reads Signaled System Error .always reads Received Master Abort Master Abort Generated.default Master Abort Generated 1394 Controller. 1394 interface logic generates master abort while acting master. This cleared software writing this position. Received Target Abort Target Abort Received .default Target Abort Received 1394 Controller. 1394 interface logic receives target abort while acting master. This cleared software writing this position. Signaled Target Abort.always reads 10-9 DEVSEL# Timing Fast Medium.fixed Slow Reserved Data Parity Error Detected .always reads Fast Back-to-Back Capable .always reads User Definable Features .always reads Capable .always reads Reserved .always reads Offset Revision (nnh) Silicon Revision Code indicates first silicon) Offset Programming Interface (10h=OHCI) Offset Class Code (00h=1394 Serial Bus) Offset Base Class Code (0Ch=Serial Controller) Offset Latency Timer (00h) Latency Timer Count burst cycles generated VT6307 last indefinitely long GNT# remains active. GNT# negated after burst initiated, VT6307 limits duration burst number clocks specified this field. Reserved .always reads Offset Header Type (00h)
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Register Descriptions
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Controller-Specific Configuration Registers Offset 43-40 -PCI Control insert definitions here
Offset 13-10 OHCI MMIO Base (0000 0000h). 31-11 Base Address (2048-Byte Space) default 10-4 Reserved always reads Prefetechable always reads Reads indicate that register space prefetchable. Type always reads Reads indicate that register space located anywhere 32-bit memory address space. Resource Type always reads Reads indicate request memory space. Offset 17-14 Base Address (0000 0001h) 31-7 Base Address (128-Byte Space) default Reserved always reads Prefetechable always reads Reads indicate that register space prefetchable. Type always reads Reads indicate that register space located anywhere 16-bit address space. Resource Type always reads Reads indicate request space. Offset 1B-18 Base (0000 0000h) (PCI Mode) (Cardbus Mode) 31-8 Base Address (256-Byte Space) default Reserved always reads Prefetechable always reads Reads indicate that register space prefetchable. Type always reads Reads indicate that register space located anywhere 32-bit memory address space. Resource Type always reads Reads indicate request memory space. Offset 2B-28 Pointer 31-0 Pointer (PCI Mode) reads 0000 0000h Pointer (Cardbus Mode) reads 0000 0083h Offset Capabilities Pointer (50h). Offset Interrupt Line (00h). Offset Interrupt (01h=Drives INTA#).
Offset Minimum Grant (00h). Offset Maximum Latency (20h)
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Register Descriptions
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Power Management Registers Offset Capabilities (01h) Capabilities always reads Always reads indicate that this list item Power Management Register Block Offset Next Item Pointer (00h) Next Item Pointer always reads Always reads indicate that there additional items Capabilities List. Offset 53-52 Power Management Capabilities (E002) PME# Asserted From D3cold capable Capable.always reads PME# Asserted From D3hot capable Capable.always reads PME# Asserted From capable Capable.always reads PME# Asserted From capable always reads Capable PME# Asserted From capable always reads Capable Power Management State Supported supported always reads Supported Power Management State Supported supported always reads Supported 3.3V Auxiliary Current Required None (device self powered) always reads Device-Specific Initialization Required required always reads Required Reserved always reads Clock clock required always reads clock required PME# generation Specification Version always reads 010b Reads 010b indicate that this function complies with Revision Power Management Interface Specification Offset 55-54 Mgmt Control Status (PMCSR) Status .RWC This when function would normally assert PME# signal independent state PME_Enable bit. Writing will clear this cause function stop asserting PME# enabled). 14-13 Data Scale Scaling factor when interpreting value Data register.always reads 12-9 Data Select Used select which data reported through Data register Data_Scale field.default Enable PME# assertion disabled.default PME# assertion enabled Reserved .always reads Power State These bits indicate current power state used change power state. attempt made write code corresponding unsupported state, write these bits ignored state change occurs. D3hot Offset Mgmt Bridge Support Extensions Power Clock Control Enable.always reads B2/B3 Support D3hot .always reads Reserved .always reads Offset Power Management Data.RO Data Used report state-dependent data requested Data Select field PMCSR register (scaled Data Scale field).
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Register Descriptions
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VT6307 1394a Host Controller
Memory Offset Asynchronous Transmit Retries 31-29 Second Limit Count Seconds (modulo These bits Cycle Limit bits below define time limit retry attempts when outbound dual-phase retry protocol use. 28-16 Cycle Limit Count Cycles (modulo 8000). These bits Second Limit bits above define time limit retry attempts when outbound dual-phase retry protocol use. 15-12 Reserved .always reads 11-8 Physical Response Retries .default Specifies many times attempt retry transmit operation physical response packet when "busy" "ack_type_error" acknowledge received from target node. This value used only responses physical requests. Response Retries .default Specifies Asynchronous Transmit Response subsystem many times attempt retry transmit operation response packet when "busy" "ack_type_error" acknowledge received from target node. This value used only responses sent software Asynchronous Transmit Response context. Request Retries .default Specifies Asynchronous Transmit Request subsystem many times attempt retry transmit operation packet when "busy" "ack_type_error" acknowledge received from target node. This value used only responses sent software Asynchronous Transmit Request context.
Link Controller Memory-Space Registers These registers occupy 2048-byte space system memory (offsets 0-7FFh). This address space begins address contained 1394 Configuration Space "Base Address Register" (Function Configuration Space Offset 10h). registers must accessed 32-bit words 32-bit boundaries. Writes reserved addresses have undefined results reads from reserved addresses return indeterminate data. Unless specified otherwise, register fields default unchanged after 1394 reset. Some registers designated Clear registers. These registers pairs, where read either address will return current contents register. Data written register address assumed mask where bits determine which bits should set. Data written Clear register address assumed mask where bits determine which bits should cleared. Memory Offset Version. 31-0 Version OHCI Mode .reads 0001 0000 Version OHCI Mode .reads 0001 0010
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Memory Offset Data 31-0 Data .default undefined Data stored comparison successful. Memory Offset Compare Data 31-0 Compare Data .default undefined Data compared with existing value resource. Memory Offset Control Done .default when compare-swap operation completed. Reset whenever this register written. 30-2 Reserved .always reads Resource Select .default undefined Manager Bandwidth Available Channels Available Channels Available Memory Offset Configuration Header. 31-24 Info Block Length.default Length Information Block doublewords 23-16 Length .default Length block protected value indicates that only protects configuration header). 15-0 Value Default value loaded from GUID present (default undefined GUID present). Must prior setting Control" register "Link Enable" bit.
Autonomous Resources VT6307 implements 1394 "Compare-and-Swap" management registers, Configuration Header, "Bus Info Block". also allows access first bytes configuration ROM. Atomic compare-and-swap transactions, when accessed from 1394 bus, autonomous without software intervention. access these management resource registers bus, software first loads Data register with data value loaded, then loads Compare register with expected value. Finally, writes Control register with selected value resource. This initiates compare-and-swap operation. When complete, Control register "done" will Data register will contain value selected resource prior host-initiated compare-and-swap operation. Management Registers 1394 requires certain 1394 management resource registers accessible only 32-bit read 32-bit lock (compareand-swap) transactions. These special management resource registers implemented on-chip: Address Select Register Name FFFF F000 021C Manager FFFF F000 0220 Bandwidth Available FFFF F000 0224 Channels Available FFFF F000 0228 Channels Available Hardware Reset 0000 003F 0000 1333 FFFF FFFF FFFF FFFF
Address FFFF F000 021C Manager 31-6 Reserved always reads Manager default Address FFFF F000 0220 Bandwidth Available 31-13 Reserved always reads 12-0 Bandwidth Available. default 1333h Address FFFF F000 0224 Channels Avail Reserved always reads Address FFFF F000 0228 Channels Avail Reserved always reads
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Memory Offset Global Unique High. This register maps 32-bit word info block. Contents cleared hardware reset affected software reset. Read/Write Rx44[0] cleared, Read/Only Rx44[0] set. 31-8 Node Vendor .default 1394 Management Field. Must prior setting Control" register "link enable" bit. Chip High.default 1394 Management Field. Must prior setting Control" register "link enable" bit. Memory Offset Global Unique Low. This register maps 32-bit word info block. Contents cleared hardware reset affected software reset. Read/Write Rx44[0] cleared, Read/Only Rx44[0] set. 31-0 Chip Low.default 1394 Management Field. Must prior setting Control" register "link enable" bit.
Memory Offset 1394 This register maps 32-bit word info block. 31-0 ID.always reads 31333934h (ASCII "1394") Memory Offset 1394 Options This register maps quadword info block. Isochronous Resource Manager Capable capable Capable. default Cycle Master Capable capable Capable. default Isochronous Capable capable Capable. default Manager Capable capable Capable. default Power Management Capable capable default Capable 26-24 Reserved always reads 23-16 Cycle Clock 1394 Management Field. This field must written with valid data prior setting Control" register "link enable" bit. 15-12 Received Block Write Request Packet Length 1394 Management Field. This field must written with valid data prior setting Control" register "link enable" bit. Received block write request packets with length greater than value contained this field generate "ack_type_error". 11-8 Reserved always reads Configuration Changed Since Last Reset Configuration changed default Configuration changed Reserved always reads Link Speed. default
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Control Registers following registers "set clear" register pair. Writing "Set" register address sets selected bits control register where written value Writing "Clear" register address clears selected bits control register where written value Reading from either address returns contents control register. Memory Offset (Set), (Clear) Control 31-20 Reserved .always reads Link Power Status Prohibit Link Communications .def Permit Link Communications (link LREQs perform reads writes). This effect "Link status node (see Link Enable status below). Both software hardware resets clear this bit. Posted Write Enable .default undefined writes return "ack_pending" Enable 2-deep posted write queue Software should only change this when "Link Enable" Link Enable Disable packets from being transmitted, received, processed.default Enable packets transmitted, received, processed Both software hardware resets clear this bit. Software should this until Configuration mapping register valid. Soft Reset When set, on-chip 1394 states reset, FIFOs flushed, registers their hardware reset (default) values unless otherwise specified. configuration registers affected. Hardware clears this automatically when reset complete reads while reset progress). 15-0 Reserved .always reads
Memory Offset Configuration This register contains start address within memory space that maps start address 1394 configuration ROM. Only 32-bit word reads first bytes configuration will memory space.(all other transactions this space will rejected with "ack_type_error"). system address configuration must start 1K-byte boundary. first five 32-bit words configuration space mapped configuration header Info Block, first five registers addressed this register used. This register must valid address prior setting Control" register "link enable" bit. 31-10 Configuration Address. default Read requests 1394 offsets FFFF F000 0400 through FFFF F000 03FC have low-order bits offset added this register determine host memory address returned data value. Reserved always reads Memory Offset Posted Write Address 31-0 Offset default undefined "Posted Write Error" Interrupt Events register, this "Posted Write Address High" register contain bits 1394 destination offset write request that resulted error. Memory Offset Posted Write Address High. 31-16 Source default undefined Number Node Number node which issued failed write request. 15-0 Offset High default undefined "Posted Write Error" Interrupt Events register, this "Posted Write Address Low" register contain bits 1394 destination offset write request that resulted error. Memory Offset Vendor 31-0 Vendor always reads
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Channel Mask Registers Offset (Set), (Clear) Channel Mask 31-0 Channel Mask N+32 .default 0000 Bits 31-0 correspond channel numbers 63-32. Writing bits offset enables corresponding channels receiving isochronous data. Writing bits offset disables corresponding channels from receiving isochronous data. Offset (Set), (Clear) Channel Mask 31-0 Channel Mask N+32 .default 0000 Bits 31-0 correspond channel numbers 31-0. Writing bits offset enables corresponding channels receiving isochronous data. Writing bits offset disables corresponding channels from receiving isochronous data.
Self-ID Control Registers Memory Offset Self Buffer Pointer 31-11 Self-ID Buffer Pointer. default undefined Contains base address 2K-byte buffer host memory where received Self-ID packets stored. 10-0 Reserved always reads Memory Offset Self Count. Self-ID Error default undefined Self-ID packet received with errors (this automatically cleared after error-free reception Self-ID packet) Error detected during most recent Self-ID packet reception (the contents Self-ID Buffer undefined this case) 30-24 Reserved always reads 23-16 Self-ID Generation default undefined value this field incremented automatically each time Self-ID reception process begins. value rolls over after reaching 255. 15-13 Reserved always reads 12-2 Self-ID Size default undefined Contains length 32-bit words Self-ID data that been received. This field cleared 1394 reset. Reserved always reads
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Interrupt Registers Memory Offset (Set), (Clear) Interrupt Events 31-27 Reserved always reads Register Data Received register data byte received (data byte sent when register received) Cycle Long More than usec (but more than usec) elapsed between start sending cycle start packet subaction gap. Unrecoverable Error Error encountered that forced chip stop operations subunits (e.g., when context sets "ContextControl.Dead" bit) Cycle Inconsistent Cycle start received with cycle count different from value "Cycle Timer" register Cycle Lost Expected cycle start received (cycle start received immediately after first subaction after "Cycle Sync" event arbitration reset detected after "Cycle Sync" event without intervening cycle start). Cycle Seconds Interrupt "Cycle Seconds Counter" changed. Cycle Synch Interrupt isochronous cycle started (least significant cycle count toggled). Requested Interrupt requested interrupt using status transfer. Reserved always reads Reset Entered entered reset mode. Self-ID Complete Self-ID packet stream received. 15-10 Reserved always reads Lock Response Error Lock response sent serial register response lock request "ack_complete" received. Posted Write Error host error occurred while chip trying write 1394 write request (which already been given "ack_complete") into system memory.
Isochronous ReceiveDMA Complete more Isochronous receive contexts have generated interrupt (one more bits have been "Isochronous Receive Interrupt Event" register masked "Isochronous Receive Interrupt Mask" register). Isochronous Transmit Complete more Isochronous transmit contexts have generated interrupt (one more bits have been "Isochronous Transmit Interrupt Event" register masked "Isochronous Transmit Interrupt Mask" register). Response Packet Sent packet sent asynchronous receive response context buffer. Receive Packet Sent packet sent asynchronous receive request context buffer. Async Receive Response Complete Conditionally upon completion ARDMA Response context command descriptor. Async Receive Request Complete Conditionally upon completion ARDMA Request context command descriptor. Async Response Transmit Complete Conditionally upon completion ATDMA Response command. Async Request Transmit Complete Conditionally upon completion ATDMA Request command.
Memory Offset (Set), (Clear) Interrupt Mask. bits this register (except Master Interrupt Enable bit-31) correspond bits Interrupt Event register above. Zeros these bits prevent corresponding interrupt condition from generating interrupt. Bits mask register writing bits "Set" address cleared writing bits "Clear" address. current value mask bits read from either address. Master Interrupt Enable Disable Interrupt Events.default Generate interrupts mask bits 0-26 30-27 Reserved .always reads 26-0 Interrupt Mask .default undefined (see Interrupt Event register)
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Offset B3-B0 Initial Bandwidth Available 31-13 Reserved .always reads 12-0 Initial Bandwidth Available.default 1333h
Offset (Set), (Clear) Xmit Interrupt Events 31-8 Reserved always reads Isochronous Transmit Context default undefined interrupt generated isochronous transmit context "Output Last DMA" command completes bits "interrupt always". Software clears bits this register writing bits "Clear" address. Bits this register will only corresponding bits mask register one. Offset (Set), (Clear) Xmit Interrupt Mask 31-8 Reserved always reads Transmit Context Mask. default undefined Setting bits this register enables interrupts generated corresponding isochronous transmit context
Offset B7-B4 Initial Channels Available High. 31-0 Initial Channels Available. default FFFF FFFFh Offset BB-B8 Initial Channels Available Low. 31-0 Initial Channels Available. default FFFF FFFFh
Offset (Set), (Clear) Interrupt Events 31-4 Reserved always reads Isochronous Receive Context default undefined interrupt generated isochronous receive context "Input Last DMA" command completes bits "interrupt always". Software clears bits this register writing bits "Clear" address. Bits this register will only corresponding bits mask register one. Offset (Set), (Clear) Interrupt Mask. 31-4 Reserved always reads Receive Context Mask. default undefined Setting bits this register enables interrupts generated corresponding isochronous receive context
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Link Control Registers Memory Offset Fairness Control. 31-8 Reserved always reads Requests Fairness Interval default number request packets allowed transmitted fairness interval Memory Offset Node This register contains address node which this chip resides. 16-bit combination Number Node Number fields referred "Node ID". Node Number field updated when register sent from PHY. This happen either because software requested read from through Control register because sending register (most likely reset). Valid valid node number (cleared reset) Valid node number received from Root This during reset Attached root.def Attached root 29-28 Reserved .always reads Cable Power Status reports cable power status OK.def reports cable power status 26-16 Reserved .always reads 15-6 Number default ones Used identify specific 1394 which this node belongs when multiple 1394-compatible buses connected bridge (set 3FFh reset) Node Number .default physical node number established during self-identification automatically value received from after selfidentification phase. sets this field (all ones), link-level transmits disabled.
Memory Offset (Set), (Clear) Link Control This register contains control flags that enable configure link core protocol portions chip. contains controls receiver cycle timer. 31-22 Reserved always reads Cycle Master. default undefined Received cycle start packets will accepted maintain synchronization with node that sending them. sent notification that root, cycle start packet will generated every time cycle timer rolls over, based setting "Cycle Source" bit. This cleared automatically "Cycle Long" interrupt event occurs cannot until "Cycle Long" interrupt event cleared. Cycle Timer Enable. default undefined Cycle timer offset will count Cycle Timer offset will count cycles 24.576 clock roll over appropriate time based settings above bits 19-11 Reserved always reads Receive Packet. default packets received outside selfID phase ignored receiver will accept incoming packets into request context request context enabled. This does control receipt self-ID packets. Receive Self-ID default self-ID packets ignored receiver will accept incoming selfidentification packets. Before setting this bit, software must ensure that self-ID buffer pointer register contains valid address. Reserved always reads
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Cycle Timer Registers Memory Offset Isochronous Cycle Timer This register shows current cycle number offset. When chip cycle master, this register transmitted with cycle start message. When cycle master, this register loaded with data field incoming cycle start. event that cycle start message received, fields continue incrementing their (when "Cycle Timer Enable" field "Link Control" register) maintain local time reference. 31-25 Cycle Seconds .default This field counts seconds ("Cycle Count" rollovers) modulo 128. 24-12 Cycle Count .default This field counts cycles ("Cycle Offset" rollovers) modulo 8000. 11-0 Cycle Offset .default This field counts 24.576 clocks modulo 3072 (125 usec).
Control Registers Memory Offset Control. This register used read write register. read write, address register written into Register Address field. reads "Read Register" (when request been sent PHY, "Read Register" cleared automatically chip). When transmitting request, first clock LREQ register read/write portion will bit-11 this register followed bit-10, etc, finishing with bit-8 register reads bit-0 register writes. When returns register through status transfer, "Read Done" set. address register received placed "Read Address" field contents "Read Data" field. first bits data received status transfer register placed bits (D[0]) (D[1]) this register. writes, value write written "Write Data" field "Write Register" set. "Write Register" cleared automatically chip when write request been sent PHY. Read Done Indicates that read request been completed valid information contained Read Data Read Address fields. Cleared when "Read Register" set. chip when register transfer received from PHY. Reserved always reads Read Address address register most recently received from PHY. Read Data contents register most recently received from Read Register Used initiate read request from register (must same time "Write Register" bit). Cleared chip when request been sent. Write Register Used initiate write request register (must same time "Read Register" bit). Cleared chip when request been sent. Reserved always reads Register Address address register read written Write Data data written (ignored reads)
30-28 27-24
23-16
13-12 11-8
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Filter Registers Offset (Set), (Clear) Async Filter High Async Request Resources Buses Asynchronous requests received from nonlocal nodes will accepted only which corresponds node number (see remaining bits this register "Async Request Filter Low" register). default asynchronous requests received from nonlocal nodes will accepted. reset does affect value this bit. 30-0 Async Request Resource default local node number N+32, asynchronous requests received from that node number will accepted. number corresponds node number reset sets bits this field Offset (Set), (Clear) Physical Filter HighRW Physical Request Resources Buses Asynchronous physical requests received from non-local nodes will accepted only which corresponds node number (see remaining bits this register "Physical Request Filter Low" register). default asynchronous physical requests received from non-local nodes will accepted. reset does affect value this bit. 30-0 Physical Request Resource "N".default local node number N+32, asynchronous physical requests received from that node number will accepted. number corresponds node number reset sets bits this field
Offset (Set), (Clear) Async Filter 31-0 Async Request Resource default local node number asynchronous requests received from that node number will accepted. number corresponds node number. reset sets bits this field
Offset (Set), (Clear) Physical Filter LowRW 31-0 Physical Request Resource "N".default local node number asynchronous physical requests received from that node number will accepted. number corresponds node number. reset sets bits this field
Offset Physical Upper Bound. 31-0 Physical Upper Bound.default
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however, value non-zero, chip will continue processing. wake while chip active value non-zero, takes special action. chip will clear this before reads rereads descriptor. wake should while zero. Dead .default This chip indicate fatal error processing descriptor. When set, active cleared. This cleared when software clears hardware software reset. Active .default This chip when software sets sets wake while set. chip will clear this bit: when branch indicated descriptor value branch address when software clears chip reached safe stopping point while dead after hardware software reset asynchronous transmit contexts (request response), when reset occurs When this chip will Interrupt Event context. Reserved .always reads Speed (Async Receive Contexts Only) This field indicates speed which packet received transmitted: Mbits/sec Mbits/sec Mbits/sec -reserved1xx -reservedAck Code .default Following "Output Last" command, received "Ack Code" "Event Error Code" indicated this field. Possible values are: "Ack Complete", "Ack Pending", Busy "Ack Data Error", "Ack Type Error", "Event Tcode Error", "Event Missing Ack", "Event Underrun", "Event Descriptor Read", "Event Data Read", "Event Timeout", "Event Flushed", "Event Unknown" (see "Table Packet Event Codes" following page descriptions values these codes).
Asynchronous Transmit Receive Context Registers Offset (Set), (Clr) Async Xmit Context Offset (Set), (Clr) Async Xmit Context. Offset (Set), (Clr) Async Context Offset (Set), (Clr) Async Context. These registers Context Control registers Asynchronous Transmit Requests Responses Asynchronous Receive Requests Responses, respectively. They contain bits control options, operational state, status context. layout both registers given below: 31-16 Reserved always reads This cleared software enable descriptor processing context. chip will clear this automatically hardware software reset. Before software sets this bit, active must clear Command Pointer register context must contain valid descriptor block address value that appropriate descriptor block address. Software stop chip from further processing context clearing this bit. When cleared, chip will stop processing context manner that will impact operation other context controller. This require significant amount time. software clears isochronous context while chip processing packet context, will continue receive transmit packet update descriptor status. will then stop conclusion that packet. cleared non-isochronous context, chip will stop processing convenient point descriptors consistent state (e.g., status updated packet sent acknowledged). Clearing have other side effects that controller dependent. This described sections that cover each controllers. 14-13 Reserved always reads Wake default When software adds list descriptors context, chip have already read descriptor that list before updated. This provides semaphore indicate that list have changed. chip fetched descriptor indicated branch address value zero, will reread pointer value when wake set. reread, value still zero, then list been reached chip will clear active bit.
Offset Async Xmit Context Command Ptr. Offset Async Xmit Context Command Offset Async Context Command Ptr. Offset Async Context Command
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Table Packet Event Codes
Code Name 00/10 Event Tcode Error 01/11 Event Short Packet 02/12 Event Long Packet 03/13 Event Missing 04/14 Event Underrun 05/15 Event Overrun 06/16 Event Descriptor Read 07/17 Event Data Read 08/18 Event Data Write 09/19 0A/1A Event Reset Event Timeout
Meaning Tcode associated with this packet. packet flushed.
Event Tcode Error 0CReserved 0D/1B 0E/1E Event Unknown error condition occurred that cannot represented other defined event codes 0F/1F Sent link side output FIFO when asynchronous packets being flushed Event Flushed reset destination node successfully accepted packet. packet request Complete subaction, destination node successfully completed transaction response subaction shall follow. code transmitted PHY, isochronous broadcast packets, none which yield code, will hardware "Ack Complete" unless "Event Underrun" "Event Data Read" occurs. destination node successfully accepted packet. packet request Pending subaction, response subaction will follow later time. This code returned response subaction. Reserved packet could accepted after "ATretries" attempts last Busy received "Ack Busy packet could accepted after "ATretries" attempts last Busy received "Ack Busy OHCI does support dual phase retry protocol transmitted packets, this should received. packet could accepted after "ATretries" attempts last Busy received "Ack Busy (see note "Ack Busy A"). 17-1C Reserved destination node could accept block packet because data field failed Data Error check because length data block payload match length contained "Data Length" field. This code returned packet that does have data block payload. Returned when received block write request received block read request greater Type Error than "max_rec" Reserved
received data length less than packet's data length packet-per-buffer mode only). received data length greater than packet's data length packet-per-buffer mode only). subaction detected before arrived underrun occurred corresponding FIFO packet truncated. receive FIFO overflowed during reception isochronous packet. unrecoverable error occurred while Host Controller reading descriptor block. error occurred while Host Controller attempting read from host memory data stage descriptor processing. error occurred while Host Controller attempting write host memory data stage descriptor processing. Identifies packet receive buffer being synthesized reset packet Indicates that asynchronous transmit response packet expired transmitted Tcode associated with this packet. packet flushed.
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Wake .default When software adds list descriptors context, chip have already read descriptor that list before updated. This provides semaphore indicate that list have changed. chip fetched descriptor indicated branch address value zero, will reread pointer value when wake set. reread, value still zero, then list been reached chip will clear active bit. however, value non-zero, chip will continue processing. wake while chip active value non-zero, takes special action. chip will clear this before reads rereads descriptor. wake should while zero. Dead .default This chip indicate fatal error processing descriptor. When set, active cleared. This cleared when software clears hardware software reset. Active .default This chip when software sets sets wake while set. chip will clear this bit: when branch indicated descriptor value branch address when software clears chip reached safe stopping point while dead after hardware software reset When this cleared clear, chip will Interrupt Event context. Reserved .always reads Code .default Following "Output Last" command, received "Ack Code" "Event Error Code" indicated this field. Possible values are: "Ack Complete", "Ack Pending", Busy "Ack Data Error", "Ack Type Error", "Event Tcode Error", "Event Missing Ack", "Event Underrun", "Event Descriptor Read", "Event Data Read", "Event Timeout", "Event Flushed", "Event Unknown" (see "Table Packet Event Codes" previous page descriptions values these codes).
Isochronous Transmit Context Registers Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context Offset (Set), (Clr) Isoch Xmit Context These registers Context Control registers isochronous Transmit Contexts 0-7. Each context consists registers: Command Pointer Context Control register. Command Pointer used software tell controller where context program begins. Context Control register controls context's behavior indicates current status. layout Context Control registers given below: 31-30 Reserved always reads Cycle Match Enable general, when context will begin running only when 13-bit "Cycle Match" field matches 13-bit "Cycle Count" Cycle Start packet. effects this however impacted values other bits this register. Once context becomes active, this cleared automatically chip. 28-16 Cycle Match Contains 13-bit value corresponding 13-bit "Cycle Count" field. "Cycle Match Enable" set, this ITDMA context will become enabled transmits when cycle time "Cycle Count" value equals value this field. This cleared software enable descriptor processing context. chip will clear this automatically hardware software reset. Before software sets this bit, active must clear Command Pointer register context must contain valid descriptor block address value that appropriate descriptor block address. Software stop chip from further processing context clearing this bit. When cleared, chip will stop processing context manner that will impact operation other context controller. This require significant amount time. software clears while chip processing packet context, will continue receive transmit packet update descriptor status. will then stop conclusion that packet. Clearing have other side effects that controller dependent. This described sections that cover each controllers. 14-13 Reserved always reads
Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr. Offset Isoch Xmit Context Command Ptr.
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Isochronous Receive Context Registers Offset (Set), (Clr) Isoch Context Offset (Set), (Clr) Isoch Context Offset (Set), (Clr) Isoch Context Offset (Set), (Clr) Isoch Context These registers Context Control registers isochronous Receive Contexts 0-3. Each context consists three registers: Command Pointer, Context Control register, Context Match register. Command Pointer used software tell controller where context program begins. Context Control register controls context's behavior indicates current status. Context Match Register used start transmitting from context program specified cycle number. layout Context Control registers given below: Buffer Fill Each received packet placed single buffer Received packets placed back-to-back completely fill each receive buffer "Multi-Channel Mode" set, this must also set. This must changed while "Active" set. Isoch Header packet header stripped from received isochronous packets Received packets will include isochronous packet header (the header will stored first memory followed payload). packet will marked with "Transfer Status" (bits 15-0 this register) first word followed 16-bit time stamp indicating time most recently received "Cycle Start" packet. Cycle Match Enable Context will begin running immediately Context will begin running only when 13bit "Cycle Match" field "Context Match" register matches 13-bit "Cycle Count" Cycle Start packet. effects this impacted values other bits this register. Once context becomes active, this cleared automatically chip. Multi-Channel Mode context will receive packets single channel. context will receive packets isochronous channels enabled Channel Mask High" Channel Mask Low" registers (the channel number "Context Match" register ignored). more than Context Control register Multi-Channel Mode set, unspecified behavior will result.
27-16 Reserved .always reads This cleared software enable descriptor processing context. chip will clear this automatically hardware software reset. Before software sets this bit, active must clear Command Pointer register context must contain valid descriptor block address value that appropriate descriptor block address. Software stop chip from further processing context clearing this bit. When cleared, chip will stop processing context manner that will impact operation other context controller. This require significant amount time. software clears while chip processing packet context, will continue receive transmit packet update descriptor status. will then stop conclusion that packet. Clearing have other side effects that controller dependent. This described sections that cover each controllers. 14-13 Reserved .always reads Wake .default When software adds list descriptors context, chip have already read descriptor that list before updated. This provides semaphore indicate that list have changed. chip fetched descriptor indicated branch address value zero, will reread pointer value when wake set. reread, value still zero, then list been reached chip will clear active bit. however, value non-zero, chip will continue processing. wake while chip active value non-zero, takes special action. chip will clear this before reads rereads descriptor. wake should while zero. Dead .default This chip indicate fatal error processing descriptor. When set, active cleared. This cleared when software clears hardware software reset.
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Offset Isoch Receive Context Command Offset Isoch Receive Context Command Offset Isoch Receive Context Command Offset Isoch Receive Context Command Offset Isoch Receive Context Match Offset Isoch Receive Context Match Offset Isoch Receive Context Match Offset Isoch Receive Context Match
Active default This chip when software sets sets wake while set. chip will clear this bit: When branch indicated descriptor value branch address When software clears chip reached safe stopping point While dead After hardware software reset When this cleared clear, chip will Interrupt Event context. Reserved always reads Speed This field indicates speed which packet received transmitted: Mbits/sec Mbits/sec Mbits/sec -reservedAck Code. default Following "Input" command, this field contains error code. "Buffer Fill" mode, possible values are: "Ack Complete", "Ack Data Error", "Event Overrun", "Event Descriptor Read", "Event Data Write", "Event Unknown" (see "Table Packet Event Codes" descriptions values these codes). "Packet-Per-Buffer" mode, possible values are: "Ack Complete", "Ack Data Error", "Event Short Packet", "Event Long Packet", "Event Overrun", "Event Descriptor Read", "Event Data Write", "Event Unknown" (see "Table Packet Event Codes" descriptions values these codes).
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Register Field Descriptions (continued)
Contender Contender. Cleared software control value transmitted first self-ID packet. Pins Power class. This information will copied bits 21-23 first [0:2] self-ID packet. Repeater delay; 20ns variation Watchdog enable. Controls whether loop, power fail, timeout interrupts indicated link when link sleep. Also determines whether interrupts indicated internal link when resume operations start from port. Initiate short (arbitrated) reset. write this instructs chip arbitrate issue short reset. This selfclearing. Loop detect. write this clears zero. Cable power failure detect. when changes from zero. write this clears zero. Arbitration state machine timeout. write this clears zero. Port event detect. chip sets this connected, Bias, Disabled Fault change port whose Int_enable one. chip also sets this resume operations commence port Resume_int one. write this clears zero. Enable arbitration acceleration. When one, chip must enhancements specification IEEE P1394a 4.0. Enable multi-speed packet concatenation. Selects which eight possible register pages accessible through window register address 1000b through 1111b, inclusive. 0000 page selected Page_select presents port information, this field selects which port's registers accessible through window register addresses 1000b through 1111b, inclusive.
Registers registers accessed through Control register Memory Offset 0ECh. Register Overview Offset 0000b Physical 0001b Count 0010b Total Ports Extended 0011b Delay Speed 0100b Power Class Jitter Cont 0101b Multi Accel Tout Loop ISBR 0110b -reserved0111b Port Select Page Select 1000b Register (Page Select) 1001b Register (Page Select) 1010b Register (Page Select) 1011b Register (Page Select) 1100b Register (Page Select) 1101b Register (Page Select) 1110b Register (Page Select) 1111b Register (Page Select) Register Field Descriptions Field
Physical_ID
Power Class
Jitter
ISBR
Loop Power Fail
Bits Type Description
address this node determined during self-identification. value indicates malconfigured where link must transmit packets. setting indicates that this node root. Cable Power status. Root hold-off bit. setting instructs chip attempt become root during next tree identification process. Initiate reset. setting instructs chip initiate reset immediately (without arbitration). This causes assertion reset state self-clearing. Used configure arbitration timer setting order optimize times according topology bus. Constant value seven Three ports Supports 98.304, 196.608, 393.216 Mbit/s Worse case repeater delay Link Control. Cleared software control value transmitted node's SelfID packet
Timeout
Port Event
Enable Acceleration
Enable Multi Page Select
Count
Extended Total Ports Speed Delay Link Control
Port Select
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Register Page Vendor Identification Vendor Identification page used identify VT6307's vendor compliance level. page selected writing Page_select register address 0111. Offset 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Field
Compliance Level Vendor
Register Page Port Status Port Status page used access configuration status information each PHY's port. port selected writing zero Page_select desired port number Port_select register address 0111. Offset 1000b Disa Bias Conn Child Bstat Astat 1001b -reservedFault IntEn Negotiated Speed 1010b -reserved1011b -reserved1100b -reserved1101b -reserved1110b -reserved1111b -reserved-
Compliance Level -reservedVendor
Product
Table Register Page Field Descriptions
Field Astat Bits Type Description line state port invalid Bstat Same encoding Astat Child indicates port child, parent. meaning this undefined from time reset detected until chip transitions state T1:Child Handshake during tree identify process (see 4.4.2.2 IEEE 1394-1995) Conncted indicates port connected, zero indicates disconnected. value reported this filtered hysteresis logic reduce multiple status changes caused contact scrape when connector inserted removed. Bias indicates that bias voltage detected (possible connection). value reported this filtered hysteresis logic reduce multiple status changes caused contact scrape when connector inserted removed. Disabled When one, port disabled. value this subsequent power reset implementation-dependent, should strappable option. Negotiated Indicates maximum speed negotiated Speed between this port immediately connected port. 98.304 Mbit/s 196.608 Mbit/s 393.216 Mbit/s Interrupt Enable port event interrupts. When Enable one, chip sets Port_event Connected, Bias, Disabled Fault (for this port) change state. Fault error detected during suspend resume operation. write this clears zero.
Table Register Page Field Descriptions
Bits Type Default Description
indicates IEEE P1394a company Organizationally Unique Identifier (OUI) manufacturer PHY. most significant byte Vendor_ID appears register location 1010 least significant 1100. meaning this number determined company organization that been granted Vendor_ID. most significant byte Product_ID appears register location 1101 least significant 1111.
Product
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Register Descriptions
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VT6307 1394a Host Controller
Register Page Vendor-Dependent vendor-dependent page provides registers aside PHY's vendor. page selected writing seven Page_select register address 0111. Offset 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b Reserved Test Access) Reserved Test Access) Reserved Test Access) Reserved Test Access) Reserved Test Access) Reserved Test Access) Reserved Test Access) Reserved Test Access)
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Register Descriptions
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VT6307 1394a Host Controller
FUNCTIONAL DESCRIPTIONS
General Description
Cable Interface VT6307 provides three-port physical layer function cable IEEE 1394-1995 1394a-2000 network. Each cable port incorporates differential line transceivers. transceivers include circuitry monitor line conditions needed determining connection status, initialization arbitration, half duplex packet reception transmission. Data bits transmitted through cable ports latched internally VT6307 synchronization with 49.152-MHz system clock. During transmission encoded data transmitted differentially cable pair(s) encoded strobe information transmitted differentially cable pair(s). During packet reception, transmitters receiving cable port disabled, receivers that port enabled. encoded data information received cable pair, encoded Strobe information received cable pair. received data-strobe information resynchronized local clocks retiming buffer tolerate clock variation +/-100ppm with bytes 393.216 Mbps, bytes 196.608 Mbps, bytes 98.304 Mbps. Both cable interfaces (see figure below) incorporate differential comparators monitor line states during initialization arbitration. outputs these comparators used internal logic determine arbitration status. channel generates cable common-mode voltage. value this common mode voltage used during arbitration detect speed next packet transmission peer PHY. addition, VT6307 adds current source connection detect circuit channel. When TPBIAS driven low, connection detect circuit used detect presence absence peer other cable connection. channel monitors incoming cable common-mode voltage presence remotely supplied twisted-pair bias voltage. presence absence this common-mode voltage used indication cable suspend, resume active status.
Figure Cable Interface
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VT6307 1394a Host Controller
Circuit Description
Pinless Clock Generation VT6307 requires external 24.576 crystal reference. external clock also provided instead crystal. internal oscillator drives internal phase-locked loop (PLL), which generates required 393.216 reference clock. This reference signal internally divided provide clock signals used control transmission outbound encoded Strobe Data information. 49.152 clock signal used resynchronization received data. requires external filter components, referred "pinless PLL", saving board implementation cost. Power Down Auto Power Save power down function stops operation disables circuits except connection detection circuits bias detection circuits XTPBIAS pins. Port transmitter receiver circuitry also disabled automatically when port disabled, suspended, disconnected. Data Transmission Data bits transmitted through cable ports latched internally synchronization with 49.152 system clock. These bits combined serially, encoded, transmitted 98.304/196.608/392.216 Mbps (referred S100, S200, S400 speed, respectively) outbound data-strobe information stream. During transmission, encoded data information transmitted differentially cable pair(s), encoded strobe information transmitted differentially cable pair(s). Data Reception During packet reception transmitters receiving cable port disabled, receivers that port enabled. encoded data information received cable pair, encoded strobe information received cable pair. received data-strobe information decoded recover receive clock signal serial data bits. serial data bits collected into two-bit, four-bit eight-bit parallel streams (depending upon indicated receive speed), resynchronized local 49.152 system clock sent LLC. retiming buffer tolerate clock variation +/-100 (compared peer PHY) with bytes 393.216 Mbps, bytes 196.608 Mbps, bets 98.304 Mbps. received data also transmitted (repeated) other active (connected) cable ports. TPBIAS Both cable interfaces incorporate differential comparators monitor line states during initialization arbitration. outputs these comparators used internal logic determine arbitration status. channel monitors incoming cable common-mode voltage determine speed next packet transmission (speed signaling) during arbitration. addition, channel monitors incoming cable common-mode voltage pair presence peer bias voltage. VT6307 provides three independent 1.84V nominal bias voltages XTPBIAS pins. bias voltage, when seen through cable remote receiver, indicates presence active connection. bias voltage source must stabilized external filter capacitor 0.33 Bias-Detector Connect-Detector Bias-Discharger VT6307 supports suspend resume disable functions defined IEEE P1394a V4.0 specification. suspend mechanism allows pairs directly connected ports placed into power state while maintaining port-to-port connection between 1394 segments. While power state, port unable transmit receive data transaction packets. However, port power state capable detecting connection status changes detecting incoming TPBIAS. When three ports suspended, circuits except connect-detect circuits bias-detect circuits powered down, resulting significant power savings. connect-detect circuit monitors value incoming pair common-mode voltage when local TPBIAS inactive. very small current source charges XTPBIAS almost when cable connected. Before connect-detect circuit enabled, VT6307 enables bias-discharger improve later-on connect-detect quality. Both cable bias-detect monitor connect-detect monitor used connect suspend resume disable signaling. additional details suspend resume disable operation, refer IEEE P1394a V4.0 specification.
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Functional Descriptions
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VT6307 1394a Host Controller
Twisted-Pair line drivers operate high-impedance current mode, designed work with external line-termination resistor networks order match cable impedance. network provided each twisted-pair cable. Each network composed pair series-connected resistors. midpoint pair resistors that directly connected twisted-pair pins connected corresponding XTPBIAS pin. midpoint pair resistors that directly connected twisted-pair pins coupled ground through parallel network with recommended values values external line termination resistors designed meet standard specifications when connected parallel with internal receiver circuits. Bandgap Current Generation external resistor connected between XRES ground sets driver output current, well internal operating currents. This current setting resistor value 6.34K Power When power supply VT6307 removed while twisted-pair cables connected, VT6307 transmitter receiver circuitry XTPBIAS presents high impedance state. consequence, peer PHYs VT6307 unconnected. Unimplemented Ports When VT6307 used with more ports brought connector, some twisted-pair pins unused ports left unconnected reduce implementation cost. each unused port, XTPBIAS pins tied analog power (VCCA) more reliable operation. XTPAP, XTPAM, XTPBP XTPBM pins unused port left unconnected. CMC, PC0, PC1, Strapping PC[0:2] used strapping pins default value four configuration status bits self-ID packet should hard-wired high function equipment design. PC0, PC1, pins used indicate default power-class status node (the need power from cable ability supply power cable). used input indicate that node contender manager.
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Functional Descriptions
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VT6307 1394a Host Controller
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Symbol Parameter
TSTG VESD Storage temperature Case operating temperature Power supply voltage Input voltage Output voltage output Electrostatic discharge
-0.5 -0.5 -0.5
Unit
Volts Volts Volts
Comment
3.6V Human Body Model
Note: Stress above conditions listed cause permanent damage device. Functional operation this device should restricted conditions described under operating conditions.
Characteristics
0-55oC, 3.3V+/-5%,
Symbol Parameter
Input Voltage Input High Voltage Output Voltage Output High Voltage Input Leakage Current Tristate Leakage Current
-0.50
0.45
Unit
Condition
+4.0mA -1.0mA 0.45 VOUT
Power Characteristics
0-55oC, 3.3V+/-5%,
Symbol Parameter
ICC-PD ICCRAM-PD ICCSUS-PD ICCRAM ICCSUS ICCARX ICCATX Power Supply Current Power Supply Current VCCRAM Power Supply Current VCCSUS Power Supply Current Power Supply Current VCCRAM Power Supply Current VCCSUS Power Supply Current VCCARXn Power Supply Current VCCATXn Power Dissipation
Unit
Condition
Power Down Suspend Power Down Suspend Power Down Suspend S400, ports transmitting S400, ports transmitting S400, ports transmitting S400, ports transmitting S400, ports transmitting S400, ports transmitting
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VT6307 1394a Host Controller
Recommended Operating Conditions
Symbol Parameter VIL1 VIH1 VIL2 VIH2 Supply voltage Input Voltage Input High Voltage Input Voltage Input High Voltage TPBIAS output current PHYCMC, PHYPC[0:2] PHYCMC, PHYPC[0:2] PHYRST# PHYRST# Condition -0.5 -0.5 -1.2 PHYRST# input TPA/TPB cable input during data reception TPA/TPB cable input during arbitration 1.165 S400 S400 24.5735 24.576 2.515 ±0.5 ±0.5 Unit
Output High/Low current VIDA Power-up reset time Differential input voltage Differential input voltage Common mode input voltage Receive input jitter Receive input skew
FXSTAL Crystal external clock frequency
24.5785
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Electrical Specifications
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VT6307 1394a Host Controller
Analog Signal Characteristics
Unless otherwise noted, test conditions follows: +550C 3.3V 24.576 0.01% XRES 6.34 load TPA/TPB Driver Characteristics Symbol Parameter Output signal amplitude Transmitter skew Transmitter jitter Data output rise/fall time Condition Differential, 54.9 S400 S400 S100(10%-90%) S200(10%-90%) S400(10%-90%) VOFF state differential voltage Driver difference current Peak-to-peak, differential, 54.9 Speed signaling OFF, XTPAP, XTPAM, XTPBP, XTPBM -1.05 0.15 1.05 Unit
Common mode speed signaling S100, XTPBP, XTPBM current S200, XTPBP, XTPBM S400, XTPBP, XTPBM TPA/TPB Receiver Characteristics Symbol Parameter Differential input impedance Condition Driver disabled
-0.81 -0.44 -4.84 -2.53 -12.4 -8.10
Unit Kohm
Common mode impedance Driver disabled VTH-R Receiver input threshold voltage VTH-CB Cable bias detect threshold, XTPBx cable inputs VTH+ VTHPositive arbitration comparator threshold voltage Driver disabled Driver disabled Driver disabled -168
Kohm
Negative arbitration comparator threshold voltage Driver disabled Driver disabled Driver disabled
VTH-S200 S200 speed signal threshold VTH-S400 S400 speed signal threshold Connect Detect output TPBIAS pins
Characteristics Symbol Parameter Power status threshold TPBIAS output voltage Condition input with 1K/11K voltage divider current Unit
1.665 2.015
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Electrical Specifications
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VT6307 1394a Host Controller
PACKAGE MECHANICAL SPECIFICATIONS
-D102
0.05
Date Code Year Date Code Week Chip Version Revision Code Code
VT6307
YYWWVV TAIWAN LLRLLLLLL
DETAIL SEATING PLANE
CONTROL DIMENSIONS MILLIMETERS. MILLIMETER INCH MBOL MIN. NOM. MAX. MIN. NOM. MAX. 0.134 3.40 0.010 0.25 2.50 2.72 2.90 0.098 0.107 0.114 0.913 BASIC 23.20 BASIC GAGE PLANE 0.677 BASIC 17.20 BASIC 0.787 BASIC 20.00 BASIC 0.25 0.551 BASIC 14.00 BASIC 18.50 BASIC 0.728 BASIC 12.50 BASIC 0.492 BASIC DETAIL 0.13 0.30 0.005 0.012 0.13 0.005 NOTES DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING 0.11 0.15 0.23 0.004 0.006 0.009 MOLD MISMATCH. 0.73 0.88 1.03 0.029 0.035 0.041 1.60 0.063 DIMENSION DOES INCLUDE DAMBAR 0.20 0.008 PROTRUSION. ALLOWABLE DAMBAR 0.17 0.20 0.27 0.007 0.008 0.011 PROTRUSION SHALL CAUSE LEAD 0.50 BASIC 0.020 BASIC WIDTH EXCEED MAXIMUM DIMENSION TOLERANCES FORM POSITION MORE THAN 0.08mm. DAMBAR 0.20 0.008 LOCATED LOWER RADIUS FOOT. 0.20 0.008 MINIMUM SPACE BETWEEN PROTRUSION 0.08 0.003 ADJACENT LEAD 0.07mm. 0.08 0.003
Figure Mechanical Specifications VT6307 Rectangular 128-Pin PQFP Package
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Package Mechanical Specifications
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VT6307 1394a Host Controller
-D65
0.05
VT6307L
YYWWVV TAIWAN LLRLLLLLL
Date Code Year Date Code Week Chip Version Revision Code Code
DETAIL SEATING PLANE
CONTROL DIMENSIONS MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 1.60 0.063 0.05 0.15 0.002 0.006 1.35 1.40 1.45 0.053 0.055 0.057 22.00 BASIC 0.866 BASIC 20.00 BASIC 0.787 BASIC 16.00 BASIC 0.630 BASIC 14.00 BASIC 0.551 BASIC 0.08 0.20 0.003 0.008 0.08 0.003 0.09 0.20 0.004 0.008 0.45 0.60 0.75 0.018 0.024 0.030 1.00 0.039 0.20 0.008 0.17 0.20 0.27 0.007 0.008 0.011 0.50 BASIC 0.020 BASIC 18.50 0.728 12.50 0.492 TOLERANCES FORM POSITION 0.20 0.008 0.20 0.008 0.08 0.003 0.08 0.003
GAGE PLANE DETAIL
NOTES DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDTH EXCEED MAXIMUM DIMENSION MORE THAN 0.08mm. DAMBAR LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSION ADJACENT LEAD 0.07mm.
0.25
Figure Mechanical Specifications VT6307L Rectangular 128-Pin LQFP Package
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Package Mechanical Specifications
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VT6307 1394a Host Controller
0.05
Date Code Year Date Code Week Chip Version Revision Code Code
VT6307S
YYWWVV TAIWAN LLRLLLLLL
SEATING PLANE
0.25mm
GAGE PLANE
NOTES DIMENSIONS INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL CAUSE LEAD WIDTH EXCEED MAXIMUM DIMENSION MORE THAN 0.08mm. DAMBAR LOCATED LOWER RADIUS FOOT.
CONTROL DIMENSIONS MILLIMETERS. MILLIMETER INCH SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. 0.063 1.60 0.006 0.15 0.002 0.05 1.35 1.40 1.45 0.053 0.065 0.057 0.630 BASIC 16.00 BASIC 16.00 BASIC 0.630 BASIC 14.00 BASIC 0.551 BASIC 14.00 BASIC 0.551 BASIC 12.40 BASIC 0.488 BASIC 12.40 BASIC 0.488 BASIC 0.08 0.003 0.08 0.20 0.003 0.008 0.09 0.20 0.004 0.008 0.45 0.60 0.75 0.018 0.024 0.030 1.00 0.039 0.20 0.008 0.13 0.16 0.23 0.005 0.006 0.009 0.40 BASIC 0.016 BASIC TOLERANCES FORM POSITION 0.20 0.008 0.20 0.008 0.08 0.003 0.07 0.003
Figure Mechanical Specifications VT6307S Square 128-Pin LQFP Package
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Package Mechanical Specifications
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