03/11/02 16215 Alton Parkway P.O. 57013 Irvine, Califor

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APPLICATION NOTE Altima AC101L
03/11/02
16215 Alton Parkway
P.O. 57013
Irvine, California 92619-7013
Phone: 949-450-8700
Fax: 949-450-8710
Revision History
Revision
AC101L-AN100-R
Date
03/11/02
Change Description
Initial draft.
Altima Communications, Inc. Wholly Owned Subsidiary Broadcom Corporation P.O. 57013 16215 Alton Parkway Irvine, California 92619-7013 2002 Altima Communications, Inc. rights reserved
Broadcom® pulse logo® trademarks Broadcom Corporation and/or subsidiaries United States certain other countries. other trademarks property their respective owners.
Application Note
03/11/02
AC101L
TABLE CONTENTS
AC101L Overview 2.5V/3.3V Tolerance Internal Pull-ups Pull-downs. Reference Clock. RBIAD Power Saving Modes Manual Power Down Mode. Energy Detect/Low Power Mode Valid Data Detection Mode 100BASE-FX RXP/RXN TXP/TXN. Auto-MDI/MDIX Magnetics. Operation Cable Length Monitoring Capability. Supply Pins Power Planes VCC33IN. VCC25OUT. VCCPLL General Layout Notes Analog Related Passive Component Placement TXP/TXN Trace Routing RXP/RXN Trace Routing Reference Clock Magnetics RJ45 Chassis Ground Board Layer Allocation. Power Supply Filter Component Placement General Layout Recommendations Thermal Information AC101TF/QF AC101L
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AC101L
Application Note
03/11/02
AC101L Reference Schematic AC101L Bill Material Reference Schematic.18
Section Ordering Information
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Page Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
AC101L OVERVIEW
This application note contains detailed information regarding AC101L single channel 10/100 Physical Layer Device. AC101L, which capable either 2.5V 3.3V operation, targeted single port port copper fiber designs such NIC, motherboard, additional switch port, type implementations. AC101L includes following features: Auto-MDIX switching capability, 2.5V operation, MII/RMII interface, 10/100TX, 100FX. AC101L actually 2.5V device that includes on-chip 3.3V 2.5V regulators making suitable 3.3V system applications. AC101L suitable applications that 5.0V. AC101TF/QF identical AC101L with exception features. These differences described this application note. recommended that this application note read conjunction with latest versions AC101L data sheet.
2.5V/3.3V TOLERANCE
There basic power supply configurations that used with AC101L. operate exclusively 2.5V, operate exclusively 3.3V. AC101L digital inputs 3.3V tolerant accept 3.3V CMOS logic levels AC101L tolerant
Figure page illustrates power supply connections configurations described above.
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Document AC101L-AN100-RDC AC101L Overview Page
AC101L
Application Note
03/11/02
Power Connections AC101L
2.5V
3.3V SUPPLY
VCC25OUT VCC33IN
22UF .1UF
10UF .1UF .01UF 2.5V
VCCPLL
2.5V 2.2UF .01UF
.01UF
2.2UF
.1UF
.1UF
.1UF
.1UF
Place these caps next pins:
Power Connections AC101L
2.5V SUPPLY VCC25OUT VCC33IN
22UF .1UF 2.5V
2.5V
VCCPLL
2.5V 2.2UF .01UF
.01UF
2.2UF
.1UF
.1UF
.1UF
.1UF
Place these caps next pins:
Figure
Power Supply Configuration Options
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Page 2.5V/3.3V Tolerance Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
INTERNAL PULL-UPS PULL-DOWNS
This section lists those Inputs, combination Inputs/Outputs, that include internal resistive pull-ups pull-downs. value each pull-up pull-down approximately (±20%). following pins have very weak pull-up/pull-down, required have external resistor (5K-10K) pull-up/pulldown these pins:
Table Pull-Ups Pull-Downs Name
RXDV/CRSDV RMII_mode/RX_CLK ISOLATE/RX_ER TXER TX_CLK TXEN TXD[3:0] REPEATER/CRS PHYAD[4:0] BURNIN#/LED0 SPD100/LED1 DUPLEX/LED2 ANEN/LED3 PDOWN# RESET# MDIO
Default Internal
pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-down pull-up pull-up pull-up pull-up pull-up pull-up pull-up
Need External Pull-Down
always pull-down mode normal operation always pull-down normal operation always pull-down address [4:0] 00000 Speed10 Half Duplex Disable Auto-neg Power Down chip Reset chip
Need External Pull-Up
RMII mode Isolate Mode Repeater Mode address [4:0] 11111 always pull-up Speed100 Full Duplex Enable Auto-neg normal operation normal operation always pull-up with to2.5V 3.3V
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Document AC101L-AN100-RDC Internal Pull-ups Pull-downs Page
AC101L
Application Note
03/11/02
REFERENCE CLOCK
AC101L device accepts RMII applications) reference clock from either cost crystal circuit (parallel resonance operating fundamental mode) single ended clock source such self-contained oscillator buffered system clock. Figure clock connection requirements. stand-alone crystal applications, Broadcom recommends that crystal located close (crystal input) (crystal output) pins AC101L possible minimize stray capacitance excessive trace routing that could interfere with crystal start-up well clock stability. Broadcom recommends crystal rated total load capacitance calculation deriving approximate load capacitance ((CL1 CL2)/(CL1 CL2)) Where actual load capacitors connected either side crystal, stray capacitance input capacitance device. Assuming load caps 20pF each total stray parasitic capacitance approximately 8pF, above equation yields total load capacitance around 18pF. load capacitor values need adjusted from example above account variations parasitic capacitance and/or crystal specification. applications using crystal-based oscillator buffered system clock, input should used remain unconnected. input voltage swing reference clock must greater than 3.3v.
25Mhz_MII 50Mhz_RMII
CRYSTAL
330K
18pF
AC101L
18pF
Output Oscillator
AC101L
Figure
Oscillator Clock Considerations
electrical specifications recommended crystal oscillator clock source follows: Frequency tolerance: +/-50 Duty cycle: Edge rates: from (10% 90%) Voltage swing: limited 3.3v maximum Crystal aging: year, maximum Crystal frequency stability (over temperature):
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Page Reference Clock Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
following clock devices exhibit good performance variety Broadcom's evaluation platforms. Oscillator: part number LM20001E/DI-25.000M (G-ED, Marcos, (760) 591-4170) Oscillator: Epson Electronics part #SG636-PCE, SG636-PDE Crystal: Epson part number MA-506-25.000M-C2 Crystal: Digi-Key part number SE2639CT-ND Crystal: Ecliptek part #EC1SM-25.000
RBIAD
100BASE-TX 10BASE-T transmit amplitudes directly controlled adjusting amount current allowed flow from RBIAD GND. recommended that order verify proper transmit signal amplitude given design, initial value (1%) used external RBIAD resistor. important note that transmit signal amplitude affected magnetics insertion loss well stray capacitance front-end design. Therefore, important quantify these additional possible sources attenuation adjust value RBIAD resistor accordingly compensate. change RBIAD current results change transmit amplitude TXP/TXN outputs. Increasing value RBIAD resistor results proportional decrease transmit amplitude.
POWER SAVING MODES
AC101L supports three power modes operation discussed data sheet: Manual Power Down Mode, Energy Detect /Low Power Mode, Valid Data Detection Mode.
MANUAL POWER DOWN MODE
Manual Power Down Mode (PDOWN# Register 0.11=1) configures device such that circuitry, with exception Energy Detect block, powered down. This mode results maximum device current consumption approximately mA). device still able interface through management interface.
ENERGY DETECT/LOW POWER MODE
Energy Detect/Low Power Mode enable setting register 19.4=0. This Energy Detect circuit asserts when receive energy detected RXP/RXN wire side inputs. Reference CLOCK(REF_CLK) must present Energy Detection mode function properly. When this mode enabled, AC101L remains inactive will transmit anything onto wire until detects energy least 300mV differential) it's RXP/RXN inputs. Once energy detected, AC101L will automatically power operate normally. Note that this feature should restricted implementations environments where Link partner known entity. example, both ends link happen Automatic Power Saving mode, link will never activate.
VALID DATA DETECTION MODE
Valid Data Detection Mode achieved setting Register 23.13=1. During this mode RCLK (Receive Clock) will resume operation clock period prior assertion RXDV. receive clock will again shut clock cycles after RXDV gets deasserted, there data other than idles coming receive clock (RX_CLK) will turn off. This could save power. order successfully enter either Power modes, REF_CLK must continue least full clock cycles after PDOWN# switched. This ensures that power mode properly latched REF_CLK then deactivated, needed.
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Document AC101L-AN100-RDC RBIAD Page
AC101L
Application Note
03/11/02
100BASE-FX
AC101L supports 100BASE-FX operation RXP/N, TXP/N pins. connection diagrams Figure illustrate proper termination level shifting required interface AC101L 3.3V fiber transceiver.
APPLICATION
3_3V 2_5V
3_3V
3_3V
BLM11A601S .1uF .1uF BLM11A601S .1uF .1uF
0.01UF
Z=50 Z=50 Z=50 0.01UF
.1uF .1uF
Z=50 Z=50 RDSD
AC101L
SD/FXEN
Z=50 Z=50
.1uF .1uF
Z=50 Z=50
RxVcc RxVee TxVcc TxVee HFBR-5903
Figure
AC101L-100BASE-FX Interface with 3.3V Fiber module
Figure illustrates only termination scheme 100BASE-FX interface. Refer fiber transceiver manufacturer's guidelines transceiver power supply connection filtering. TXP/TXN RXP/RXN signal traces between fiber transceiver should each routed with characteristic impedance (100 differential) match termination network impedance given Figure traces require special impedance considerations static nature signal detect. Configuring AC101L 100BASE-FX operation accomplished simply connecting input 100BASE-FX compliant transceiver setting potential shown Figure There configure 100BASEFX operation through software. Hewlett Packard manufacture provides high quality 100BASE-FX transceivers. fiber module part #HFBR-5903.
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Page 100BASE-FX Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
When using 3.3V fiber transceiver, take care level shift signal from fiber transceiver AC101L properly. with interface, trace lengths should kept minimum wherever possible. module disabled when input level mode enabled when input used Signal Detect input with PECL threshold.
RXP/RXN
RXP/RXN inputs AC101L internally biased, typical 3.3V fiber transceivers normally source PECL with center voltage swing approximately 2.0V. Additionally, system layout requires that RXP/RXN trace lengths more than approximately inch, take care termination account transmission line effects well indicated Figure
TXP/TXN
AC101L employs current-sink outputs transmit 100BASE-FX signals fiber transceiver, special level shifting impedance matching termination network must implemented. slight mismatch final voltage divider versus ensures that TXP/TXN input fiber transceiver will switch noise that might present when AC101L quiet.
AUTO-MDI/MDIX
most 10/100BASE-TX connections, link configured (Medium Dependent Interface) crossover that each transceiver's transmitter connected other's receiver. This allows user install straight-through cables. However, there many instances where cross-over cables required causing confusion downtime field. AC101L contains ability perform Auto-MDI/MDIX crossover chip, thus eliminating need crossover cables cross-wired (MDIX) ports. During auto-negotiation 10/100BASE-TX operations, AC101L normally transmits TXP/TXN receives RXP/ RXN. When connected through straight-through cable another device that does perform Auto-MDI/MDIX crossover, AC101L automatically switches transmitter receiver communicate with remote device. devices connected that both have Auto-MDI/MDIX crossover capabilities, then random algorithm determines which performs crossover function. Auto-MDI/MDIX crossover feature function auto-negotiation. AC101L configured perform AutoNegotiation, feature does work, specific cable required ensure Transmitter cable connected with Receiver other cable. This feature enabled default disabled. Auto-MDI/MDIX feature implemented AC101L accordance with IEEE 802.3ab specification. Automatic MDI/MDI-X state machine facilitates switching between receiving pair transmitting pair respectively, prior auto-negotiation mode operation. This ensures that Fast Link Pulses (FLPs) transmitted received compliance with Clause auto-negotiation specification. final state crossover circuit determined algorithm that controls switching function between pairs (transmit receive). algorithm uses 11-bit Linear Feedback Shift Register (LFSR) create pseudo-random sequence with which AC101L determines initial configuration. AC101L, ensure LFSR seeded with unique value during reset, this determines initial state MDIX. specification, sample timer implemented manner that allows AC101L detect either valid Link Pulses Valid Link. after 62±2 receiver unable detect valid Link Pulse valid Link, LFSR advanced, switching pairs. Additionally, asynchronous timer used unlikely event where PHYs have identical reference clocks reset circuits. When this timer expires, resets state machine State restarts sample timer. This timer free running impact LFSR.
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AC101L
Application Note
03/11/02
Auto-MDI/MDIX operates only transmit receive data pairs (swapping them required). does operate individual wires within given pair therefore cannot correct possible polarity swap issues. However, 10BASE-T transceiver within AC101L includes polarity detection correction ensure proper functionality should polarity problem exist wiring. Note that 100BASE-TX signaling sensitive polarity therefore does strictly require polarity detection correction. Specific magnetics cable termination issues must considered when using AC101L Auto-MDI/MDIX mode. following section further detail.
MAGNETICS
Most applications require single channel magnetics support implementations based more AC101L devices. some applications, Quad-channel magnetics more practical. important restriction pairing magnetics with AC101L relates ordering isolation transformer common mode choke transmit signal path (and receive signal path when Auto-MDI/MDIX enabled). transmit output signal from AC101L must connected isolation transformer first, followed common mode choke depicted Figure common mode choke placed between transmit output pins isolation transformer, potentially severe signal distortion result while operating 10BASE-T auto-negotiation modes. following list includes recommended single channel magnetics components from various vendors with AC101L. these magnetics recommended regardless whether Auto-MDI/MDIX enabled. S558-5999-W2 (single) Pulse Engineering H1102 (single) Halo TG110-S050N2 (single), TG110-LC50N2 (single)
Figure page illustrates specific magnetics interconnect differential cable termination requirements applications that Auto-MDI/MDIX.
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Page Magnetics Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
2.5V
49.9_1/16W_1%
49.9_1/16W_1%
49.9_1/16W_1%
49.9_1/16W_1%
Application
Auto MDI/MDIX
RJ45
.1uF
AC101L
.1uF
2.5V
.1uF
.1uF
75_1/16W_5% 75_1/16W_5%
75_1/16W_5% 75_1/16W_5%
Auto MDI/MDIX Magnetics: BEL: S558-5999-W2; PULSE: H1102; HALO: TG110-S050N2
1000PF_2KV
Figure
Twist Pair/Magnetics Connection Differential Cable Termination Requirements
OPERATION
LED[3:0] output either source sink current approximately AC101L data sheet provides details LED1, LED2, LED3 provides proper external connectivity LEDs configure LEDs into different modes other than default. Connection: LEDs pull-up 2.5V 3.3V. recommended limit current below 10mA LED. Choosing current limiting resister value importance ensure desired LEDs brightness (typically 2.5V connection) Configuration: Each 16-bit registers define operation. Refer Common Register Event table AC101L data sheet detail. Table example configure LED3 Transmit/Receive Activity remove Collision (COL)
Table Configure LED3 TX/RX activity Step
Setting Register
[15:12]= 0011 A3.30[7:0]= 0000 0100
Purpose
Page Register Common register Turn Transmit/Receive Activity Event into LED3 turn Collision Event
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AC101L
Application Note
03/11/02
CABLE LENGTH MONITORING CAPABILITY
Bits [7:4] Register provide meter length estimate cable connected receiver inputs AC101L (assuming station operational). This estimate accessed simply reading Reg. 20[7:4]. This provides user with easily accessed powerful diagnostic tool determining potential problems within cable plant and/or associated connectors. Table length estimates.
Table Cable Length Estimate Register Bits[7,
0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1100
Cable Length Meters
<100 <110 <120 <130 >130
SUPPLY PINS POWER PLANES
This section describes power pins recommended power plane partitioning AC101L well detailed descriptions each type power supply pin. solid power supply plane always recommended each supply required application. design calls both 2.5V 3.3V supplies, then dedicated board layers should provided each supply. Fragmenting, segmenting, otherwise interrupting power supply plane recommended. AC101L essentially 2.5V device with on-chip regulators, making suitable 3.3V applications. clarify purpose power types, each type listed defined below (See Figure page
VCC33IN
voltage regulator input pins should connected 3.3V system power rail only device powered from single 3.3V supply (See Figure pins should left unconnected applications where system provides 2.5V directly chip.
VCC25OUT
used chip regulator, supply 2.5V output. This must connected pins supply power chip. used chip regulator, (VCC25OUT) pins connected external 2.5V power supply.
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Application Note
03/11/02
AC101L
These pins must connected VCC25OUT external 2.5V power supply.
VCCPLL
This must connected VCC25OUT external 2.5V power supply.
GENERAL LAYOUT NOTES
When determining component placement routing AC101L based design, following recommendations help optimize system design performance.
ANALOG RELATED PASSIVE COMPONENT PLACEMENT
Relative component placement across analog side AC101L (pins through critical should addressed with following priorities mind: Power supply filter components should placed first located closest (highest priority) Transmit termination resistors should placed close possible TXP/TXN pins Receive termination network should placed close possible RXP/RXN pins
TXP/TXN TRACE ROUTING
When routing TXP/TXN signal traces from transformer, traces should routed adjacent ground plane controlled characteristic impedance. Broadcom recommends that signal traces routed with matched length short possible), with characteristic differential impedance 100.
RXP/RXN TRACE ROUTING
traces, which connect receive transformer PHY, should routed with differential characteristic impedance should routed adjacent ground plane. Again, matched trace length important.
REFERENCE CLOCK
design requires cost crystal, minimize trace length from crystal (crystal output) (crystal input) pins AC101L. This will help minimize stray capacitance noise pick-up that might otherwise affect reference clock integrity. worst case scenario, much parasitic capacitance and/or inductance crystal traces could cause crystal suffer from start-up problems and/or instability. When using single-ended reference clock, usually best series terminate clock source ensure optimal signal integrity input AC101L.
MAGNETICS RJ45
Broadcom recommends that properly grounded (usually chassis ground) shielded RJ45 media connectors used control emissions. When routing transmit receive pairs between magnetics RJ45, recommended that inner layer layers used. outer layers (top bottom) then dedicated chassis ground area between magnetics RJ45. This will help isolate sensitive analog signals from external noise sources, well help reduce emissions. Figure page
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AC101L
Application Note
03/11/02
CHASSIS GROUND
When planning placement chassis ground layout, always beneficial consider placing least component pads (1206 size) across void between chassis ground system ground. These component pads stuffed with variety components reduce emissions. Installing capacitors leaving these pads unpopulated options considered. These options provide substantial flexibility when attempting control emissions.
BOARD LAYER ALLOCATION
Figure page illustrates option board layer allocation. figure gives example based single single ground plane. course some applications will require second plane order accommodate second power rail.
Optional
RXP/N Layer 1=Top (Components, Signals Chassis ground) RJ45 Chassis ground TXP/N Layer (Groung, Signals) RJ45
AC101L
Signal Routing
AC101L
ground plane
Signal Routing RXP/N
Layer (Power plane, signals)
AC101L
RJ45 Signal Routing
Power plane TXP/N Layer bottom (signals, chassis gnound)
AC101L
RJ45 Chassis ground
Signal Routing
Figure
Typical Layer Allocation (AC101L)
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Page General Layout Notes Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
POWER SUPPLY FILTER COMPONENT PLACEMENT
Power supply filter component placement illustrated Figure page these general placement guidelines ensure optimal performance.
10UF .1uF
3_3V
0.01UF
2_5V
.1uF 22UF
2_5V
.1uF
RXD0/PHYAD4 RXD1/PHYAD3 RXD2/PHYAD2 RXD3/PHYAD1 MDIO RST_L VCC33IN GND8 GND7
Place CAPs close possible each power AC101L
0.01UF .1uF
TXD2 TXD3 CRS/REPEATER GND3 INTR/PHYAD0 LED0/BURNIN_L LED1/SPD100 LED2/DUPLEX LED3/ANEN PDOWN
0.01UF
GND1 RXDV/CRSDV RXC/RMII_mode AC101L RXER/ISOLATE GND2 48TQFP_7x7mm TXER TXEN TXD0 TXD1
VCC25OUT GND6 VCCPLL RBIAD GND5 GND4 SD/FXEN
2_5V
VCCPLL 2.2UF
2_5V
.1uF 0.01UF
.1uF
0.01UF
Figure
AC101L Relative Placement Filter Components
GENERAL LAYOUT RECOMMENDATIONS
following general layout recommendations help ensure robust overall system design: Keep trace lengths minimum, especially more sensitive signal traces between RJ45. Each signal trace routed between RJ45 should controlled impedance (100 differential). Refrain from routing traces with right-angle corners. Always chamfer trace corners gradually possible. Route differential pairs such that signals matched length. Route signal traces with target characteristic impedance Always attempt route noisy digital traces away from sensitive power supply pins associated filtering such
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2_5V
AC101L
Application Note
03/11/02
VCC. traces must cross each other, even though would have separate layers, always cross them degrees minimize potential crosstalk. Always place power supply filter components close possible recommended pins (see Figure page order maximize filtering effects. filter component cannot directly connected given power with very short etch, connect copper trace. Instead make connection directly associated planes with vias. Refrain from routing signals (analog digital) over non-contiguous power ground planes this causes interruptions controlled impedance results reflections possible increase emissions. Leave outer edges (approximately mils) voided layers minimize fringe effects that could otherwise contribute emissions. Other than chassis ground area, keep system ground plane single uninterrupted plane maximum area create impedance path return currents. This will also help control emissions. Connect power ground pins directly their respective planes large and/or multiple vias. Avoid routing traces power ground connections.
THERMAL INFORMATION
This section includes basic thermal information pertaining AC101LKPT package types. Table provide Thermal data Theta-JA versus Airflow.
Table AC101LKPB Theta-JA Airflow FLOW (feet minute) 48TQFP Package
Theta-JA (C/W) 53.9
51.2
48.6
47.5
Theta-JC this package given 24.7 C/W. Additionally, AC101LKQT designed rated maximum Junction Temperature 125C.
AC101TF/QF AC101L
AC101TF/QF differs from AC101L follows: AC101TF/QF does support Auto-MDI/MDIX; AC101L supports Auto MDI/MDIX AC101TF/QF operates 3.3V; AC101L operates 2.5V with chip regulator AC101TF TQFP package, AC101QF PQFP package; AC101L TQFP package AC101TF/QF does support programmable LED; AC101L supports programmable
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Application Note
03/11/02
AC101L
AC101L REFERENCE SCHEMATIC
Diagram DEMO board AC101L with Copper
LED0_Link/Act LED3_COL/ANEN LED1_SPD100
LED2_DPX
Header signal
RJ45
Auto MDI/MDIX Magnetic
AC101L
Clock Power Supply Reset
BAC90101L-TP-MII
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Horizontal connector
2.5V_output
2_5V
2_5V
TAB/GND
LED2V5 RST_L 4.7K .1uF 22UF .1uF 10UF SW_8MM_EVQ 10UF
Vout
4.7K
.1uF
0.01UF
XTAL_OUT 25MHZ_CRYSTAL PHYAD1 PHYAD2 PHYAD3 PHYAD4 18pF
REFCLK
.1uF
22UF
RXD0/PHYAD4 RXD1/PHYAD3 RXD2/PHYAD2 RXD3/PHYAD1 MDIO RST_L VCC33IN GND8 GND7
VCCPLL RBIAD Mode
H1102
RXDV RXER
RJ45_1 RJ45_2 RJ45_3 TXNC RXH1102
2_5V
.1uF
.1uF
.1uF
.1uF
TXD2 TXD3 PDOWN 4.7K 4.7K LED0
TXD2 TXD3 CRS/REPEATER GND3 INTR/PHYAD0 LED0/BURNIN_L LED1/SPD100 LED2/DUPLEX LED3/ANEN PDOWN
4.7K
.1uF .1uF .1uF .1uF
LED3_COL
LED3
Place close AC101L 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF
2.2UF Place close pins AC101L
4.7K
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TXER TXEN TXD0 TXD1
GND1 RXDV/CRSDV RXC/RMII_mode AC101L RXER/ISOLATE GND2 48TQFP_7x7mm TXER TXEN TXD0 TXD1 VCC25OUT GND6 VCCPLL RBIAD GND5 GND4 SD/FXEN
2_5V
2_5V
1000PF_2KV
4.7K
2_5V
2_5V
LED0_LINK/ACT
PHYAD0 PHYAD1 PHYAD2 PHYAD3 PHYAD4 4.7K 4.7K 4.7K 4.7K 4.7K
Address 0000
4.7K
LED1_SPD100
LED1
4.7K
2_5V
LED2_DPX
LED2 VCCPLL
2_5V
Hole
Hole
Hole
Hole
Page
MII_5V
.1uF
2_5V
AC101L
LT1963 LT1963EST_2-5
MII_5V 2_5V
2.5V
.1uF
.1uF
10UF
RESET
required least square inch copper heat dissipation. 3_3V
line Impedance
3_3V
MDIO RXD3 RXD2 RXD1 RXD0 RXDV RXER TXER TXEN TXD0 TXD1 TXD2 TXD3
MDIO RXD3 RXD2 RXD1 RXD0 RXDV RXCLK RXER TXER TXCLK TXEN TXD0 TXD1 TXD2 TXD3
MII_5V
CLOCK
SMD_MII
10UF
.1uF
XTAL_IN 330K 18pF 10UF
AC101L Reference Schematic
Interface
RST_L MDIO RXD3 RXD2 RXD1 RXD0
2_5V
2_5V
RJ45_NOLED
Broa
Title
Application Note
03/11/02
Document AC101L-AN100-RDC
Date:
AC90101L
Size Custo
03/11/02
PART# 110246-00
Revision: Bill Materials Reference
C1,C5,C9,C10,C12 C2,C3,C4,C6,C8,C11,C14, C17,C20,C21,C22,C23,C30, C31,C32,C33 C7,C18 C13,C25,C26,C27,C28,C29 C16,C15 C36,C37,C38,C39 GP2,GP1 JP3,JP1 JP4,JP2 MT1,MT2,MT3,MT4 R2,R8,R9,R10,R11,R16,R17, R18,R19,R28,R29 R3,R5,R25,R30,R31,R32, R33,R34,R36,R38,R40,R42 R4,R35,R37,R39,R41 330K RC0603 RC0603 RM73B1JT334J Eric Electronic
RES-THK-150-5%-1/16W-0603 RES-THK-330K-0603-5%-63MW
Application Note
Document AC101L-AN100-RDC
Item
10UF .1uF CC0603 PCC1762CT-ND DIGIKEY
X7R-CERAMIC-0603
CaseA DigiKey
Part value
Footprint
Description
CAP-TNT-10UF-3528-10V-20% A-CASE
0.01UF 18pF 1000PF_2KV 2.2UF LED2V5 LED0_LINK/ACT LED1_SPD100 LED2_DPX LED3_COL GNDLUGB J9X2HDR_PS J2HDR_PS SMD_MII RJ45_NOLED Hole RJ_45 MTG_125 RC0603 RC0603 4.7K RC0603 SMD_MII J2HDR_PS J9X2HDR_PS TP_080 LED_0805 LED_0805 LED_0805 LED_0805 LN1371G-(TR) LN1371G-(TR) LN1371G-(TR) LN1371G-(TR) 151-103-100 LED_0805 LN1371G-(TR) CC1206 PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC MOUSER FCN-238P040-G/F Fujitsu C3216PN TCM1C225AT CC0603 CC1812 CC0603 DIGIKEY CC0603 DIGIKEY CC0603
22UF
CaseB
DigiKey
CAP-TNT-22UF-3528-10V-20%-CaseB CAP-CER-X7R-0.01UF-50V-0603-10% CAP-CER-18PF-0603-5%-100V-NPO X7R-CERAMIC-0603-10% CAP-CER-1000PF-1812-80/20_2KV CAP-CER-X7R-1NF-50V-0603-10%
SURFACE MOUNT CAP-TNT-2.2UF-3216-16V-10%-A Case DISTRIBUTOR
CAP-CER-X7R-1000PF-1206-10%-50V DIO-LED-GRN-STR-0805-SMD DIO-LED-GRN-STR-0805-SMD DIO-LED-GRN-STR-0805-SMD DIO-LED-GRN-STR-0805-SMD DIO-LED-GRN-STR-0805-SMD
AC101L BILL MATERIAL REFERENCE SCHEMATIC
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Header-CON-STR-Male-0.100 center
Header-CON-STR-Male-0.100 center FCN-238P040-G/F: Plug, Straddle mount, RJ45-NOLED-SHIELD
RES-THK-1.1K-0603-1%-63MW RES-THK-22-5%-1/16W-0603
RES-THK-4.7K-5%-1/16W-0603
AC101L Bill Material Reference Schematic
AC101L
Page
Page
AC101L_TP_MII_CC_BOM
RES-THK-300-0603-5%-63MW
AC101L
R12,R13,R14,R15 R20,R21,R22,R26 R23,R24,R43
RES-THK-10K-0603-1%-63MW RES-THK-4.7K-5%-1/16W-0603
49.9 RC0603 RC0603 4.7K SW_8MM_EVQ H1102 LT1963EST_2-5 AC101L 2_5V 3_3V 25Mhz_Crystal SMT_4X10 EC1SM-25.000; Ecliptek CA18C1-25.000MH TP_080 TP_080 TP_080 48TQFP AC101LKQT LT1963_SOT223 Linear SO16W Pulse Eng. SW_8MM_EVQ P8029SCT DigiKey
Auto
RC0603 DIGI-KEY MCR03EZHMJW75 SURFACE MOUNT RES-THK-75-0603-1%-63MW 0;RM73B1JT750J DISTRIBUTOR DigiKey (Genr) RES-THK-49.9-0805-1%
RC0603 RC0603
IC-REG-LT1963-SOT223-,2.5V
CON-PIN-TEST-RED CON-PIN-TEST-RED CON-PIN-TEST-RED
Broadcom
AC101L Bill Material Reference Schematic
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Application Note
03/11/02
Document AC101L-AN100-RDC
Application Note
03/11/02
AC101L
Table Ordering Information Part Name
AC101L
Part Number
AC101LKQT
Package Type
48-pin TQFP package
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Document AC101L-AN100-RDC Ordering Information Page
AC101L
Application Note
03/11/02
Broadcom Corporation
16215 Alton Parkway P.O. 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
Broadcom Corporation reserves right make changes without further notice products data herein improve reliability, function, design. Information furnished Broadcom Corporation believed accurate reliable. However, Broadcom Corporation does assume liability arising application this information, application product circuit described herein, neither does convey license under patent rights rights others.
ocume 101L- 100-

03/11/02 16215 Alton Parkway P.O. 57013 Irvine, Califor

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