SUMMARY High performance 32-bit/40-bit floating-point processor o

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SHARC® Processor ADSP-21262
SUMMARY
High performance 32-bit/40-bit floating-point processor optimized high precision signal processing applications ADSP-21262 SHARC code compatible with other SHARC DSPs Single-Instruction Multiple-Data (SIMD) computational architecture-two 32-bit IEEE floating-point/32-bit fixedpoint/40-bit extended precision floating-point computational units, each with multiplier, ALU, shifter, register file High bandwidth I/O-A parallel port, port, serial ports, digital audio interface (DAI), JTAG incorporates precision clock generators (PCGs), input data port (IDP) which includes parallel data acquisition port (PDAP), three programmable timers, under software control through signal routing unit (SRU) On-chip memory-2M bits on-chip SRAM dedicated bits on-chip mask-programmable independent synchronous serial ports provide variety serial communication protocols including modes ADSP-21262 available with core instruction rate. complete ordering information, Ordering Guide Page
CORE PROCESSO INSTRUCTION CACHE 48-BIT
DUAL PORTED MEMORY BLOCK SRAM MBIT MBIT
DUAL PORTED MEMORY SRAM MBIT MBIT
TIMER
DAG1
DAG2
PROGRAM SEQUENCER
ADDR
DATA
ADDR
DATA
ADDRESS ADDRESS DATA DATA NTROLLER
(32)
(18) GPIO FLAGS/ IRQ/TIMEXP
OL/GP
REGISTER PROCESSING EMENT (PEX) PROCESSING ELEMENT (PEY)
GPIO
JTAG TEST EMULATION SIGNAL ROUTING UNIT
SERIAL PORTS INPUT DATA PORTS PARALLEL DATA ACQUISITION PORT PRECISI GENERATORS TIMERS REGISTERS (MEMORY MAPPED) NTROL, STATUS, DATA BUFFERS
PARALLEL PORT
DIGITAL AUDIO INTERFACE PROCESSOR
Figure Functional Block Diagram
SHARC SHARC logo registered trademarks Analog Devices, Inc.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106 U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. rights reserved.
ADSP-21262
FEATURES
core instruction rate, ADSP-21262 operates 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating fixed floating point data MMACS sustained performance Super Harvard Architecture-three independent buses dual data fetch, instruction fetch, nonintrusive, zerooverhead bits on-chip dual-ported SRAM block block simultaneous access core processor bits on-chip dual-ported mask-programmable bits block bits block Dual data address generators (DAGs) with modulo bitreverse addressing Zero-overhead looping with single-cycle loop setup, providing efficient program sequencing Single instruction multiple data (SIMD) architecture provides: computational processing elements Concurrent execution- Each processing element executes same instruction, operates different data Parallelism buses computational units allows: Single cycle executions (with without SIMD) multiply operation; operation; dual memory read write; instruction fetch Transfers between memory core four 32-bit floating- fixed-point words cycle, sustained 2.4G Bytes/s bandwidth core instruction rate. addition, 900M Bytes/sec available Accelerated butterfly computation through multiply with subtract instruction controller supports: zero-overhead channels transfers between ADSP-21262 internal memory serial ports (12), input data port (IDP) (8), SPI-compatible port (1), parallel port 32-bit background transfers core clock speed, parallel with full-speed processor execution Asynchronous parallel/external port provides: Access asynchronous external memory multiplexed address/data lines support 24-bit address external address range with 8-bit data 16-bit address external address range with 16-bit data Byte transfer rate core rate word page boundaries External memory access dedicated channel 32-bit 32-bit word packing options Programmable wait state options: CCLK Digital audio interface (DAI) includes serial ports, precision clock generators, input data port, three programmable timers signal routing unit Serial ports provide: dual data line serial ports that operate Mbits/s core each data line each clock, frame sync, data lines that configured either receiver transmitter pair Left-justified sample pair support, programmable direction simultaneous receive transmit channels using compatible stereo devices serial port support telecommunications interfaces including channel support telephony interfaces such H.100/H.110 stream support, each with channels frame Companding selection channel basis mode Input data port provides additional input path core configurable either eight channels serial data seven channels plus single 20-bit wide synchronous parallel data acquisition port Supports receive audio channel data I2S, left-justified sample pair, right-justified mode Signal routing unit provides configurable flexible connections between components, serial ports, input data port, precision clock generators, three timers, interrupts, flag inputs, flag outputs, pins (DAI_Px) Serial peripheral interface (SPI) Master slave serial boot through Full-duplex operation Master-slave mode multimaster support Open drain outputs Programmable baud rates, clock polarities, phases Muxed Flag/IRQ lines Muxed Flag/Timer expired line based security features: JTAG access memory permitted with 64-bit Protected memory regions that assigned limit access under program control sensitive code wide variety software hardware multiplier/divider ratios JTAG background telemetry enhanced emulation features IEEE 1149.1 JTAG standard test access port on-chip emulation Dual voltage: I/O, core Available 136-ball 144-lead LQFP packages Lead free packages also available
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TABLE CONTENTS
General Description ADSP-21262 Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch Instruction Four Operands Instruction Cache Data Address Generators With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction ADSP-21262 Memory Interface Features Dual-Ported On-Chip Memory Controller Digital Audio Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Designing Emulator-Compatible Board (Target) Additional Information Function Descriptions Address Data Pins FLAGs Boot Modes Core Instruction Rate CLKIN Ratio Modes Address Data Modes ADSP-21262 Specifications Recommended Operating Conditions Electrical Characteristics Absolute Maximum Ratings Sensitivity Timing Specifications Power-up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Direct Routing Precision Clock Generator (Direct Routing) Flags Memory Read-Parallel Port Memory Write-Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Interface-Master Interface-Slave JTAG Test Access Port Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 136-Ball Configurations 144-LQFP Configurations Package Dimensions Ordering Guide
REVISION HISTORY
4/04-Data Sheet Changed from Rev. Rev. Added notes pins Added VIHCLKIN VILCLKIN specifications Changed specifications (tALERW, tALEHZ) .25-28 Updated 136-BGA package drawing
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GENERAL DESCRIPTION
ADSP-21262 SHARC member SIMD SHARC family DSPs featuring Analog Devices Super Harvard Architecture. ADSP-21262 source code compatible with ADSP-21160 ADSP-21161 DSPs well with first generation ADSP-2106x SHARC processors SISD (Single-Instruction, Single-Data) mode. Like other SHARC DSPs, ADSP-21262 32-bit/40-bit floating-point processor optimized high precision signal processing applications with dual-ported on-chip SRAM, mask-programmable ROM, multiple internal buses eliminate bottlenecks, innovative Digital Audio Interface (DAI). shown functional block diagram Page ADSP21262 uses computational units deliver times performance increase over ADSP-2106x range algorithms. Fabricated state-of-the-art, high speed, CMOS process, ADSP-21262 achieves instruction cycle time MHz. With SIMD computational hardware, ADSP-21262 perform 1200 MFLOPS running MHz. Table shows performance benchmarks ADSP-21262. Table ADSP-21262 Benchmarks MHz)
Benchmark Algorithm 1024 Point Complex (Radix with reversal) Filter (per tap)1 Filter (per biquad)1 Matrix Multiply (pipelined) Divide Inverse Square Root
Three Programmable Interval Timers with Generation, Capture/Pulse Width Measurement, External Event Counter Capabilities On-chip dual-ported SRAM bits) On-chip dual-ported mask-programmable bits) JTAG test access port block diagram ADSP-21262 Page illustrates following architectural features: 16-bit parallel port that supports interfaces off-chip memory peripherals controller full duplex serial ports compatible interface Digital Audio Interface that includes precision clock generators (PCG), input data port (IDP), serial ports, eight serial interfaces, 20-bit synchronous parallel input port, interrupts, flag outputs, flag inputs, three timers, flexible signal routing unit (SRU) Figure Page shows sample configuration SPORT using precision clock generator interface with with much lower jitter clock than serial port would generate itself. Many other configurations possible.
Speed MHz) 22.5 22.5
ADSP-21262 FAMILY CORE ARCHITECTURE
ADSP-21262 code compatible assembly level with ADSP-21266, ADSP-21160 ADSP-21161, with first generation ADSP-2106x SHARC DSPs. ADSP-21262 shares architectural features with ADSP-2126x ADSP-2116x SIMD SHARC family DSPs, detailed following sections.
Assumes files multichannel SIMD mode
SIMD Computational Engine
ADSP-21262 contains computational processing elements that operate Single-Instruction Multiple-Data (SIMD) engine. processing elements referred each contains ALU, multiplier, shifter, register file. always active, enabled setting PEYEN mode MODE1 register. When this mode enabled, same instruction executed both processing elements, each processing element operates different data. This architecture efficient executing math intensive algorithms. Entering SIMD mode also effect data transferred between memory processing elements. When SIMD mode, twice data bandwidth required sustain computational operation processing elements. Because this requirement, entering SIMD mode also doubles bandwidth between memory processing elements. When using DAGs transfer data SIMD mode, data values transferred with each access memory register file.
ADSP-21262 continues SHARC's industry leading standards integration DSPs, combining high performance 32-bit core with integrated, on-chip system features. These features include Mbits dual-ported SRAM memory, Mbits dual-ported ROM, processor that supports channels, serial ports, interface, external parallel bus, Digital Audio Interface (DAI). block diagram ADSP-21262 Page illustrates following architectural features: processing elements, each containing ALU, Multiplier, Shifter, Data Register File Data Address Generators (DAG1, DAG2) Program sequencer with instruction cache buses capable supporting four 32-bit data transfers between memory core every core processor cycle
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ADSP-212
CLKO CLOCK CLKIN XTAL CLK_CFG1 TCFG FLAG3 FLAG0 (OPTI ONAL) AD15 LATCH ADDR DATA PARALLEL PORT RAM, BOOT VICE
CONTRO
DATA
ADDRESS
DAI_P DAI_P DAI_P SCLK0 SFS0 SD0A SD0B PORT0 PORT2 PORT3 PORT4 PORT5
(OPTI ONAL)
RESE
Figure ADSP-21262 System Sample Configuration
Independent, Parallel Computation Units
Within each processing element computational units. computational units consist arithmetic/logic unit (ALU), multiplier, shifter. These units perform operations single cycle. three units within each processing element arranged parallel, maximizing computational throughput. Single multifunction instructions execute parallel multiplier operations. SIMD mode, parallel multiplier operations occur both processing elements. These computation units support IEEE 32-bit singleprecision floating-point, 40-bit extended precision floatingpoint, 32-bit fixed-point data formats.
Single-Cycle Fetch Instruction Four Operands
ADSP-21262 features enhanced Harvard architecture which data memory (DM) transfers data program memory (PM) transfers both instructions data (see Figure Page With ADSP-21262's separate program data memory buses on-chip instruction cache, processor simultaneously fetch four operands (two over each data bus) instruction (from cache), single cycle.
Instruction Cache
ADSP-21262 includes on-chip instruction cache that enables three-bus operation fetching instruction four data values. cache selective-only instructions whose fetches conflict with data accesses cached. This cache allows full-speed execution core, looped operations such digital filter multiply-accumulates, butterfly processing.
Data Register File
general-purpose data register file contained each processing element. register files transfer data between computation units data buses, store intermediate results. These 10-port, 32-register primary, secondary) register files, combined with ADSP-2126x enhanced Harvard architecture, allow unconstrained data flow between computation units internal memory. registers referred R0-R15 S0-S15.
Data Address Generators with Zero-Overhead Hardware Circular Buffer Support
ADSP-21262's data address generators (DAGs) used indirect addressing implementing circular data buffers hardware. Circular buffers allow efficient programming delay lines other data structures required digital signal processing, commonly used digital filters
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Fourier transforms. DAGs ADSP-21262 contain sufficient registers allow creation circular buffers primary register sets, secondary). DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, simplify implementation. Circular buffers start memory location. (PDAP), parallel port. Twenty-two channels available ADSP-21262-one interface, serial ports, eight Input Data Port, processor's parallel port. Programs downloaded ADSP-21262 using transfers. Other features include interrupt generation upon completion transfers, chaining automatic linked transfers.
Flexible Instruction
48-bit instruction word accommodates variety parallel operations concise programming. example, ADSP-21262 conditionally execute multiply, add, subtract both processing elements while branching fetching four 32-bit values from memory-all single instruction.
Digital Audio Interface (DAI)
Digital Audio Interface (DAI) provides ability connect various peripherals DSPs pins (DAI_P[20:1]). Programs make these connections using Signal Routing Unit (SRU, shown Figure matrix routing unit group multiplexers) that enables peripherals provided interconnected under software control. This provides easy associated peripherals much wider variety applications using larger algorithms than possible with nonconfigurable signal paths. also includes serial ports, precision clock generators (PCGs), input data port (IDP), flag outputs flag inputs, three timers. provides additional input path core configurable either eight channels serial data, seven channels plus single 20-bit wide synchronous parallel data acquisition port. Each data channel channel that independent from ADSP-21262's serial ports. complete information using DAI, ADSP-2126x SHARC Peripherals Manual.
ADSP-21262 MEMORY INTERFACE FEATURES
ADSP-21262 adds following architectural features SIMD SHARC family core.
Dual-Ported On-Chip Memory
ADSP-21262 contains megabits internal SRAM four megabits internal mask-programmable ROM. Each block configured different combinations code data storage (see ADSP-21262 Memory Page Each memory block dual-ported single-cycle, independent accesses core processor processor. dualported memory, combination with three separate on-chip buses, allows data transfers from core from processor, single cycle. ADSP-21262's SRAM configured maximum words 32-bit data, 128K words 16-bit data, words 48-bit instructions 40-bit data), combinations different word sizes megabits. memory accessed 16-bit, 32-bit, 48-bit, 64-bit words. 16-bit floating-point storage format supported that effectively doubles amount data that stored on-chip. Conversion between 32-bit floating-point 16-bit floating-point formats performed single instruction. While each memory block store combinations code data, accesses most efficient when block stores data using transfers, other block stores instructions data using transfers. Using buses, with dedicated each memory block assures single-cycle execution with data transfers. this case, instruction must available cache.
Serial Ports
ADSP-21262 features synchronous serial ports that provide inexpensive interface wide variety digital mixed-signal peripheral devices such Analog Devices AD183x family audio codecs, DACs, ADCs. serial ports made data lines, clock, frame sync. data lines programmed either transmit receive each data line dedicated channel. Serial ports enabled programmable simultaneous receive transmit pins that support transmit receive channels serial data when SPORTs enabled, full duplex streams channels frame. serial ports operate one-quarter core clock rate, providing each with maximum data rate bits/s core. Serial port data automatically transferred from on-chip memory dedicated channels. Each serial ports work conjunction with another serial port provide support. SPORT provides transmit signals while other SPORT provides receive signals. frame sync clock shared.
Controller
ADSP-21262's on-chip controller allows zero-overhead data transfers without processor intervention. controller operates independently invisibly processor core, allowing operations occur while core simultaneously executing program instructions. transfers occur between ADSP-21262's internal memory serial ports, SPI-compatible (Serial Peripheral Interface) port, (Input Data Port), Parallel Data Acquisition Port
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ADDRESS
REGISTERS 0x0000 0000 0x0003 FFFF 0x0004 0000 BLOCK SRAM (1Mbit) 0x0004 3FFF RESERVED 0x0004 4000 0x0005 7FFF 0x0005 8000 0x0005 FFFF 0x0006 0000 BLOCK SRAM Mbit) 0x0006 3FFF 0x0006 4000 0x0007 7FFF 0x0007 8000 EXTERNAL 0x0007 FFFF 0x0008 0000 ADDRESS SPACE RESERVED
LONG WORD ADDRESS SPACE
BLOCK Mbit)
ADDRESS
0x0020 0000 0x00FF FFFF 0x0100 0000
RESERVED BLOCK Mbit)
BLOCK SRAM Mbit) 0x0008 7FFF RESERVED 0x0008 8000 0x000A FFFF 0x000B 0000 0x000B FFFF 0x000C 0000 BLOCK SRAM Mbit) 0x000C 7FFF RESERVED BLOCK Mbit)3 0x000C 8000 0x000E FFFF 0x000F 0000 0x000F FFFF 0x0010 0000 RESERVED
0x02FF FFFF 0x0300 0000 0x3FFF FFFF
NORMAL WORD ADDRESS SPACE
BLOCK Mbit)
EXTERNAL MEMORY SPACE
1EXTERNAL MEMORY DIRECTLY ACCESSIBLE CORE. MUST USED READ WRITE THIS MEMORY USING PARALLEL PORT. 2BLOCK 48-BIT ADDRESS RANGE (0x000A 0000 0x000A AAAA). 3BLOCK 48-BIT ADDRESS RANGE
BLOCK SRAM Mbit) 0x0010 FFFF RESERVED BLOCK Mbit) 0x0011 0000 0x0015 FFFF 0x0016 0000 0x0017 FFFF 0x0018 0000
(0x000E 0000 0x000E AAAA). 4USE EXTERNAL ADDRESSES LISTED HERE WITH PARALLEL PORT REGISTERS. PARALLEL PORT GENERATES ADDRESS WITHIN RANGE 0x0000 0000-0x00FF FFFF.
SHORT WORD ADDRESS SPACE
BLOCK SRAM Mbit)
0x0018 FFFF RESERVED BLOCK Mbit) 0x0019 0000 0x001D FFFF 0x001E 0000 0x001F FFFF
INTERNAL MEMORY SPACE
Figure ADSP-21262 Memory
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Serial ports operate four modes: Standard serial mode Multichannel (TDM) mode mode Left-justified sample pair mode Left-justified sample pair mode mode where each frame sync cycle samples data transmitted/received-one sample high segment frame sync, other segment frame sync. Programs have control over various attributes this mode. Each serial ports supports left-justified sample pair protocols (I2S industry standard interface commonly used audio codecs, ADCs DACs), with data pins, allowing four left-justified Sample Pair channels (using stereo devices) serial port, with maximum audio channels. serial ports permit little-endian big-endian transmission formats word lengths selectable from bits bits. left-justified sample pair modes, data-word lengths selectable between bits bits. Serial ports offer selectable synchronization transmit modes well optional µ-law A-law companding selection channel basis. Serial port clocks frame syncs internally externally generated.
Timers
ADSP-21262 total four timers: core timer able generate periodic software interrupts three general-purpose timers that generate periodic interrupts independently operate three modes: Pulse Waveform Generation mode Pulse Width Count/Capture mode External Event Watchdog mode core timer configured FLAG3 Timer Expired output signal, each general-purpose timer bidirectional four registers that implement mode operation: 6-bit configuration register, 32-bit count register, 32-bit period register, 32-bit pulse width register. single control status register enables disables three general-purpose timers independently.
Based Security
ADSP-21262 security feature that provides hardware support securing user software code preventing unauthorized reading from internal code when enabled. When using this feature, does boot-load external code, executing exclusively from internal SRAM/ROM. Additionally, freely accessible JTAG port. Instead, unique 64-bit key, which must scanned through JTAG Test Access Port will assigned each customer. device will ignore wrong key. Emulation features external boot modes only available after correct scanned.
Serial Peripheral (Compatible) Interface
Serial Peripheral Interface (SPI) industry standard synchronous serial link, enabling ADSP-21262 SPI-compatible port communicate with other SPI-compatible devices. interface consisting data pins, device select pin, clock pin. full-duplex synchronous serial interface, supporting both master slave modes. port operate multimaster environment interfacing with four other SPI-compatible devices, either acting master slave device. ADSP-21262 compatible peripheral implementation also features programmable baud rates 37.5 MHz, clock phases, polarities. ADSP-21262 compatible port uses open drain drivers support multimaster configuration avoid data contention.
Program Booting
internal memory ADSP-21262 boots system power-up from 8-bit EPROM parallel port, master, slave internal boot. Booting determined Boot Configuration (BOOTCFG1-0) pins. Selection boot source controlled either master slave device, immediately begin executing from ROM.
Phase-Locked Loop
ADSP-21262 uses on-chip Phase-Locked Loop (PLL) generate internal clock core. power-up, CLKCFG1-0 pins used select ratios 16:1, 8:1, 3:1. After booting, numerous other ratios selected software control. ratios made software configurable numerator values from software configurable divisor values
Parallel Port
Parallel Port provides interfaces SRAM peripheral devices. multiplexed address data pins (AD15-0) access 8-bit devices with bits address, 16-bit devices with bits address. either mode, 16bit, maximum data transfer rate one-third core clock speed. example, clock rate MHz, this equivalent Bytes/sec. transfers used move data from internal memory. Access core also facilitated through parallel port register read/write functions. (Address Latch Enable) pins control pins parallel port.
Power Supplies
ADSP-21262 separate power supply connections internal (VDDINT), external (VDDEXT), analog (AVDD/AVSS) power supplies. internal analog supplies must meet requirement. external supply must meet requirement. external supply pins must connected same power supply. Note that analog supply (AVDD) powers ADSP-21262's clock generator PLL. produce stable clock, programs should provide external circuit filter power input
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AVDD pin. Place filter close possible pin. example circuit, Figure prevent noise coupling, wide trace analog ground (AVSS) signal install decoupling capacitor close possible pin. Note that AVSS AVDD pins specified Figure inputs SHARC analog ground plane board. VisualDSP++, enables software developer passively gather important code execution metrics without interrupting real-time characteristics program. Essentially, developer identify bottlenecks software quickly efficiently. using profiler, programmer focus those areas program that impact performance take corrective action. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert breakpoints conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory Perform source level debugging Create custom debugger windows VisualDSP++ IDDE lets programmers define manage software development. dialog boxes property pages programmers configure manage SHARC development tools, including color syntax highlighting VisualDSP++ editor. This capability permits programmers Control development tools process inputs generate outputs Maintain one-to-one correspondence with tool's command line switches VisualDSP++ Kernel (VDK) incorporates scheduling resource management tailored specifically address memory timing constraints programming. These capabilities enable engineers develop code more effectively, eliminating need start from very beginning, when developing application code. features include Threads, Critical Unscheduled regions, Semaphores, Events, Device flags. also supports Priority-based, Preemptive, Cooperative, Time-Sliced scheduling approaches. addition, designed scalable. application does specific feature, support code that feature excluded from target system. Because library, developer decide whether not. integrated into VisualDSP++ development environment, also used standard command line tools. When used, development environment assists developer with many error-prone tasks assists managing system resources, automating generation various based objects, visualizing system state, when debugging application that uses VDK. VisualDSP++ Component Software Engineering (VCSE) Analog Devices' technology creating, using, reusing software components (independent modules substantial functionality) quickly reliably assemble software applications. Download components from drop them into
VDDINT 0.01 AVDD
AVSS
Figure Analog Power (AVDD) Filter Circuit
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices Tools product line JTAG emulators uses IEEE 1149.1 JTAG test access port ADSP-21262 processor monitor control target board processor during emulation. Analog Devices Tools product line JTAG emulators provides emulation full processor speed, allowing inspection modification memory, registers, processor stacks. processor's JTAG interface ensures that emulator will affect target system loading timing. complete information Analog Devices' SHARC Tools product line JTAG emulator operation, appropriate emulator hardware user's guide.
DEVELOPMENT TOOLS
ADSP-21262 supported with complete CROSSCOREsoftware hardware development tools, including Analog Devices emulators VisualDSP++development environment. same emulator hardware that supports other SHARC processors also fully emulates ADSP-21262. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ runtime library that includes mathematical functions. point these tools C/C++ code efficiency. compiler been developed efficient translation C/C++ code assembly. SHARC architectural features that improve efficiency compiled C/C++ code. VisualDSP++ debugger number important features. Data visualization enhanced plotting package that offers significant level flexibility. This graphical representation user data enables programmer quickly determine performance algorithm. algorithms grow complexity, this capability have increasing significance designer's development schedule, increasing productivity. Statistical profiling enables programmer nonintrusively poll processor running program. This feature, unique
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application. Publish component archives from within VisualDSP++. VCSE supports component implementation C/C++ assembly language. Expert Linker visually manipulate placement code data embedded system. View memory utilization color-coded graphical form, easily move code data different areas external memory with drag mouse, examine time stack heap usage. Expert Linker fully compatible with existing Linker Definition File (LDF), allowing developer move between graphical textual environments. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting SHARC processor family. Hardware tools include SHARC processor plug-in cards. Third party software tools include libraries, real-time operating systems, block diagram design tools. these emulators, target board must include header that connects DSP's JTAG port emulator. details target board design issues including mechanical layout, single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website (www.analog.com)- site search "EE-68." This document updated regularly keep pace with improvements emulator support.
ADDITIONAL INFORMATION
This data sheet provides general overview ADSP-21262 architecture functionality. detailed information ADSP-2126x family core architecture instruction set, refer ADSP-2126x Core Manual ADSP-21160 SHARC Instruction Reference.
DESIGNING EMULATOR-COMPATIBLE BOARD (TARGET)
Analog Devices family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. Nonintrusive incircuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing.
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FUNCTION DESCRIPTIONS
ADSP-21262 definitions listed below. Inputs identified synchronous must meet timing requirements with respect CLKIN with respect TMS, TDI). Inputs identified asynchronous asserted asynchronously CLKIN TRST). pull unused inputs VDDEXT GND, except following: DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI, AD15-0 (NOTE: These pins have pull-up resistors.) following symbols appear Type column Table Asynchronous, Ground, Input, Output, Power Supply, Synchronous, (A/D) Active Drive, (O/D) Open Drain, Three-State.
Table Descriptions
AD15-0 Type I/O/T State During After Reset Three-state with pull-up enabled Function
FLAG3-0
I/O/A
Parallel Port Address/Data. ADSP-21262 parallel port corresponding unit output addresses data peripherals these multiplexed pins. multiplex state determined pin. parallel port operate either 8-bit 16-bit mode. Each 22.5 internal pull-up resistor. Address Data Modes Page details operation. 8-bit mode: automatically asserted whenever change occurs upper external address bits, A23-8; used conjunction with external latch retain values A23-8. 16-bit mode: automatically asserted whenever change occurs address bits, A15-0; used conjunction with external latch retain values A15-0. these pins flags (FLAGS15-0) (=1) SYSCTL register disable parallel port. When used input, Channel these pins parallel input data. Output only, driven Parallel Port Read Enable. asserted whenever reads 8-bit high1 16-bit data from external memory device. When AD15-0 flags, this remains deasserted. Output only, driven Parallel Port Write Enable. asserted whenever writes 8-bit high1 16-bit data external memory device. When AD15-0 flags, this remains deasserted. Output only, driven Parallel Port Address Latch Enable. asserted whenever drives low1 address parallel port address pin. reset, active high. However, reconfigured using software active low. When AD15-0 flags, this remains deasserted. Three-state Flag Pins. Each flag configured control bits either input output. input, tested condition. output, used signal external peripherals. These pins used interface slave select output during mastering. These pins also multiplexed with IRQx TIMEXP signals. master boot mode, FLAG0 slave select that must connected EPROM. FLAG0 configured slave select during master boot. When (=1) SYSCTL register, FLAG0 configured IRQ0. When (=1) SYSCTL register, FLAG1 configured IRQ1. When (=1) SYSCTL register, FLAG2 configured IRQ2. When (=1) SYSCTL register, FLAG3 configured TIMEXP, which indicates that system timer expired.
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Table Descriptions (Continued)
DAI_P20-1 Type I/O/T State During After Reset Three-state with programmable pull-up Function Digital Audio Interface Pins. These pins provide physical interface SRU. configuration registers define combination on-chip peripheral inputs outputs connected pin's output enable. configuration registers these peripherals then determine exact behavior pin. input output signal present routed these pins. provides connection from serial ports, input data port, precision clock generators, timer DAI_P20-1 pins. These pins have internal 22.5 pull-up resistors which enabled reset. These pull-ups disabled DAI_PIN_PULLUP register. Serial Peripheral Interface Clock Signal. Driven master, this signal controls rate which data transferred. master transmit data variety baud rates. SPICLK cycles once each transmitted. SPICLK gated clock that active during data transfers, only length transferred word. Slave devices ignore serial clock slave select input driven inactive (HIGH). SPICLK used shift shift data driven MISO MOSI lines. data always shifted clock edge sampled opposite edge clock. Clock polarity clock phase relative data programmable into SPICTL control register define transfer format. SPICLK 22.5 internal pull-up resistor. Serial Peripheral Interface Slave Device Select. active signal used select slave device. This input signal behaves like chip select, provided master device slave devices. multimaster mode DSP's SPIDS signal driven slave device signal master) that error occurred, some other device also trying master device. asserted when device master mode, considered multimaster error. single-master, multiple-slave configuration where flag pins used, this must tied pulled high VDDEXT master device. ADSP-21262 ADSP21262 interaction, master ADSP-21262's flag pins used drive SPIDS signal ADSP-21262 slave device. Master Slave ADSP-21262 configured master, MOSI becomes data transmit (output) pin, transmitting output data. ADSP-21262 configured slave, MOSI becomes data receive (input) pin, receiving input data. ADSP-21262 interconnection, data shifted from MOSI output master shifted into MOSI input(s) slave(s). MOSI 22.5 internal pull-up resistor. Master Slave Out. ADSP-21262 configured master, MISO becomes data receive (input) pin, receiving input data. ADSP-21262 configured slave, MISO becomes data transmit (output) pin, transmitting output data. ADSP-21262 interconnection, data shifted from MISO output slave shifted into MISO input master. MISO 22.5 internal pull-up resistor. MISO configured setting SPICTL register. Note: Only slave allowed transmit data given time. enable broadcast transmission multiple slaves, DSP's MISO disabled setting (=1) (DMISO) SPICTL register. Boot Configuration Select. Selects boot mode DSP. BOOTCFG pins must valid before reset asserted. Table Page description boot modes.
SPICLK
Three-state with pull-up enabled
SPIDS
Input only
MOSI
(O/D)
Three-state with pull-up enabled
MISO
(O/D)
Three-state with pull-up enabled
BOOTCFG1-0
Input only
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Table Descriptions (Continued)
CLKIN Type State During After Reset Input only Function Local Clock Used conjunction with XTAL. CLKIN ADSP-21262 clock input. configures ADSP-21262 either internal clock generator external clock source. Connecting necessary components CLKIN XTAL enables internal clock generator. Connecting external clock CLKIN while leaving XTAL unconnected configures ADSP-21262 external clock source such external clock oscillator. core clocked either output this clock input depending CLKCFG1-0 settings. CLKIN halted, changed, operated below specified frequency. Crystal Oscillator Terminal. Used conjunction with CLKIN drive external crystal. Core/CLKIN Ratio Control. These pins start clock frequency. Table Page description clock configuration modes. Note that operating frequency changed programming multiplier divider PMCTL register time after core comes reset. Reset Out/Local Clock Out. Drives core reset signal external device. CLKOUT also configured reset (RSTOUT). functionality switched between output clock reset setting PMCTL register. default reset out. Processor Reset. Resets ADSP-21262 known state. Upon deassertion, there 4096 CLKIN cycle latency lock. After this time, core begins program execution from hardware reset vector address. RESET input must asserted (low) power-up. Test Clock (JTAG). Provides clock JTAG boundary scan. must asserted (pulsed low) after power-up held proper operation ADSP-21262. Test Mode Select (JTAG). Used control test state machine. 22.5 internal pull-up resistor. Test Data Input (JTAG). Provides serial data boundary scan logic. 22.5 internal pull-up resistor. Test Data Output (JTAG). Serial scan output boundary scan path. Test Reset (JTAG). Resets test state machine. TRST must asserted (pulsed low) after power-up held proper operation ADSP-21262. TRST 22.5 internal pull-up resistor. Emulation Status. Must connected ADSP-21262 Analog Devices Tools product line JTAG emulators target board connector only. 22.5 internal pull-up resistor. Core Power Supply. Nominally +1.2 supplies DSP's core processor pins package, pins LQFP package). Power Supply. Nominally +3.3 pins package, pins LQFP package). Analog Power Supply. Nominally +1.2 supplies DSP's internal (clock generator). This same specifications VDDINT, except that added filtering circuitry required. more information, Power Supplies Page Analog Power Supply Return. Power Supply Return. pins package, pins LQFP package).
XTAL CLKCFG1-0
Output only2 Input only
RSTOUT/CLKOUT
Output only
RESET
Input only
TRST
Input only3 Three-state with pull-up enabled Three-state with pull-up enabled Three-state4 Three-state with pull-up enabled Three-state with pull-up enabled
(O/D)
VDDINT VDDEXT AVDD
AVSS
continuously driven will three-stated. Output only three-state driver with output path always enabled. Input only three-state driver with both output paths. Three-state three-state driver.
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ADDRESS DATA PINS FLAGS
these pins flags (FLAGS15-0) (=1) SYSCTL register disable parallel port. Table AD[15:0] Flag Mapping
AD10 AD11 AD12 AD13 AD14 AD15 Flag FLAG8 FLAG9 FLAG10 FLAG11 FLAG12 FLAG13 FLAG14 FLAG15 FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7
ADDRESS DATA MODES
following table shows functionality pins 8-bit 16-bit transfers parallel port. 8-bit data transfers, latches address bits A23-A8 when asserted, followed address bits A7-A0 data bits D7-D0 when deasserted. 16-bit data transfers, latches address bits A15-A0 when asserted, followed data bits D15-D0 when deasserted. Table Address/Data Mode Selection
Data Mode 8-bit 8-bit 16-bit 16-bit Asserted Deasserted Asserted Deasserted AD7-0 Function A15-8 D7-0 A7-0 D7-0 AD15-8 Function A23-16 A7-0 A15-8 D15-8
BOOT MODES
Table Boot Mode Selection
BOOTCFG1-0 Booting Mode Slave Boot Master Boot Parallel Port boot EPROM Internal Boot Mode (ROM code only)
CORE INSTRUCTION RATE CLKIN RATIO MODES
Table Core Instruction Rate/ CLKIN Ratio Selection
CLKCFG1-0 Core CLKIN Ratio 16:1 Reserved
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ADSP-21262 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Grade Parameter1 VDDINT AVDD VDDEXT VIH_CLKIN VIL_CLKIN TAMB
Internal (Core) Supply Voltage Analog (PLL) Supply Voltage External (I/O) Supply Voltage High Level Input Voltage2, VDDEXT Level Input Voltage2 VDDEXT High Level Input Voltage3, VDDEXT Level Input Voltage, VDDEXT Ambient Operating Temperature4, 1.14 1.14 3.13 -0.5 1.74 -0.5
1.26 1.26 3.47 VDDEXT +0.8 VDDEXT +1.28
Unit
Specifications subject change without notice. Applies input bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST. Applies input CLKIN. Thermal Characteristics Page information thermal specifications. Engineer-to-Engineer Note (No. 216) further information.
ELECTRICAL CHARACTERISTICS
Parameter1 IILPU IOZH IOZL IOZLPU IDD-INTYP AIDD
High Level Output Voltage2 Level Output Voltage2 High Level Input Current4, Level Input Current4 Level Input Current Pull-Up5 Three-State Leakage Current Three-State Leakage Current6 Three-State Leakage Current Pull-Up7 Supply Current (Internal)9, Supply Current (Analog)12 Input Capacitance13,
Test Conditions VDDEXT min, -1.0 VDDEXT min, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, VDDEXT max, VDDEXT VDDEXT max, VDDEXT max, tCCLK VDDINT TAMB +25°C AVDD MHz, TCASE 25°C,
Unit
Specifications subject change without notice. Applies output bidirectional pins: AD15-0, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL. Output Drive Currents Page typical drive current capabilities. Applies input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN. Applies input pins with 22.5 internal pull-ups: TRST, TMS, TDI. Applies three-statable pins: FLAG3-0. Applies three-statable pins with 22.5 pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI. Applies open-drain output pins: EMU, MISO, MOSI. Typical internal current data reflects nominal operating conditions. Engineer-to-Engineer Note (No. 216) further information. Characterized, tested. Characterized, tested. Applies signal pins. Guaranteed, tested.
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ABSOLUTE MAXIMUM RATINGS
Parameter Internal (Core) Supply Voltage (VDDINT)1 Analog (PLL) Supply Voltage (AVDD)1 External (I/O) Supply Voltage (VDDEXT)1 Input Voltage-0.5 VDDEXT1 Output Voltage Swing-0.5 VDDEXT1 Load Capacitance1 Storage Temperature Range1 Junction Temperature under Bias
Rating -0.3 +1.4 -0.3 +1.4 -0.3 +3.8 -65°C +150°C 125°C
Stresses greater than those listed above cause permanent damage device. These stress ratings only; functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although ADSP-21262 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
TIMING SPECIFICATIONS
ADSP-21262's internal clock multiple CLKIN) provides clock signal timing internal memory, processor core, serial ports, parallel port required read/write strobes asynchronous access mode). During reset, program ratio between DSP's internal clock frequency external (CLKIN) clock frequency with CLKCFG1-0 pins. determine switching frequencies serial ports, divide down internal clock, using programmable divider control each port (DIVx serial ports). ADSP-21262's internal clock switches higher frequencies than system input clock (CLKIN). generate internal clock, uses internal phase-locked loop (PLL). This PLL-based clocking minimizes skew between system clock (CLKIN) signal DSP's internal clock (the clock source parallel port logic pads). Note definitions various clock periods that function CLKIN appropriate ratio control (Table Table Table ADSP-21262 CLKOUT CCLK Clock Generation Operation
Timing Requirements CLKIN CCLK Description Input Clock Core Clock Calculation 1/tCK 1/tCCLK
Table Clock Periods
Timing Requirements tCCLK tSCLK tSPICLK
Description1 CLKIN Clock Period (Processor) Core Clock Period Serial Port Clock Period (tCCLK) Clock Period (tCCLK) SPIR
where: serial port-to-core clock ratio (wide range, determined SPORT CLKDIV) SPIR SPI-to-Core Clock Ratio (wide range, determined SPIBAUD register) DAI_Px Serial Port Clock SPICLK Clock
Figure shows Core CLKIN ratios 3:1, 8:1, 16:1 with external oscillator crystal. Note that more ratios possible through software using power management control register (PMCTL). more information, ADSP-2126x SHARC Core Manual. exact timing information given. attempt derive parameters from addition subtraction others. While addition subtraction would yield meaningful results individual device, values given this data sheet reflect statistical variations worst cases. Consequently, meaningful parameters derive longer times. Figure Page under Test conditions voltage reference levels.
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CLKOUT CLKIN XTAL XTAL PLLICLK 3:1, 8:1, 16:1 CCLK (CORE CLOCK)
Switching characteristics specify processor changes signals. Circuitry external processor must designed compatibility with these signal characteristics. Switching characteristics describe what processor will given circumstance. switching characteristics ensure that timing requirement device connected processor (such memory) satisfied. Timingrequirements apply signals that controlled circuitry external processor, such data input read operation. Timing requirements guarantee that processor operates correctly with other devices.
CLK-CFG [1:0]
Figure Core Clock System Clock Relationship CLKIN
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Power-Up Sequencing
timing requirements startup given Table Table Power-Up Sequencing Timing Requirements (DSP Startup)
Parameter Timing Requirements tRSTVDD tIVDDEVDD tCLKVDD tCLKRST tPLLRST RESET Before VDDINT/VDDEXT VDDINT Before VDDEXT CLKIN Valid After VDDINT/VDDEXT valid
Unit
CLKIN Valid Before RESET Deasserted Control Setup Before RESET Deasserted
Switching Characteristic tCORERST
Core Reset Deasserted After RESET Deasserted
4096tCK4,
Valid VDDINT/VDDEXT assumes that supplies fully ramped their volt rails. Voltage ramp rates vary from microseconds hundreds milliseconds depending design power supply subsystem. Assumes stable CLKIN signal, after meeting worst-case startup timing crystal oscillators. Refer crystal oscillator manufacturer's data sheet startup time. Assume maximum oscillator startup time using XTAL internal oscillator circuit conjunction with external crystal. Based CLKIN cycles. Applies after power-up sequence complete. Subsequent resets require minimum CLKIN cycles RESET held order properly initialize propagate default states pins. 4096 cycle count depends tSRST specification Table setup time met, additional CLKIN cycle added core reset time, resulting 4097 cycles maximum.
LTIP
Figure Power-Up Sequencing
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Clock Input
Table Clock Input
Parameter Timing Requirements CLKIN Period tCKL CLKIN Width tCKH CLKIN Width High tCKRF CLKIN Rise/Fall (0.4 tCCLK CCLK Period3
Unit 1602
Applies only CLKCFG1-0 default values control bits PMCTL. Applies only CLKCFG1-0 default values control bits PMCTL. changes control bits PMCTL register must meet core clock timing specification tCCLK.
CLKIN tCKH tCKL
Figure Clock Input
Clock Signals
ADSP-21262 external clock crystal. CLKIN description. programmer configure ADSP-21262 internal clock generator connecting necessary components CLKIN XTAL. Figure shows component connections used crystal operating fundamental mode. Note that clock rate achieved using 12.5 crystal multiplier ratio 16:1 (CCLK:CLKIN).
CLKIN
XTAL
NOTE: SPECIFIC CRYSTAL SPECIFIED CONTACT CRYSTAL MANUFACTURER DETAILS. CRYSTAL SELECTION MUST COMPLY WITH CLKCFG1-0
Figure Operation with 12.5 Fundamental Mode Crystal
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Reset
Table Reset
Parameter Timing Requirements tWRST RESET Pulse Width Low1 tSRST RESET Setup Before CLKIN
4tCK
Unit
Applies after power-up sequence complete. power-up, processor's internal phase-locked loop requires more than while RESET low, assuming stable CLKIN (not including start-up time external clock oscillator).
CLKIN tWRST RESET tSRST
Figure Reset
Interrupts
following timing specification applies FLAG0, FLAG1, FLAG2 pins when they configured IRQ0, IRQ1, IRQ2 interrupts. Also applies DAI_P[20:1] pins when configured interrupts. Table Interrupts
Parameter Timing Requirement tIPW IRQx Pulse Width tCCLK Unit
DAI_P20-1 (FLAG2-0) (IRQ2-0)
tIPW
Figure Interrupts
Core Timer
following timing specification applies FLAG3 when configured core timer (CTIMER). Table Core Timer
Parameter Switching Characteristic tWCTIM CTIMER Pulse Width tCCLK Unit
FLAG3 (CTIMER)
tWCTIM
Figure Core Timer
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Timer PWM_OUT Cycle Timing
following timing specification applies Timer[2:0] PWM_OUT (pulse width modulation) mode. Timer signals routed DAI_P[20:1] pins through SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table Timer[2:0] PWM_OUT Timing
Parameter Switching Characteristic tPWMO Timer[2:0] Pulse Width Output tCCLK 2(231 tCCLK Unit
tPWMO DAI_P[20:1] (TIMER[2:0])
Figure Timer[2:0] PWM_OUT Timing
Timer WDTH_CAP Timing
following timing specification applies Timer[2:0] WDTH_CAP (pulse width count capture) mode. Timer signals routed DAI_P[20:1] pins through SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table Timer[2:0] Width Capture Timing
Parameter Timing Requirement tPWI Timer[2:0] Pulse Width tCCLK 2(231 tCCLK Unit
tPWI DAI_P[20:1] (TIMER[2:0])
Figure Timer[2:0] Width Capture Timing
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Direct Routing
direct connections only (for example DAI_PB01_I DAI_PB02_O). Table Routing
Parameter Timing Requirement tDPIO Delay Input Valid Output Valid Unit
DAI_Pn
DAI_Pm
tDPIO
Figure Direct Routing
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Precision Clock Generator (Direct Routing)
This timing only valid when configured such that Precision Clock Generator (PCG) takes inputs directly from pins (via buffers) sends outputs directly pins. other cases, where PCG's Table Precision Clock Generator (Direct Routing)
Parameter Timing Requirements tPCGIW Input Clock Period tSTRIG Trigger Setup Before Falling Edge Input Clock Trigger Hold After Falling Edge Input Clock tHTRIG Switching Characteristics Output Clock Frame Sync Active Edge Delay After Input tDPCGIO Clock tDTRIG Output Clock Frame Sync Delay After Trigger Output Clock Period tPCGOW Unit
inputs outputs directly routed to/from pins (via buffers) there timing data available. timing parameters switching characteristics apply external pins (DAI_P07 DAI_P20).
tPCGOW
tPCGOW
tSTRIG
DAI_Pn PCG_TRIGx_I tHTRIG DAI_Pm PCG_EXTx_I (CLKIN) DAI_Py PCG_CLKx_O tDPCGIO tPCGIW
tPCGOW DAI_Pz PCG_FSx_O tDTRIG
Figure Precision Clock Generator (Direct Routing)
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Flags
timing specifications provided below apply FLAG[3:0] DAI_P[20:1] pins, parallel port, serial peripheral interface (SPI). Table Page more information flag use. Table Flags
Parameter Timing Requirement tFIPW FLAG[3:0] Pulse Width Switching Characteristic tFOPW FLAG[3:0] Pulse Width tCCLK Unit
tCCLK
DAI_P[20:1] (FLAG3-0IN) (AD[15:0])
tFIPW
DAI_P[20:1] (FLAG3-0OUT) (AD[15:0])
tFOPW
Figure Flags
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Memory Read-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21262 accessing external memory space. Table 8-Bit Memory Read Cycle
Parameter Timing Requirements Address/Data [7:0] Setup Before High tDRS tDRH Address/Data [7:0] Hold After High tDAD Address [15:8] Data Valid Switching Characteristics tALEW Pulse Width tALERW Deasserted Read/Write Asserted tADAS Address/Data [15:0] Setup Before Deasserted1 tADAH Address/Data [15:0] Hold After Deasserted1 Deasserted1 Address/Data[7:0] High tALEHZ Pulse Width tADRH Address/Data [15:8] Hold After High (Data Cycle Duration) tCCLK tCCLK hold cycle specified, else
Unit
tCCLK
tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK
tCCLK
reset, active high cycle. However, reconfigured software active low.
tALEW tALERW
tALEHZ tADAS tADAH tADRH
AD[15:8]
VALID ADDRESS
VALID ADDRESS
tDRS
tDRH
AD[7:0]
VALID ADDRESS
tDAD
VALID DATA
Figure Read Cycle 8-Bit Memory Timing
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Table 16-Bit Memory Read Cycle
Parameter Timing Requirements tDRS tDRH Address/Data [15:0] Setup Before High Address/Data [15:0] Hold After High Unit
Switching Characteristics tALEW Pulse Width Deasserted Read/Write Asserted tALERW tADAS Address/Data [15:0] Setup Before Deasserted1 tADAH Address/Data [15:0] Hold After Deasserted1 tALEHZ Deasserted1 Address/Data[15:0] High Pulse Width (Data Cycle Duration) tCCLK tCCLK hold cycle specified, else
tCCLK tCCLK tCCLK tCCLK tCCLK
0.5tCCLK
reset, active high cycle. However, reconfigured software active low.
tALEW tALERW
tADAS
AD[15:0] VALID ADDRESS
tADAH
tDRS
tDRH
VALID DATA
tALEHZ
Figure Read Cycle 16-Bit Memory Timing
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Memory Write-Parallel Port
these specifications asynchronous interfacing memories (and memory-mapped peripherals) when ADSP-21262 accessing external memory space. Table 8-Bit Memory Write Cycle
Parameter Switching Characteristics Pulse Width tALEW tALERW Deasserted Read/Write Asserted tADAS Address/Data [15:0] Setup Before Deasserted1 tADAH Address/Data [15:0] Hold After Deasserted Pulse Width tADWL Address/Data [15:8] Address/Data [15:8] Hold After High tADWH tALEHZ Deasserted1 Address/Data[15:0] High tDWS Address/Data [7:0] Setup Before High tDWH Address/Data [7:0] Hold After High tDAWH Address/Data High (Data Cycle Duration) tCCLK tCCLK hold cycle specified, else
tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK
Unit
0.5tCCLK
reset, active high cycle. However, reconfigured software active low.
tALERW tALEW tDAWH
tALEHZ tADAS tADAH
tADWL
tADWH
AD[15:8]
VALID ADDRESS
VALID ADDRESS tDWS tDWH
AD[7:0]
VALID ADDRESS
VALID DATA
Figure Write Cycle 8-Bit Memory Timing
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Table 16-Bit Memory Write Cycle
Parameter Switching Characteristics tALEW Pulse Width Deasserted Read/Write Asserted tALERW tADAS Address/Data [15:0] Setup Before Deasserted1 tADAH Address/Data [15:0] Hold After Deasserted1 Pulse Width tALEHZ Deasserted1 Address/Data[15:0] High tDWS Address/Data [15:0] Setup Before High tDWH Address/Data [15:0] Hold After High (Data Cycle Duration) tCCLK tCCLK hold cycle specified, else
tCCLK tCCLK tCCLK tCCLK tCCLK -0.8 tCCLK
Unit
0.5tCCLK
reset, active high cycle. However, reconfigured software active low.
tALEW tALERW
tALEHZ tADAS tADAH tDWS tDWH
AD[15:0]
VALID ADDRESS
VALID DATA
Figure Write Cycle 16-Bit Memory Timing
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Serial Ports
determine whether communication possible between devices clock speed following specifications must confirmed: frame sync delay frame sync setup hold, data delay data setup hold, SCLK width. Table Serial Ports-External Clock
Parameter Timing Requirements tSFSE Setup Before SCLK (Externally Generated Either Transmit Receive Mode)1 tHFSE Hold After SCLK (Externally Generated Either Transmit Receive Mode)1 tSDRE Receive Data Setup Before Receive SCLK1 tHDRE Receive Data Hold After SCLK1 tSCLKW SCLK Width tSCLK SCLK Period Switching Characteristics tDFSE Delay After SCLK (Internally Generated Either Transmit Receive Mode)2 tHOFSE Hold After SCLK (Internally Generated Either Transmit Receive Mode)2 tDDTE Transmit Data Delay After Transmit SCLK2 tHDTE Transmit Data Hold After Transmit SCLK2
Serial port signals (SCLK, DxA,/DxB) routed DAI_P[20:1] pins using SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins.
Unit
Referenced sample edge. Referenced drive edge.
Table Serial Ports-Internal Clock
Parameter Timing Requirements tSFSI Setup Before SCLK (Externally Generated Either Transmit Receive Mode)1 tHFSI Hold After SCLK (Externally Generated Either Transmit Receive Mode)1 tSDRI Receive Data Setup Before SCLK1 tHDRI Receive Data Hold After SCLK1 Switching Characteristics tDFSI Delay After SCLK (Internally Generated Transmit Mode)2 Hold After SCLK (Internally Generated Transmit Mode)2 tHOFSI tDFSI Delay After SCLK (Internally Generated Receive Mode)2 tHOFSI Hold After SCLK (Internally Generated Receive Mode)2 tDDTI Transmit Data Delay After SCLK2 tHDTI Transmit Data Hold After SCLK2 tSCLKIW Transmit Receive SCLK Width
Unit
-1.0 -1.0 -1.0 0.5tSCLK 0.5tSCLK
Referenced sample edge. Referenced drive edge.
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Table Serial Ports-Enable Three-State
Parameter Switching Characteristics tDDTEN Data Enable from External Transmit SCLK1 Data Disable from External Transmit SCLK1 tDDTTE tDDTIN Data Enable from Internal Transmit SCLK1
Unit
Referenced drive edge.
Table Serial Ports-External Late Frame Sync
Parameter Switching Characteristics tDDTLFSE Data Delay from Late External Transmit External Receive with tDDTENFS Data Enable
Unit
tDDTLFSE tDDTENFS parameters apply left-justified sample pair mode well serial mode,
EXTERNAL RECEIVE WITH
DIA_P[20:0] (SCLK)
DRIVE
SAMPLE
DRIVE
tSFSE/I
DIA_P[20:0] (FS)
tHFSE/I
tDDTENFS
DIA_P[20:0] (DATA CHANNEL A/B)
tDDTE/I tHDTE/I
tDDTLFSE
LATE EXTERNAL TRANSMIT DRIVE SAMPLE DRIVE
DIA_P[20:0] (SCLK)
tSFSE/I
DIA_P[20:0] (FS)
tHFSE/I
tDDTENFS
DIA_P[20:0] (DATA CHANNEL A/B)
tDDTE/I tHDTE/I
tDDTLFSE
NOTE SERIAL PORT SIGNALS (SCLK, DATA CHANNEL A/B) ROUTED DAI_P[20:1] PINS USING SRU. TIMING SPECIFICATIONS PROVIDED HERE VALID DAI_P[20:1] PINS.
Figure External Late Frame Sync1
This figure reflects changes made support left-justified sample pair mode.
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DATA RECEIVE- INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA RECEIVE- EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
DAI_P[20:1] (SCLK) DAI_P[20:1] (SCLK)
tSCLKW
tDFSI tHOFSI
DAI_P[20:1] (FS)
tSFSI
tHFSI
DAI_P[20:1] (FS)
tDFSE tHOFSE tSFSE
tHFSE
tSDRI
DAI_P[20:1] (DATA CHANNEL A/B)
tHDRI
DAI_P[20:1] (DATA CHANNEL A/B)
tSDRE
tHDRE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DATA TRANSMIT INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE
tSCLKIW
DAI_P[20:1] (SCLK) DAI_P[20:1] (SCLK)
tSCLKW
tDFSI tHOFSI
DAI_P[20:1] (FS)
tSFSI
tHFSI
DAI_P[20:1] (FS)
tDFSE tHOFSE tSFSE tHFSE
tHDTI
DAI_P[20:1] (DATA CHANNEL A/B)
tDDTI
DAI_P[20:1] (DATA CHANNEL A/B)
tHDTE
tDDTE
NOTE: EITHER RISING EDGE FALLING EDGE SCLK (EXTERNAL), SCLK (INTERNAL) USED ACTIVE SAMPLING EDGE.
DRIVE EDGE DAI_P[20:1] SCLK (EXT)
DRIVE EDGE
SCLK tDDTEN tDDTTE
DAI_P[20:1] (DATA CHANNEL A/B)
DRIVE EDGE
DAI_P[20:1] SCLK (INT)
tDDTIN
DAI_P[20:1] (DATA CHANNEL A/B)
Figure Serial Ports
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Input Data Port (IDP)
timing requirements given Table Signals (SCLK, SDATA) routed DAI_P[20:1] pins using SRU. Therefore, timing specifications provided below valid DAI_P[20:1] pins. Table Input Data Port
Parameter Timing Requirements tSISFS Setup Before SCLK Rising Edge1 tSIHFS Hold After SCLK Rising Edge1 SData Setup Before SCLK Rising Edge1 tSISD tSIHD SData Hold After SCLK Rising Edge1 tIDPCLKW Clock Width tIDPCLK Clock Period
Unit
DATA, SCLK, come from pins. SCLK also come Precision Clock Generators (PCG) SPORTs. PCG's input either CLKIN pins.
SAMPLE EDGE tIDPCLKW DAI_P[20:1] (SCLK) tSIHFS
tSISFS DAI_P[20:1] (FS) tSISD DAI_P[20:1] (SDATA)
tSIHD
Figure Master Timing
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Parallel Data Acquisition Port (PDAP)
timing requirements PDAP provided Table PDAP parallel mode operation Channel IDP. details operation IDP, chapter ADSP-2126x Peripherals Manual. Note that Table Parallel Data Acquisition Port (PDAP)
Parameter Timing Requirements tSPCLKEN PDAP_CLKEN Setup Before PDAP_CLK Sample Edge1 tHPCLKEN PDAP_CLKEN Hold After PDAP_CLK Sample Edge1 PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge1 tPDSD tPDHD PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge1 tPDCLKW Clock Width tPDCLK Clock Period Switching Characteristics tPDHLDD Delay PDAP Strobe After Last PDAP_CLK Capture Edge Word tPDSTRB PDAP Strobe Pulse Width
most significant bits external PDAP data provided through either parallel port AD[15:0] DAI_P[20:5] pins. remaining bits only sourced through DAI_P[4:1]. timing below valid DAI_P[20:1] pins AD[15:0] pins.
Unit
tCCLK tCCLK
Source pins DATA ADDR[7:0], DATA[7:0], pins. Source pins SCLK are: pins, CLKIN through PCG, pins through PCG.
SAMPLE EDGE
PDCLK PDCLKW
DAI_P[20:1] (PDAP_CLK)
SPCLKEN
DAI_P[20:1] (PDAP_CLKEN)
HPCLKEN
PDSD
DATA
PDHD
DAI_P[20:1] (PDAP_STROBE)
tPDSTRB PDHLDD
Figure PDAP Timing
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Interface-Master
Table Interface Protocol Master Switching Timing Specifications
Parameter Switching Characteristics tSPICLKM Serial Clock Cycle tSPICHM Serial Clock High Period tSPICLM Serial Clock Period tDDSPIDM SPICLK Edge Data Valid (Data Delay Time) tHDSPIDM SPICLK Edge Data Valid (Data Hold Time) tSDSCIM FLAG3-0 (SPI device select) First SPICLK Edge Last SPICLK Edge FLAG3-0 High tHDSM tSPITDM Sequential Transfer Delay Timing Requirements tSSPIDM tHSPIDM tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK Unit
Data Input Valid SPICLK Edge (Data Input Setup Time) SPICLK Last Sampling Edge Data Input Valid
FLAG3-0 (OUTPUT)
tSDSCIM
SPICLK (OUTPUT)
tSPICHM
tSPICLM
tSPICLKM
tHDSM
tSPIT
tSPICLM
SPICLK (OUTPUT)
tSPICHM
MOSI (OUTPUT)
HDSPIDM
CPHASE MISO (INPUT) VALID
tSSPIDM tHSPIDM
VALID
tDDSPIDM
MOSI (OUTPUT) CPHASE MISO (INPUT)
tHDSPIDM
tSSPIDM
VALID
tHSPIDM
VALID
Figure Master Timing
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Interface-Slave
Table Interface Protocol-Slave Switching Timing Specifications
Parameter Switching Characteristics tDSOE SPIDS Assertion Data Active tDSDHI SPIDS Deassertion Data High Impedance tDDSPIDS SPICLK Edge Data Valid (Data Delay Time) tHDSPIDS SPICLK Edge Data Valid (Data Hold Time) tDSOV SPIDS Assertion Data Valid (CPHASE Timing Requirements tSPICLKS tSPICHS tSPICLS tSDSCO tCCLK tCCLK Unit
tHDS tSSPIDS tHSPIDS tSDPPW
Serial Clock Cycle Serial Clock High Period Serial Clock Period SPIDS Assertion First SPICLK Edge CPHASE CPHASE Last SPICLK Edge SPIDS Asserted CPHASE Data Input Valid SPICLK Edge (Data Input Setup Time) SPICLK Last Sampling Edge Data Input Valid SPIDS Deassertion Pulse Width (CPHASE
tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK tCCLK
SPIDS (INPUT)
SPICLK (INPUT)
tSPICLS
tSPICL tHDS tSDPPW
tSDSCO
SPICLK (INPUT)
tSPICLS
tSPICHS
tDSOE
tDDSPIDS tDDSPIDS
tDSDHI tHDSPIDS
MISO (OUTPUT) CPHASE MOSI (INPUT)
tHSPIDS tSSPIDS
VALID
tSSPIDS
VALID
tDSOV
MISO (OUTPUT) CPHASE MOSI (INPUT)
tDDSPIDS
tHDSPIDS
tDSDHI
tSSPIDS
VALID VALID
tHSPIDS
Figure Slave Timing
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ADSP-21262
JTAG Test Access Port Emulation
Table JTAG Test Access Port Emulation
Parameter Timing Requirements tTCK Period tSTAP TDI, Setup Before High tHTAP TDI, Hold After High tSSYS System Inputs Setup Before High1 tHSYS System Inputs Hold After High1 tTRSTW TRST Pulse Width Switching Characteristics tDTDO Delay from System Outputs Delay After Low2 tDSYS
4tCK
Unit
System Inputs AD15-0, SPIDS, CLKCFG1-0, RESET, BOOTCFG1-0, MISO, MOSI, SPICLK, DAI_Px, FLAG3-0 System Outputs MISO, MOSI, SPICLK, DAI_Px, AD15-0, FLAG3-0, CLKOUT, EMU, ALE.
tTCK tSTAP tDTDO tSSYS SYSTEM INPUTS tDSYS SYSTEM OUTPUTS tHSYS tHTAP
Figure IEEE 11499.1 JTAG Test Access Port
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ADSP-21262
OUTPUT DRIVE CURRENTS
Figure shows typical characteristics output drivers ADSP-21262. curves represent current drive capability output drivers function output voltage.
CAPACITIVE LOADING
Output delays holds based standard capacitive loads: pins (see Figure 29). Figure shows graphically output delays holds vary with load capacitance. graphs Figure Figure Figure linear outside ranges shown Typical Output Delay Load Capacitance Typical Output Rise Time (20% 80%, Min) Load Capacitance.
SOURCE (VDDEXT) CURRENT (mA)
3.3V,
3.47V,
12.0
3.11V,
10.0
RISE FALL TIMES (ns)
RISE 0.0904x 1.9426 FALL
3.3V, 3.11V,
3.47V, SWEEP (VDDEXT) VOLTAGE
0.0722x 1.4042
Figure ADSP-21262 Typical Drive
TEST CONDITIONS
signal specifications (timing parameters) appear Table Page through Table Page These include output disable time, output enable time, capacitive loading. Timing measured signals when they cross level described Figure delays nanoseconds) measured between point that first signal reaches point that second signal reaches
RISE FALL TIMES (ns)
LOAD CAPACITANCE (pF)
Figure Typical Output Rise/Fall Time (20%-80%, VDDEXT Max)
RISE 0.0915x 2.2207 FALL
OUTPUT 30pF
1.5V
0.0728x +1.6336
Figure Equivalent Device Loading Measurements (Includes Fixtures)
LOAD CAPACITANCE (pF)
INPUT 1.5V OUTPUT
Figure Typical Output Rise/Fall Time (20%-80%, VDDEXT Min)
1.5V
Figure Voltage Reference Levels Measurements
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ADSP-21262
where:
OUTPUT DELAY HOLD (ns)
Ambient Temperature Values provided package comparison design considerations when external heat sink required.
0.0904x 2.712
Values provided package comparison design considerations. Table Thermal Characteristics 136-Ball BGA1
Parameter
Condition Airflow Airflow Airflow
LOAD CAPACITANCE (pF)
Figure Typical Output Delay Hold Load Capacitance Ambient Temperature)
Airflow Airflow Airflow
Typical 28.2 24.4 23.3 20.1
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
ENVIRONMENTAL CONDITIONS
ADSP-21262 processor rated performance over commercial temperature range, TAMB 70°C.
thermal characteristics values provided this table modeled values.
Table Thermal Characteristics 144-Lead LQFP1
Parameter
THERMAL CHARACTERISTICS
Table Table airflow measurements comply with JEDEC standards JESD51-2 JESD51-6 junction-toboard measurement complies with JESD51-8. junction-tocase measurement complies with MIL-STD-883. measurements 2S2P JEDEC test board. determine Junction Temperature device while application PCB, use: CASE
Condition Airflow Airflow Airflow Airflow Airflow Airflow
Typical 32.5 28.9 27.8
Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W
thermal characteristics values provided this table modeled values.
where: Junction temperature TCASE Case temperature (°C) measured center package Junction-to-Top package) characterization parameter Typical value from Table Table Power dissipation (see Note #216) Values provided package comparison design considerations. used first order approximation equation:
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ADSP-21262
136-BALL CONFIGURATIONS
following table shows ADSP-21262's names their default function after reset parentheses). Figure Page shows package assignments. Table 136-Ball Assignments
Name CLKCFG0 XTAL CLKOUT MOSI MISO SPIDS VDDINT VDDINT FLAG3 Name CLKCFG1 VDDEXT CLKIN TRST AVSS AVDD VDDEXT SPICLK RESET VDDINT FLAG1 FLAG0 FLAG2 DAI_P20 (SFS45) Name BOOTCFG1 BOOTCFG0 VDDINT Name VDDINT VDDINT
VDDINT VDDEXT DAI_P19 (SCLK45)
VDDEXT DAI_P18 (SD5B) DAI_P17 (SD5A)
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Table 136-Ball Assignments (Continued)
Name VDDINT DAI_P16 (SD4B) AD15 VDDINT VDDEXT VDDINT DAI_P2 (SD0B) VDDEXT DAI_P4 (SFS0) VDDINT VDDINT DAI_P10 SD2B) Name VDDINT DAI_P15 (SD4A) AD14 AD13 AD12 AD11 AD10 DAI_P1 (SD0A) DAI_P3 (SCLK0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) DAI_P8 (SFS1) DAI_P9 (SD2A) DAI_P11 (SD3A) Name DAI_P14 (SFS23) Name DAI_P12 (SD3B) DAI_P13 (SCLK23)
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ADSP-21262
VDDINT VDDEXT GND* AVSS AVDD SIGNALS
*USE CENTER BLOCK GROUND PINS PROVIDE THERMAL PATHWAYS YOUR PRINTED CIRCUIT BOARD'S GROUND PLANE.
Figure 136-Ball Assignments (Bottom View, Summary)
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ADSP-21262
144-LEAD LQFP CONFIGURATIONS
following table shows ADSP-21262's names their default function after reset parentheses). Table 144-Lead LQFP Assignments
Name VDDINT CLKCFG0 CLKCFG1 BOOTCFG0 BOOTCFG1 VDDEXT VDDINT VDDINT VDDINT FLAG0 FLAG1 VDDINT VDDEXT VDDINT VDDINT VDDEXT VDDINT LQFP Name VDDINT AD15 AD14 AD13 VDDEXT AD12 VDDINT AD11 AD10 DAI_P1 (SD0A) VDDINT DAI_P2 (SD0B) DAI_P3 (SCLK0) VDDEXT VDDINT DAI_P4 (SFS0) DAI_P5 (SD1A) DAI_P6 (SD1B) DAI_P7 (SCLK1) VDDINT VDDINT DAI_P8 (SFS1) DAI_P9 (SD2A) VDDINT LQFP LQFP VDDEXT VDDINT DAI_P10 (SD2B) DAI_P11 (SD3A) DAI_P12 (SD3B) DAI_P13 (SCLK23) DAI_P14 (SFS23) DAI_P15 (SD4A) VDDINT DAI_P16 (SD4B) DAI_P17 (SD5A) DAI_P18 (SD5B) DAI_P19 (SCLK45) VDDINT VDDEXT DAI_P20 (SFS45) VDDINT FLAG2 FLAG3 VDDINT VDDINT VDDINT VDDINT VDDINT VDDINT Name Name VDDINT VDDINT VDDINT VDDEXT VDDINT VDDINT RESET SPIDS VDDINT SPICLK MISO MOSI VDDINT VDDEXT AVDD AVSS CLKOUT TRST CLKIN XTAL VDDEXT LQFP
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ADSP-21262
PACKAGE DIMENSIONS
ADSP-21262 available 136-ball package 144-lead LQFP package shown Figure Figure
12.00
10.40 0.80
INDICATOR
0.80
VIEW 1.70 DETAIL
BOTTOM VIEW 1.31 1.21 1.10
0.25 DIMENSIONS MILIMETERS (MM). ACTUAL POSITION BALL GRID WITHIN 0.150 IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.08 IDEAL POSITION RELATIVE BALL GRID. COMPLIANT JEDEC STANDARD MO-205-AE, EXCEPT BALL DIAMETER. CENTER DIMENSIONS NOMINAL.
0.50 0.46 0.40 (BALL DIAMETER)
SEATING PLANE 0.12 (BALL COPLANARITY)
DETAIL
Figure 136-Ball (BC-136)
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ADSP-21262
22.00 20.00
INDICATOR 0.27 0.22 0.17 0.50 (LEAD PITCH)
SEATING PLANE 0.08 (LEAD COPLANARITY) 0.15 0.05 1.45 1.40 1.35 1.60 DIMENSIONS MILLIMETERS COMPLY WITH JEDEC STANDARD MS-026-BFB. ACTUAL POSITION EACH LEAD WITHIN 0.08 IDEAL POSITION WHEN MEASURED LATERAL DIRECTION. CENTER DIMENSIONS NOMINAL.
0.75 0.60 0.45
DETAIL
DETAIL
VIEW (PINS DOWN)
Figure 144-Lead LQFP (ST-144)
ORDERING GUIDE
Part Number ADSP-21262SKBC-200 ADSP-21262SKBCZ2002 ADSP-21262SKSTZ2002
Ambient Temperature Range +70°C +70°C +70°C
Instruction Rate
On-Chip SRAM Mbit Mbit Mbit
Mbit Mbit Mbit
Operating Voltage Package1 INT/3.3 INT/3.3 INT/3.3 136-Lead 136-Lead 144-Lead LQFP
indicates Ball Grid Array package. indicates Profile Quad Flat package. Pb-free part. more information about lead-free package offerings, please visit www.analog.com.
2004 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D04442-0-4/04(A)
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SUMMARY High performance 32-bit/40-bit floating-point processor o

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