Data Sheet March, 2002 FEATURES 25ns maximum (3.3 volt supply) ad

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Data Sheet March, 2002 FEATURES 25ns maximum (3.3 volt supply) ad

Datasheet Thumbnail

Top Searches for this datasheet

QCOTSUT8Q512K32 16Megabit SRAM
Data Sheet March, 2002
FEATURES 25ns maximum (3.3 volt supply) address access time contains four 512K industry-standard asynchronous SRAMs; control architecture allows operation 32-bit data width compatible inputs output levels, three-state bidirectional data Typical radiation performance Total dose: 50krads Immune MeV-cm2 TH(0.25) MeV-cm 2/mg Saturated Cross Section bit, 5.0E-9 <1E-8 errors/bit-day, Adams geosynchronous heavy Packaging options: 68-lead dual cavity ceramic quad flatpack (CQFP) (weight 7.37 grams) Standard Microcircuit Drawing 5962-01533 compliant part
INTRODUCTION QCOTSUT8Q512K32 Quantified Commercial Off-the-Shelf product high-performance byte (16Mbit) CMOS static multi-chip module (MCM), organized four individual 524,288 SRAMs with common output enable. Memory expansion provided active chip enable (En), active output enable (G), three-state drivers. This device powerdown feature that reduces power consumption more than when deselected. Writing each memory accomplished taking chip enable (En) input write enable inputs LOW. Data pins then written into location specified address pins through Reading from device accomplished taking chip enable (En) output enable while forcing write enable (Wn) HIGH. Under these conditions, contents memory location specified address pins will appear pins. input/output pins placed high impedance state when device deselected HIGH), outputs disabled HIGH), during write operation LOW). Perform accesses making along with common input combination discrete memory die.
A(18:0)
512K
512K
512K
512K
DQ(31:24) DQ3(7:0)
DQ(23:16) DQ2(7:0)
DQ(15:3) DQ1(7:0)
DQ(7:0) DQ0(7:0)
Figure UT8Q512K32 SRAM Block Diagram
DEVICE OPERATION Each UT8Q512K32 three control inputs called Enable (En), Write Enable (Wn), Output Enable (G); address inputs, A(18:0); eight bidirectional data lines, DQ(7:0). device enable (En) controls device selection, active, standby modes. Asserting enables device, causes rise active value, decodes address inputs each memory selecting 2,048,000 byte memory. controls read write operations. During read cycle, must asserted enable outputs. Table Device Operation Truth Table
DQ0(0) DQ1(0) DQ2(0) DQ3(0) DQ4(0) DQ5(0) DQ6(0) DQ7(0) DQ0(1) DQ1(1) DQ2(1) DQ3(1) DQ4(1) DQ5(1) DQ6(1) DQ7(1) View DQ0(2) DQ1(2) DQ2(2) DQ3(2) DQ4(2) DQ5(2) DQ6(2) DQ7(2) DQ0(3) DQ1(3) DQ2(3) DQ3(3) DQ4(3) DQ5(3) DQ6(3) DQ7(3)
Mode 3-state Data 3-state Data
Mode Standby Write Read2 Read
Figure 25ns SRAM Pinout (68)
NAMES A(18:0) DQ(7:0) Address Data Input/Output Device Enable WriteEnable Output Enable Power Ground
Notes: defined "don't care" condition. Device active; outputs disabled.
READ CYCLE combination greater than (min) with less than (max) defines read cycle. Read access time measured from latter device enable, output enable, valid address valid data output. SRAM read Cycle Address Access initiated change address inputs while chip enabled with asserted deasserted. Valid data appears data outputs DQn(7:0) after specified AVQV satisfied. Outputs remain active throughout entire cycle. long device enable output enable active, address inputs change rate equal minimum read cycle time AVAV SRAM read Cycle Chip Enable-controlled Access initiated going active while remains asserted, remains deasserted, addresses remain stable entire cycle. After specified ETQV satisfied, eight-bit word addressed A(18:0) accessed appears data outputs DQn(7:0). SRAM read Cycle Output Enable-controlled Access initiated going active while asserted, deasserted, addresses stable. Read access time tGLQV unless AVQV tETQV have been satisfied.
WRITE CYCLE combination less than VIL(max) less than VIL(max) defines write cycle. state "don't care" write cycle. outputs placed high-impedance state when eitherG greater than IH(min), when less than (max). Write Cycle Write Enable-controlled Access defined write terminated going high, with still active. write pulse width defined tWLWH when write initiated byWn, ETWH when write initiated Unless outputs have been previously placed highimpedance state byG, user must wait WLQZ before applying data eight bidirectional pins DQn(7:0) avoid contention. Write Cycle Chip Enable-controlled Access defined write terminated former going inactive. write pulse width defined tWLEF when write initiated ETEF when write initiated going active. initiated write, unless outputs have been previously placed high-impedance state user must wait tWLQZ before applying data eight bidirectional pins DQn(7:0) avoid contention.
TYPICAL RADIATION HARDNESS UT8Q512K32 SRAM incorporates features which allow operation limited radiation environment. Table Typical Radiation Hardness Design Specifications Total Dose Heavy Error Rate <1E-8 krad(Si) nominal Errors/Bit-Day
Notes: SRAM will latchup during radiation exposure under recommended operating conditions. worst case particle environment, Geosynchronous orbit, mils Aluminum.
ABSOLUTE MAXIMUM RATINGS1 (Referenced SYMBOL TSTG PARAMETER supply voltage Voltage Storage temperature Maximum power dissipation Maximum junction temperature Thermal resistance, junction-to-case3 input current LIMITS -0.5 4.6V -0.5 4.6V +150°C 1.0W (per byte) +150°C 10°C/W
Notes: Stresses outside listed absolute maximum ratings cause permanent damage device. This stress rating only, functional operation device these other conditions beyond limits indicated operational sections this specification recommended. Exposure absolute maximum rating conditions extended periods affect device reliability performance. Maximum junction temperature increased +175°C during burn-in steady-static life. Test MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER Positive supply voltage Case temperature range input voltage LIMITS 3.6V +125°C
ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL VOH1 VOH2 PARAMETER High-level input voltage Low-level input voltage Low-level output voltage Low-level output voltage High-level output voltage High-level output voltage Input capacitance Bidirectional capacitance Input leakage current Three-state output leakage current (CMOS) (CMOS) 8mA, =3.0V 200µA,VDD =3.0V -4mA,VDD =3.0V -200µA,VDD =3.0V 1MHz 1MHz (max) (max) (max) (OP) Short-circuit output current Supply current operating 1MHz (per byte) Inputs: 0.8V, 2.0V IOUT (max) Inputs: 0.8V, 2.0V IOUT (max) IDD2 (SB) Nominal standby supply current @0MHz (per byte) Inputs: IOUT 0.5, (max) 0.5V
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Measured only initial qualification after process design changes that could affect input/output capacitance. Supplied design limit guaranteed tested. more than output shorted time maximum duration second.
CONDITION
UNIT
0.08 DD-0.10
DD1(OP)
Supply current operating @40MHz (per byte)
-40°C 25°C +125°C
CHARACTERISTICS READ CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL tAVAV tAVQV tAXQX tGLQX tGLQV tGHQZ tETQX tETQV tEFQZ Read cycle time Read access time Output hold time G-controlled Output Enable time G-controlled Output Enable time (Read Cycle G-controlled output three-state time En-controlled Output Enable time En-controlled access time En-controlled output three-state time PARAMETER UNIT
Notes: Post-radiation performance guaranteed MIL-STD-883 Method 1019. Functional test. Three-state defined 300mV change from steady-state output voltage. (enable true) notation refers falling edge immunity does affect read parameters. (enable false) notation refers rising edge immunity does affect read parameters.
High Active Levels
Active High Levels
VLOAD 300mV VLOAD VLOAD 300mV
300mV
300mV
Figure 3-Volt SRAM Loading
tAVAV A(18:0)
DQn(7:0)
Previous Valid Data
Valid Data tAVQV
Assumptions: andG (max) (min)
tAXQX Figure SRAM Read Cycle Address Access
A(18:0) ETQV DQn(7:0) tETQX tEFQZ
DATA VALID
Assumptions: (max) (min)
Figure SRAM Read Cycle Chip Enable-Controlled Access
AVQV A(18:0) tGHQZ tGLQX DQn(7:0)
Assumptions: (max) andW (min)
DATA VALID
tGLQV
Figure SRAM Read Cycle Output Enable-Controlled Access
CHARACTERISTICS WRITE CYCLE (Pre/Post-Radiation)* (-40°C +125°C) 3.3V 0.3) SYMBOL tAVAV tETWH tAVET tAVWL tWLWH tWHAX tEFAX tWLQZ tWHQX2 tETEF tDVWH tWHDX2 tWLEF tDVEF tEFDX tAVWH tWHWL1 Write cycle time Device Enable write Address setup time write controlled) Address setup time write controlled) Write pulse width Address hold time write controlled) Address hold time Device Enable controlled) controlled three-state time controlled Output Enable time Device Enable pulse width controlled) Data setup time Data hold time Device Enable controlled write pulse width Data setup time Data hold time Address valid write Write disable time PARAMETER UNIT
Notes: Post-radiation performance guaranteed 25°C MIL-STD-883 Method Functional test performed with outputs disabled high). Three-state defined 300mV change from steady-state output voltage
A(18:0) AVAV2 tAVWH ETWH tAVWL Qn(7:0) tWLQZ Dn(7:0)
Assumptions: (max). (min) then Qn(8:0) will three-state entire cycle. high AVAV cycle. APPLIED DATA
WHWL tWHAX
WLWH
tWHQX
tDVWH
tWHDX
Figure SRAM Write Cycle Write Enable Controlled Access
tAVAV A(18:0) AVET tETEF tEFAX
AVET tETEF tWLEF
APPLIED DATA
tEFAX
Dn(7:0)
WLQZ Qn(7:0)
DVEF
EFDX
Assumptions Notes: (max). (min) then Qn(7:0) will three-state entire cycle. Either scenario above occur. high AVAV cycle.
Figure SRAM Write Cycle Chip Enable Controlled Access
CMOS DD-0.05V ohms LOAD 1.55 0.5V 50pF Input Pulses
Notes: 50pF including scope probe test socket capacitance. Measurement data output occurs high high transition mid-point (i.e., CMOS input DD/2).
Figure Test Loads Input Waveforms
DATA RETENTION MODE
2.0V
Figure Data Retention Waveform
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Rentention Test) SYMBOL PARAMETER tEFR tR1,3 data retention Data retention current (per byte) Chip select data retention time Operation recovery time
MINIMUM tAVAV
MAXIMUM -2.0
UNIT
Notes: .2V, other inputs Data retention current 25oC. guaranteed tested. T=-40
DATA RETENTION CHARACTERISTICS (Pre/Post-Irradiation) Second Data Retention Test, TC=-40oC +125oC) SYMBOL tEFR2, tR2, PARAMETER data retention Chip select data retention time Operation recovery time MINIMUM tAVAV MAXIMUM UNIT
Notes: Performed (min) (max). other inputs guaranteed tested.
PACKAGING
Notes: Package shipped with non-conductive strip (NCS). Leads trimmed. Total weight approx. 7.37g.
Figure 68-pin Ceramic FLATPACK
ORDERING INFORMATION 512K32 16Megabit SRAM MCM:
UT8Q512K32
Lead Finish: Gold
Screening: Prototype flow Extended Industrial Temperature Range Flow (-40 +125o
Package Type: 68-lead dual cavity CQFP
Device Type: 25ns access, 3.3V operation Aeroflex UTMC Core Part Number
Notes: Prototype flow UTMC Manufacturing Flows Document. Tested only. Lead finish GOLD ONLY. Extended Industrial Temperature Range Flow UTMC Manufacturing Flows document. Devices tested +125 Radiation neither tested guaranteed. Gold lead finish only.
512K32 16Megabit SRAM MCM:
5962 01533
Lead Finish: Gold
Case Outline: 68-lead dual cavity CQFP Class Designator: Class Class
Device Type 25ns access time, 3.3V operation, Extended Industrial Temp (-40 +125o
Drawing Number: 01533 Total Dose (10krad(Si)) (50krad(Si)) (contact factory) (30krad(Si)) (contact factory) Federal Stock Class Designator: Options
Notes: Total dose radiation must specified when ordering. available without radiation hardening. Gold lead finish only. Only Extended Industrial Temperature -40C +125C. military temp. test available.

Data Sheet March, 2002 FEATURES 25ns maximum (3.3 volt supply) ad

Top Searches for this datasheet

Other recent searches