FQS4900 Dual P-Channel, Logic Level MOSFET General Descripti
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FQS4900
FQS4900
Dual P-Channel, Logic Level MOSFET
General Description
These dual P-channel enhancement mode power field effect transistors produced using Fairchild's proprietary, planar stripe, DMOS technology. This advanced technology been especially tailored minimize on-state resistance, provide superior switching performance, withstand high energy pulse avalanche commutation mode. This device well suited high interface telephone sets.
Features
N-Channel 1.3A, 60V, RDS(on) 0.55 RDS(on) 0.65 P-Channel -0.3A, -300V, RDS(on) 15.5 RDS(on) gate charge typical N-Channel typical P-Channel Fast switching Improved dv/dt capability
Absolute Maximum Ratings
Symbol VDSS VGSS dv/dt TSTG
25°C unless otherwise noted
Parameter Drain-Source Voltage Continuous 25°C) Drain Current Continuous 70°C) Drain Curent Pulsed
(Note
N-Channel 0.82
(Note
P-Channel -300 -0.3 -0.19 -1.2
Units V/ns
Gate-Source Voltage Peak Diode Recovery dv/dt Power Dissipation 25°C) 70°C) Operating Storage Temperature Range
+150
Thermal Characteristics
Symbol Parameter Thermal Resistance, Junction-to-Ambient -Max 62.5 Units °C/W
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Electrical Characteristics
Symbol Parameter
25°C unless otherwise noted
Test Conditions
Type
Units
Characteristics
BVDSS IDSS Drain-Source Breakdown Voltage -250 Zero Gate Voltage Drain Current 55°C -300 -240 55°C IGSSF IGSSR Gate-Body Leakage Current, Forward Gate-Body Leakage Current, Reverse N-Ch P-Ch N-Ch P-Ch -300 -100
Characteristics
VGS(th) RDS(on) Gate Threshold Voltage Static Drain-Source On-Resistance 0.65 0.65 -0.15 -0.15 Forward Transconductance 0.65 -0.15 N-Ch P-Ch N-Ch P-CH N-CH P-CH -1.0 -0.39 0.46 11.2 11.4 1.95 -1.95 0.55 0.65 15.5
Switching Characteristics
td(on) td(off) Turn-On Delay Time Turn-On Rise Time Turn-Off Delay Time Turn-Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge N-Channel P-Channel -150 -0.3 N-Channel P-Channel -240 -0.3 N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch -5.7 0.28 0.42 0.82
Drain-Source Diode Characteristics Maximum Ratings
Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage -0.3
Notes: Repetitive Rating Pulse width limited maximum junction temperature Pulse Test Pulse width 300µs, Duty cycle Essentially independent operating temperature
N-Ch P-Ch N-Ch P-Ch
-0.3 -4.0
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Typical Characteristics N-Channel
Drain Current
Drain Current
10.0 Bottom
Notes Pulse Test
Notes Pulse Test
VDS, Drain-Source Voltage
VGS, Gate-Source Voltage
Figure On-Region Characteristics
Figure Transfer Characteristics
RDS(ON) Drain-Source On-Resistance
Reverse Drain Current
Notes Pulse Test
Note
Drain Current
VSD, Source-Drain voltage
Figure On-Resistance Variation Drain Current Gate Voltage
Figure Body Diode Forward Voltage Variation Source Current Temperature
Ciss (Cds shorted) Coss Crss
Capacitance [pF]
Ciss Coss
Notes
VGS, Gate-Source Voltage
Crss
Note
VDS, Drain-Source Voltage
Total Gate Charge [nC]
Figure Capacitance Characteristics
Figure Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Typical Characteristics N-Channel (Continued)
(Normalized) Drain-Source Breakdown Voltage
RDS(ON) (Normalized) Drain-Source On-Resistance
Notes
Notes 0.65
-100
-100
Junction Temperature
Junction Temperature
Figure Breakdown Voltage Variation Temperature
Figure On-Resistance Variation Temperature
Operation This Area Limited DS(on)
Drain Current
Drain Current
Notes Single Pulse
VDS, Drain-Source Voltage
Case Temperature
Figure Maximum Safe Operating Area
Figure Maximum Drain Current Case Temperature
Figure Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Typical Characteristics P-Channel (Continued)
Drain Current
Drain Current
-10.0 -8.0 -6.0 -5.0 -4.5 -4.0 -3.5 Bottom -3.0
Notes -25V Pulse Test
Notes Pulse Test
-VDS, Drain-Source Voltage
-VGS Gate-Source Voltage
Figure On-Region Characteristics
Figure Transfer Characteristics
RDS(on) Drain-Source On-Resistance
Note
Reverse Drain Current
Notes Pulse Test
Drain Current
-VSD Source-Drain Voltage
Figure On-Resistance Variation Drain Current Gate Voltage
Figure Body Diode Forward Voltage Variation Source Current Temperature
Ciss (Cds shorted) Coss Crss
Gate-Source Voltage
-60V -150V
Capacitance [pF]
Ciss
Coss
Notes
-240V
Crss
Note -0.3
VDS, Drain-Source Voltage
Total Gate Charge [nC]
Figure Capacitance Characteristics
Figure Gate Charge Characteristics
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Typical Characteristics P-Channel (Continued)
(Normalized) Drain-Source Breakdown Voltage
RDS(ON) (Normalized) Drain-Source On-Resistance
Notes -250
Notes -0.15
-100
-100
Junction Temperature
Junction Temperature
Figure Breakdown Voltage Variation Temperature
Figure On-Resistance Variation Temperature
0.35
Operation This Area Limited DS(on)
0.30
Drain Current
Drain Current
0.25
0.20
0.15
0.10
Notes Single Pulse
0.05
0.00
-VDS, Drain-Source Voltage
Case Temperature
Figure Maximum Safe Operating Area
Figure Maximum Drain Current Case Temperature
Figure Transient Thermal Response Curve
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Gate Charge Test Circuit Waveform
200nF 300nF
Same Type
Charge
Resistive Switching Test Circuit Waveforms
td(on)
td(off)
©2000 Fairchild Semiconductor International
Rev.
FQS4900
Package Dimensions
8-SOP
1.55 ±0.20 0.061 ±0.008 0.1~0.25 0.004~0.001
4.92 ±0.20 0.194 ±0.008 5.13 0.202
6.00 ±0.30 0.236 ±0.012
+0.10 0.15 -0.05 +0.004 0.006 -0.002
0.56 0.022 1.80 0.071 MAX0.10 MAX0.004 3.95 ±0.20 0.156 ±0.008 5.72 0.225 0.50 ±0.20 0.020 ±0.008
©2000 Fairchild Semiconductor International
1.27 0.050
Rev.
0.41 ±0.10 0.016 ±0.004
TRADEMARKS
following registered unregistered trademarks Fairchild Semiconductor owns authorized intended exhaustive list such trademarks.
Quiet SeriesFAST® FASTrGTO
QFETQSQuiet SeriesSuperSOTTM-3 SuperSOTTM-6
SuperSOTTM-8 SyncFETTinyLogicUHCVCX
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR INTERNATIONAL. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
PRODUCT STATUS DEFINITIONS Definition Terms
Datasheet Identification Advance Information Product Status Formative Design First Production Definition This datasheet contains design specifications product development. Specifications change manner without notice. This datasheet contains preliminary data, supplementary data will published later date. Fairchild Semiconductor reserves right make changes time without notice order improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves right make changes time without notice order improve design. This datasheet contains specifications product that been discontinued Fairchild semiconductor. datasheet printed reference information only.
Preliminary
Identification Needed
Full Production
Obsolete
Production
©2000 Fairchild Semiconductor International
Rev. January 2000
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