Low-Skew Clock Fanout Buffer Features Description Gener

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Low-Skew Clock Fanout Buffer Features Description Gener

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FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Features
Description
Generates eighteen low-skew, non-inverting clocks from clock input Supports four SDRAM DIMMs Uses either SMBus serial interface with Read Write capability individual clock output control Output enable tristates clock outputs facilitate board testing Clock outputs skew-matched less than 250ps Less than propagation delay Output impedance: 0.5VDD Serial interface meet specifications; other LVTTL/LVCMOS-compatible Five differerent configurations available:
FS6050: clock outputs 48-pin SSOP FS6051: clock outputs 28-pin SOIC, SSOP FS6053: clock outputs 28-pin SOIC FS6054: clock outputs 28-pin SOIC
FS6050 family CMOS clock fanout buffer designed high-speed motherboard applications, such Intel Pentium PC100-based systems with 100MHz SDRAM. eighteen buffered, non-inverting clock outputs fanned-out from clock input. Individual clocks skew matched less than 250ps 100MHz. Multiple power ground supplies reduce effects supply noise device performance. Under C-bus control, individual clock outputs turned off. active-low output enable available force clock outputs tristate level system testing.
Figure Configuration (FS6050)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_17 SDRAM_9 SDRAM_8 (reserved) (reserved)
VSS_I2C
Figure Block Diagram (FS6050)
FS6050
(reserved)
(reserved)
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_4
SDRAM_5
SDRAM_6
SDRAM_7
SDRAM_16
VDD_I2C
CLK_IN
SDRAM_(0:1)
VDD_I
VSS_I2C
SDRAM_(2:3) Serial Interface
48-pin SSOP
SDRAM_(4:5)
SDRAM_(6:7) CLK_IN
Figure Configuration (FS6051)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_17 VSS_I2C
SDRAM_(8:9)
SDRAM_(12:13)
FS6051
SDRAM_(14:15)
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_16
VDD_I2C
CLK_IN
SDRAM_16
SDRAM_17
28-pin SOIC, SSOP
FS6050
Additional configurations noted Page
ISO9001
Intel Pentium registered trademarks Intel Corporation. licensed trademark Philips Electronics, N.V. American Microsystems, Inc. reserves right change detail specifications required permit improvements design products. 3.4.02
SDRAM_(10:11)
FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Table Descriptions
Key: Analog Input; Analog Output; Digital Input; Input with Internal Pull-Up; Input with Internal Pull-Down; Digital Input/Output; DI-3 Three-Level Digital Input, Digital Output; Power/Ground; Active
(FS6050)
(FS6051)
(FS6053)
(FS6054)
TYPE DIUO
NAME CLK_IN SDRAM_0 SDRAM_1 SDRAM_2 SDRAM_3 SDRAM_4 SDRAM_5 SDRAM_6 SDRAM_7 SDRAM_8 SDRAM_9 SDRAM_10 SDRAM_11 SDRAM_12 SDRAM_13 SDRAM_14 SDRAM_15 SDRAM_16 SDRAM_17 VDD_I2C VSS_I2C (reserved)
DESCRIPTION Clock input SDRAM clock outputs Serial clock input Serial data input/output
SDRAM clock outputs (Byte
SDRAM clock outputs (Byte
SDRAM feedback clock outputs (Byte Output enable tristates clock outputs when 3.3V power supply SDRAM clock buffers 3.3V power supply serial communications Ground SDRAM clock buffers Ground serial communications Reserved
Figure Configuration (FS6053)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_9 SDRAM_8 VSS_I2C
Figure Configuration (FS6054)
SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_9 SDRAM_17
SDRAM_8
VSS_I2C
FS6053
FS6054
SDRAM_0
SDRAM_1
SDRAM_2
SDRAM_3
SDRAM_6
SDRAM_7
SDRAM_16
VDD_I2C
CLK_IN
SDRAM_16
SDRAM_2
SDRAM_0
SDRAM_1
SDRAM_3
SDRAM_6
SDRAM_7
VDD_I2C
CLK_IN
3.4.02
ISO9001
FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Programming Information
Register Programming
Table Clock Enable
CONTROL INPUTS CLOCK OUTPUTS (MHz) SDRAM_0:17 tristate CLK_IN
logic-one written valid location turns assigned output clock. Likewise, logic-zero written valid location turns assigned output clock. unused reserved register bits should cleared zero. Serial bits written this device order shown Table
Table Register Summary Power-Up Initialization
SERIAL (LSB) Byte SDRAM Control Register (LSB) (MSB) Byte SDRAM Control Register (LSB) (MSB) Byte SDRAM Control Register DATA BYTE (MSB) CLOCK OUTPUT SDRAM_7 SDRAM_6 SDRAM_5 SDRAM_4 SDRAM_3 SDRAM_2 SDRAM_1 SDRAM_0 SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_9 SDRAM_8 SDRAM_17 SDRAM_16 Reserved Reserved Reserved Reserved Reserved Reserved
outputs enabled active upon power-up, output control register bits initialized one. outputs must configured power-up expected configured during normal operation. Inactive outputs held disabled from switching. 3.1.1 Unused Outputs Outputs that used versions this device with reduced pinout still operational internally. reduce power dissipation crosstalk effects from unloaded outputs, recommended that these outputs shut Control Registers.
3.4.02
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Low-Skew Clock Fanout Buffer
Table Byte SDRAM Control Register
REGISTER CLOCK OUTPUT SDRAM_7 SDRAM_6 SDRAM_5 SDRAM_4 SDRAM_3 SDRAM_2 SDRAM_1 SDRAM_0 DESCRIPTION OUTPUT (FS6050) OUTPUT (FS6051) OUTPUT (FS6053) OUTPUT (FS6054)
Table Byte SDRAM Control Register
REGISTER CLOCK OUTPUT SDRAM_15 SDRAM_14 SDRAM_13 SDRAM_12 SDRAM_11 SDRAM_10 SDRAM_9 SDRAM_8 DESCRIPTION OUTPUT (FS6050) OUTPUT (FS6051) OUTPUT (FS6053) OUTPUT (FS6054)
Table Byte SDRAM Control Register
REGISTER CLOCK OUTPUT SDRAM_17 SDRAM_16 DESCRIPTION OUTPUT (FS6050) OUTPUT (FS6051) OUTPUT (FS6053) OUTPUT (FS6054)
Reserved (set Reserved (set Reserved (set Reserved (set Reserved (set Reserved (set
3.4.02
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FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Dual Serial Interface Control
This integrated circuit read/write slave device that supports both Inter C-bus) System Management (SMBus) two-wire serial interface protocols. unique device address that written device determines whether part expects receive SMBus commands commands. Since SMBus derived from C-bus, protocol both types very similar. general, controlled master device that generates serial clock SCL, controls access, generates START STOP conditions while device works slave. Both master slave operate transmitter receiver, master device determines which mode activated. device that sends data onto defined transmitter, device receiving data receiver. logic levels timing parameters noted herein fol2 C-bus convention. Logic levels based percentage VDD. logic-one corresponds nominal voltage VDD, while logic-zero corresponds ground (VSS).
4.1.4 Data Valid state line represents valid data line stable duration high period line after START condition occurs. data line must changed only during period signal. There clock pulse data bit. Each data transfer initiated START condition terminated with STOP condition. number data bytes transferred between START STOP conditions determined master device, continue indefinitely. However, data that overwritten device after data registers filled will overflow from last register into first register, then second, first-in, first-overwritten fashion. 4.1.5 Acknowledge When addressed, receiving device required generate Acknowledge after each byte received. master device must generate extra clock pulse coincide with Acknowledge bit. acknowledging device must pull line during high period master acknowledge clock pulse. Setup hold times must taken into account. master must signal data slave generating acknowledge last byte that been read (clocked) slave. this case, slave must leave line high allow master generate STOP condition.
Conditions
Data transfer only initiated when busy. During data transfer, data line (SDA) must remain stable whenever clock line (SCL) high. Changes data line when clock line high interpreted device START STOP condition. Both C-bus SMBus protocols define following conditions bus. Refer Figure Timing Data more information. 4.1.1 Busy Both data (SDA) clock (SCL) lines remain high indicate busy. 4.1.2 START Data Transfer high transition line while input high indicates START condition. commands device must preceded START condition. 4.1.3 STOP Data Transfer high transition line while held high indicates STOP condition. commands device must followed STOP condition.
Operation Commands
programmable registers accessed bidirectional wire digital interface. device accepts Random Register Read/Write Sequential Register Read/Write commands. device also supports Block Read/Write SMBus commands. 4.2.1 C-bus SMBus Device Addressing After generating START condition, master broadcasts seven-bit device address followed bit. Note that every device C-bus SMBus must have unique address avoid conflicts. SMBus interface, address device
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Low-Skew Clock Fanout Buffer
C-bus interface, device support vice addresses permit multiple devices C-bus. address ignored either zero. Therefore, C-bus interface device address
4.2.2
C-bus: Random Register Write Procedure Random write operations, shown Figure allow master directly write register. initiate write procedure, that transmitted after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write eight bits data into addressed register. final acknowledge returned device, master generates STOP condition. either STOP repeated START condition occurs during Register Write, data that been transferred ignored.
4.2.4 C-bus: Sequential Register Write Procedure Sequential write operations, shown Figure allow master write each register order. register pointer automatically incremented after each write. This procedure more efficient than Random Register Write several registers must written. initiate write procedure, that transmit2 after seven-bit device address logic-low. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address written into slave's address pointer. Following acknowledge slave, master allowed write data last addressed register before register address pointer overflows back beginning address. acknowledge device between each byte data must occur before next data byte sent. Registers updated every time device sends acknowledge host. register update does wait STOP condition occur. Registers therefore updated different times during Sequential Register Write. 4.2.5 C-bus: Sequential Register Read Procedure Sequential read operations allow master read from each register order. register pointer automatically incremented after each read. This procedure, shown Figure more efficient than Random Register Read several registers must read from. perform read procedure, that trans2 mitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits data starting with initial addressed register. register address pointer will overflow initial register address larger than zero. After last byte data, master does acknowledge transfer does generate STOP condition.
3.4.02
4.2.3 C-bus: Random Register Read Procedure Random read operations allow master directly read from register. perform read procedure, shown Figure that transmitted after seven-bit address logic-low, Register Write procedure. This indicates addressed slave device that register address will follow after slave device acknowledges device address. register address then written into slave's address pointer. Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then transmits eight-bit word. master does acknowledge transfer does generate STOP condition.
ISO9001
FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Figure Random Register Write Procedure (I2C-bus)
DEVICE ADDRESS REGISTER ADDRESS DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge STOP Condition Acknowledge From device host
Figure Random Register Read Procedure (I2C-bus)
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command STOP Condition Acknowledge
Figure Sequential Register Write Procedure (I2C-bus)
DEVICE ADDRESS REGISTER ADDRESS DATA DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
Data Acknowledge
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
From device host
Figure Sequential Register Read Procedure (I2C-bus)
DEVICE ADDRESS REGISTER ADDRESS DEVICE ADDRESS DATA DATA
7-bit Receive Device Address START Command
Register Address Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Data Acknowledge READ Command Acknowledge
Data Acknowledge STOP Command
3.4.02
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Low-Skew Clock Fanout Buffer
4.2.6
SMBus: Block Write Block Write command permits master write several bytes data sequential registers, starting default Register Block Write command, noted Figure begins with seven-bit SMBus device address followed logiclow begin Write command. Following acknowledge SMBus address slave device, command code written. defined that eight bits command code must zero (0). After command code zero acknowledge, host then issues byte count that describes number data bytes written. According SMBus convention, byte count should value between however this slave device ignores byte count value. Following acknowledge byte count, data bytes written starting with Register incrementing sequentially. acknowledge device between each byte data must occur before next data byte sent.
SMBus
4.2.7 SMBus: Block Read Block Read command, shown Figure permits master read several bytes data from sequential
registers, starting default Register perform Block Read procedure that transmitted after seven-bit SMBus address logic-low, Block Write procedure. write resets register address pointer zero. Following acknowledge SMBus address slave device, command code written. defined that eight bits command code must zero (0). Following acknowledge slave, master generates repeated START condition. repeated START terminates write procedure, until after slave's address pointer set. slave SMBus address then resent, with this time logic-high, indicating slave that data will read. slave will acknowledge device address, then will expect byte count value (which will ignored). Following byte count value, device will take command will transmit data beginning with Register After last byte data, master does acknowledge transfer does generate STOP condition. master does want receive data, master acknowledge last data byte then issue STOP condition next clock.
Figure Block Write (SMBus)
DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command From host device
Byte Count
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
Acknowledge From device host
Figure Block Read (SMBus)
DEVICE ADDRESS DEVICE ADDRESS BYTE COUNT DATA BYTE DATA BYTE
7-bit Receive Device Address START Command
Command Code Acknowledge WRITE Command From host device
7-bit Receive Device Address Repeat START Acknowledge From device host
Byte Count Acknowledge READ Command
Data Acknowledge Acknowledge
Data Acknowledge STOP Command
3.4.02
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Low-Skew Clock Fanout Buffer
Electrical Specifications
Table Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These conditions represent stress rating only, functional operation device these other conditions above operational limits noted this specification implied. Exposure maximum rating conditions extended conditions affect device performance, functionality, reliability.
PARAMETER Supply Voltage, Clock Buffers (VSS ground) Supply Voltage, Serial Communications Input Voltage, Output Voltage, Input Clamp Current, VDD) Output Clamp Current, VDD) Storage Temperature Range (non-condensing) Ambient Temperature Range, Under Bias Junction Temperature Lead Temperature (soldering, 10s) Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
SYMBOL VDD_I2C
MIN. VSS-0.5 VSS-0.5 VSS-0.5 VSS-0.5
MAX. VDD+0.5 VDD+0.5
UNITS
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting loss functionality performance occur this device subjected high-energy electrostatic discharge.
Table Operating Conditions
PARAMETER Supply Voltage, Clock Buffers Supply Voltage, Serial Communications Ambient Operating Temperature Range Input Frequency Output Load Capacitance Serial Data Transfer Rate SYMBOL VDD_I2C fCLK Standard mode CONDITIONS/DESCRIPTION 3.3V 3.3V MIN. 3.135 3.135 TYP. MAX. 3.465 3.465 UNITS kb/s
3.4.02
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Low-Skew Clock Fanout Buffer
Table Electrical Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical. Negative currents indicate current flows device.
PARAMETER Overall (FS6050) Supply Current, Dynamic, with Loaded Outputs Supply Current, Static High-Level Input Voltage Low-Level Input Voltage Hysteresis Voltage High-Level Input Current Low-Level Input Current (pull-up) Low-Level Output Sink Current (SDA) Output Enable Input (OE) High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current (pull-up) Clock Input (CLK_IN) High-Level Input Voltage Low-Level Input Voltage Input Leakage Current
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
IDDL Vhys IOSH IOSL
fCLK 100MHz; 3.47V Outputs low; 3.47V Outputs Outputs Outputs Outputs low; 0.4V, 3.47V. Note: requires external pull-up drive data bus. 0.4V 2.31 VSS-0.3 VSS-0.3 0.4V; 3.47V
0.75
VDD+0.3
Serial Communication Inputs/Output (SDA, SCL)
VDD+0.3
VSS-0.3
VDD+0.3
Clock Outputs (SDRAM_0:17 3.3V Type Clock Buffer) High-Level Output Source Current Low-Level Output Sink Current Output Impedance Tristate Output Current Short Circuit Source Current Short Circuit Sink Current 3.135V, 2.0V 3.465V, 3.135V 3.135V, 1.0V 3.465V, 0.4V 0.5VDD; output driving high 0.5VDD; output driving shorted 30s, max. 3.3V; shorted 30s, max. -106 17.9 16.3
3.4.02
ISO9001
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Low-Skew Clock Fanout Buffer
Table Timing Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical.
PARAMETER Overall Clock Skew, Maximum; SDRAM_0 SDRAM
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK (MHz)
MIN.
TYP.
MAX.
UNITS
tskw tPLH(min) tPLH(max) tPHL(min) tPHL(max)
Measured rising edge 1.5V; 20pF Measured rising edge 1.5V; 20pF Measured rising edge 1.5V; 30pF Measured rising edge 1.5V; 20pF Measured rising edge 1.5V; 30pF
66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67
Propagation Delay, Average; CLK_IN SDRAM
Clock Outputs (SDRAM_0:17 3.3V Type Clock Buffer) tr(min) Rise Time tr(max) tf(min) Fall Time tf(max) tKH(min) Clock High Time tKH(max) tKL(min) Clock Time tKL(max) 0.4V; 30pF From rising edge rising edge 1.5V; 20pF From rising edge rising edge 1.5V; 30pF tPZL tPZH tPLZ tPHZ Output tristated output active; 20pF Output active output tristated; 20pF 2.4V; 30pF 0.4V; 20pF 2.4V 0.4V; 30pF 2.4V; 20pF 0.4V 2.4V; 30pF 2.4V 0.4V; 20pF 0.4V 2.4V; 20pF
Duty Cycle
Tristate Enable Delay Tristate Disable Delay
3.4.02
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Low-Skew Clock Fanout Buffer
Table Serial Interface Timing Specifications
Unless otherwise stated, power supplies 3.3V load output, ambient temperature range 70°C. Parameters denoted with asterisk represent nominal characterization data currently production tested specific limits. characterization data from typical.
PARAMETER Clock frequency free time between STOP START time, START (repeated) Hold time, START time, data input Hold time, data input Output data valid from clock Rise time, data clock Fall time, data clock High time, clock time, clock time, STOP
SYMBOL fSCL tBUF tsu:STA thd:STA tsu:DAT thd:DAT tsu:STO
CONDITIONS/DESCRIPTION
MIN.
MAX.
UNITS
Minimum delay bridge undefined region falling edge avoid unintended START STOP SDA, SDA,
1000
Figure Timing Data
tsu:STA thd:STA tsu:STO
START
ADDRESS DATA VALID
DATA CHANGE
STOP
Figure Data Transfer Sequence
tsu:STA thd:STA thd:DAT
tsu:DAT
tsu:STO
tBUF
3.4.02
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Low-Skew Clock Fanout Buffer
Figure SDRAM_0:17 Clock Output (3.3V Type Clock Buffer)
Voltage 0.65 0.85 1.65 1.95 3.135 Drive Current (mA) MIN. TYP. MAX. Voltage 1.65 3.135 3.465 High Drive Current (mA)
MIN.
TYP. -116 -116 -110 -107 -103
MAX. -198 -198 -188 -177 -170 -157 -126 -107 Output Current (mA) -184
-100 -120 -140 -160 -180 -200 -220
MIN. TYP. MAX.
Output Voltage
Figure Measurement Points
3.3V 2.4V 1.5V 0.4V (device interface) 0.8V
Figure Timing Measurement Points
Duty Cycle
2.0V
2.4V 1.5V 0.4V
(system interface)
Figure Clock Skew Measurement Point
1.5V 3.3V
tskw
1.5V 3.3V
tPLZ
tPZL
tPHZ
tPHZ
3.4.02
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Low-Skew Clock Fanout Buffer
Package Information
Table 48-pin SSOP (7.5mm/0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.095 0.008 0.088 0.008 0.005 0.620 0.292 0.400 0.010 0.024 MAX. 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 0.410 0.016 0.040 MILLIMETERS MIN. 2.41 0.203 2.24 0.203 0.127 15.75 7.42 10.16 0.254 0.610 MAX. 2.79 0.406 2.34 0.343 0.254 16.00 7.59 10.41 0.410 1.02
BASE PLANE SEATING PLANE RADII: 0.005" 0.01"
AMERICAN MICROSYSTEMS, INC.
typ.
0.025
0.64
Table 48-pin SSOP (7.5mm/0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. UNITS °C/W
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Low-Skew Clock Fanout Buffer
Table 28-pin SOIC (7.5mm/0.300") Package Dimensions
DIMENSIONS INCHES MIN. 0.093 0.004 0.08 0.013 0.009 0.697 0.291 0.393 0.010 0.016 MAX. 0.104 0.012 0.100 0.013 0.009 0.713 0.299 0.419 0.030 0.05 MILLIMETERS MIN. 2.35 0.10 2.05 0.33 0.23 17.70 7.40 10.00 0.25 0.40 MAX. 2.65 0.30 2.55 0.51 0.32 18.10 7.60 10.65 0.75 1.27
BASE PLANE RADII: 0.005" 0.01"
AMERICAN MICROSYSTEMS, INC.
SEATING PLANE
typ.
0.05
1.27
Table 28-pin SOIC (7.5mm/0.300") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. 0.85 0.42 0.08 UNITS °C/W
3.4.02
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Low-Skew Clock Fanout Buffer
Table 28-pin SSOP (5.3mm/0.209") Package Dimensions
DIMENSIONS INCHES MIN. 0.068 0.002 0.066 0.01 0.005 0.396 0.205 0.301 0.022 MAX. 0.078 0.008 0.07 0.015 0.008 0.407 0.212 0.311 0.037 MILLIMETERS MIN. 1.73 0.05 1.68 0.25 0.13 10.07 5.20 7.65 0.55 MAX. 2.00 0.21 1.78 0.38 0.20 10.33 5.38
RADII: 0.005" 0.01" AMERICAN MICROSYSTEMS, INC.
typ.
0.028
0.65 7.90 0.95
BASE PLANE
SEATING PLANE
Table 28-pin SSOP (5.3mm/0.209") Package Characteristics
PARAMETER Thermal Impedance, Junction Free-Air Lead Inductance, Self Lead Inductance, Mutual Lead Capacitance, Bulk Lead Capacitance, Mutual SYMBOL CONDITIONS/DESCRIPTION flow Center lead Center lead adjacent lead Center lead Center lead adjacent lead TYP. 2.24 0.95 0.25 0.07 UNITS °C/W
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Low-Skew Clock Fanout Buffer
Ordering Information
ORDERING CODE 11257-801 11257-811 11257-802 PACKAGE TYPE 48-pin (7.5mm/0.300") SSOP 48-pin (7.5mm/0.300") SSOP 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.209") SOIC 28-pin (5.3mm/0.209") SSOP 28-pin (5.3mm/0.209") SSOP 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC 28-pin (7.5mm/0.300") SOIC OPERATING TEMPERATURE RANGE 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) 70°C (Commercial) SHIPPING CONFIGURATION Tape Reel Tube Tape Reel Tube Tape Reel Tube Tape Reel Tube Tape Reel Tube
DEVICE NUMBER FS6050
FS6051
11257-812 11257-806 11257-816
FS6053
11257-803 11257-813 11257-804 11257-814
FS6054
Purchase components American Microsystems, Inc., sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
Copyright 1998 American Microsystems, Inc.
Devices sold covered warranty patent indemnification provisions appearing Terms Sale only. makes warranty, express, statutory implied description, regarding information forth herein regarding freedom described devices from patent infringement. makes warranty merchantability fitness purposes. reserves right discontinue production change specifications prices time without notice. AMI's products intended commercial applications. Applications requiring extended temperature range, unusual environmental requirements, high reliability applications, such military, medical life-support life-sustaining equipment, specifically recommended without additional processing such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, 83201, (208) 233-4690, (208) 234-6796, Address: http://www.amis.com E-mail: tgp@amis.com
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Low-Skew Clock Fanout Buffer
Application Information
Reduction
Figure Board Layout
VOID
1000pF 1000pF 1000pF 1000pF 1000pF 1000pF
primary concern when designing board layout this device reduction electromagnetic interference (EMI) generated copies 100MHz SDRAM clock. assumed reader familiar with basic transmission line theory. 8.1.1 Layout Guidelines obtain best performance, noise should minimized power ground supplies Observe good high-speed board design practices, such multi-layer circuit boards with dedicated impedance power ground planes device (denoted Figure 18). device power ground planes should completely isolated from motherboard power ground planes void power planes. Several low-pass filters using impedance ferrite beads 100MHz) recommended decouple device power ground planes from motherboard power ground planes GND). beads should span between power ground planes. Seven beads power seven beads ground suggested total) that clock rise times (1V/ns) maintained. Place 1000pF bypass capacitors close possible power pins RF-quality lowinductance multi-layer ceramic chip capacitors. capacitors optimal, each power/ground grouping shown Figure Load similar clock outputs equally, keep output loading light possible help reduce clock skew power dissipation. equal-length clock traces that short possible. Rounded trace corners help reduce reflections ringing clock signal. clock traces must never cross void area between power/ground planes. Each trace must have complete plane (either GND) under complete length trace.
Component Layer Signal Layer
8.1.2 Output Driver Termination signal reflection will occur point PC-board trace where impedance mismatches exist. Reflections cause several undesirable effects high-speed applications, such increase clock jitter rise electromagnetic emissions from board. Using properly designed series termination each high-speed line alleviate these problems eliminating signal reflections.
Figure Series Termination
DRIVER LINE
RECEIVE
3.4.02
ISO9001
FS6050/FS6051/FS6053/FS6054
Low-Skew Clock Fanout Buffer
Series termination adds loading driver, requires less power than other resistive termination methods. Further, extra impedance exists from signal line reference voltage, such ground. shown Figure driver's output impedance (zO) series termination resistance (RS) must equal line impedance (zL). That
pacitance, number connected devices with their associated input currents. Control clock data lines done through open drain/collector current-sink outputs, thus requires external pull-up resistors both lines. guideline
Note that when source impedance (zO+RS) matched line impedance, then voltage division incident wave amplitude one-half full signal amplitude.
Cbus
where maximum rise time (minus some margin) Cbus total capacitance. Assuming device each DIMM, controller, clock buffer, other devices results values range. series resistor provide protection against high voltage spikes will alter values
full signal amplitude take twice long propagation delay line develop, reducing noise immunity during half-amplitude period. Note also that voltage receive must signal amplitude that meets receiver switching thresholds. slew rate signal also reduced additional delay load capacitance line impedance. Also note that output driver impedance will vary slightly with output logic state (high low).
Figure Connections Serial
(optional)
(optional)
(optional)
(optional)
Data Clock Data Clock
Data
Data
Dynamic Power Dissipation
TRANSMITTER
RECEIVER
High-speed clock drivers require careful attention power dissipation. Transient power (PT) consumption derived from
load
where Cload load capacitance, supply voltage, fCLK clock frequency, number switching outputs. internal heat (junction temperature, generated power dissipation calculated from
where package thermal resistance, ambient temperature, derived above.
8.3.1 More Information More detailed information serial design obtained from SMBus Design, available from Intel Corporation http://www.intel.com. Information C-bus found document C-bus (Including Specifications), available from Philips Semiconductors Additional information System Management found System Management Specification, available from Smart Battery System Implementers' Forum http://www.sbs-forum.org.
Serial Communications
Connection devices standard-mode implementa2 tion either C-bus SMBus similar that shown Figure Selection pull-up resistors (RP) optional series resistors (RS) lines depends supply voltage, ca3.4.02
ISO9001

Low-Skew Clock Fanout Buffer Features Description Gener

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