BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR MHz-1
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BCM1250
BCM1250 HIGH-PERFORMANCE, INTEGRATED 64-BIT MULTIPROCESSOR
MHz-1
64-bit MIPS CPUs, scalable from
Quad-issue order pipeline; dual execute, dual memory pipes Enhanced skew pipeline enables zero load-to-use penalty 32-KB instruction cache, 32-KB data cache Advanced branch predictors
Industry-leading performance
Processing speed Mpps* Gbps on-chip bandwidth; Gbps memory bandwidth, Gbps total bandwidth
Fast, on-chip multiprocessor
Connects CPUs, cache, memory controller bridges Runs half core frequency; bits wide
On-chip cache
shared both CPUs 4-way associative, protected Ways removed provide fast on-chip
power dissipation 8-10W MHz) High functional integration Programming Instruction Setease flexibility based MIPS64 Architecture (ISA) Scalable multiprocessor chip system architecture Broad tools system software support additional information evaluation boards, refer BCM1250and BCM91250A
BCM91250E product briefs
*Based internal Broadcom benchmark, using BCM1250 standard IPv4 look-up/switching.
memory controller
channels, each with 64-bit data plus optional Runs clock rate, data rate Support SDRAM, SGRAM, FCRAM
High-speed packet interfaces
Three 10/100/1000 Ethernet MACs; 802.3 compliant Option configure MACs into packet FIFOs packet FIFOs each capable OC-48 data rates
BCM1250's world-class performance, power efficiency integration, processor ideal broad variety applications including:
Enterprise workgroup backbone switches switches/routers Multiservice access concentrators routers/gateway/switches services/subscriber management platforms Web-server switches High-end firewall/intrusion detection devices Wireless basestations
interface
bits, 33/66 (PCI 2.2) Host bridge target device
HyperTransport
(formerly LDT) interface
Complies with HyperTransportstandard high-speed fabric 500-MHz clock rate, double data rate, CPUs; 600-MHz clock rate CPUs Peak bandwidth Gbps each direction Supports double-ended fabrics link BCM1250s)
Example: Packet Processing Blade
BCM5840 2,400 Mbps IPSec BCM5615 24-10/100 +2-Gigabit Ports
Integrated system
Generic direct connect boot ROM, flash SMBus serial configuration interfaces PCMCIA control interface serial interfaces
SMII
BCM5238 10/100 Ports BCM5238 BCM5238
SGMII 10/100 /1000 Ports
FPGA
HyperTransport
Extensive, on-chip debug features 8-10W power dissipation Support leading operating systems including VxWorks Linux NetBSD Evaluation board platform available with tools,
GMII
BCM5404
BCM5680 8-Port 10/100/1000 BASE-T Aggregation, L2/L3 Switching
1250 1250
DRAM
GMII
DRAM
firmware software drivers
Deep Packet Look-up, L4-L7 Processing
BCM1250 Block Diagram
JTAG Mbps Serial Interface Serial Interface Dual SMBus GPIO/ Interrupt/ PCMCIA
Debug/ Trace
SB-1 Core
SB-1 Core
512-KB Cache
Data Mover Memory Controller
Bits ZBbus runs clock @128 Gbps 10/100/ 1000 FIFO 10/100/ 1000 10/100/ 1000 FIFO
16-50 Gbps
Mbps
Bridge Generic Flash
PCI/HT Bridge 32-Bit Host Bridge
Gbps
GMII 16-bit FIFO Gbps Gbps
Gbps 19.2 Gbps
Broadcom's first SiByteprocessor, BCM1250, state-ofthe-art multiprocessor solution targeted fast-growing networking communications markets. BCM1250 first MIPS64processor offer industry-leading performance, high functional integration, power levels required next-generation networking applications. BCM1250 intelligent on-chip multiprocessor system (CMP) consisting Broadcom SB-1 high performance MIPS64CPUs, shared 512-KB cache, memory controller, integrated I/O. major blocks processor connected together ZBbus, high-speed, splittransaction multiprocessor bus. implements standard MESI protocol ensure coherency between CPUs, cache, agents, memory. Three Gigabit Ethernet MACs (10/100/1000) enable easy interfacing LANs. enable higher data rates, cases where Ethernet protocol processing required, MACs configured either three 8-bit 16-bit packet FIFOs. high-speed provided using
HyperTransport(HT) fabric 32-bit (rev 2.2) local bus. serial ports available UARTs console ports asynchronous interface connections T3/OC-1 rates Mbps). enable chip-count systems, BCM1250 also includes configurable generic that allows glueless connection boot flash memory simple peripherals. On-chip debug, trace, performance monitoring functions assist both hardware software designers debugging tuning system. system either big- little-endian mode. BCM1250 manufactured TSMC's 0.13µ process available package. Implementation MIPS64ISA SB-1 core high-performance implementation standard MIPS64instruction architecture (ISA), incorporates MIPS-3D MIPS-MDMX application specific extensions (ASEs). core supports four-issue enhanced skew pipeline dispatch memory (Integer, Floating Point, MDMX MIPS-3D) instructions cycle.
Broadcom®, pulse logo®, Connecting EverythingTM, SiByteand System I/Oare trademarks Broadcom Corporation and/or affiliates United States certain other countries. other trademarks mentioned property their respective owners.
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2002 BROADCOM CORPORATION. rights reserved. 1250-PB06-R-3.5.02
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