34COM/80SEG DRIVER CONTROLLER MATRIX KS0074 matrix driver control

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34COM/80SEG DRIVER CONTROLLER MATRIX KS0074 matrix driver control

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KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
KS0074 matrix driver controller which fabricated power CMOS technology. display lines with dots format.
FUNCTIONS
Character type matrix driver controller Internal driver common segment signal output Easy interface with 4-bit 8-bit Clock synchronized serial Interface matrix possible matrix possible Bi-directional shift function character reverse display Display shift line Voltage converter drive voltage times times) Various instruction functions Automatic power reset
FEATURES
Internal Memory Character Generator (CGROM) 9,600 bits (240 characters dot) Character Generator (CGRAM) bits characters dot) Segment Icon (SEGRAM) bits icons max.) Display Data (DDRAM) bits characters max.) power operation Power supply voltage range (VDD) Drive voltage range 13.0 (VDD CMOS process Programmable duty cycle 1/17, 1/33 (refer Table Internal oscillator with external resistor power consumption Bare chip available
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Table Programmable duty cycles 5-dot font width Display Line Numbers 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters line characters lines characters lines characters Possible icons
6-dot font width Display Line Numbers 1/17 1/33 1/33 Duty Ratio Single-chip Operation Displayable characters line characters lines characters lines characters Possible icons
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
BLOCK DIAGRAM
)'!!
346-/ 346-1
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
CONFIGURATION
SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33
SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26
chip size 6450 4870 size uCnit
SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24
OSC2 OSC1 RESET VSS1 RS/CS RW/SID E/SCLK DB0/SOD VSS2 V5OUT2 V5OUT3
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
LOCATION
<=>?@A
DEFGH DEFGL DEFGQ DEFGM DEFHP DEFHC DEFHJ DEFHO DEFHK DEFHG DEFHH DEFHL DEFHQ DEFHM DEFLP DEFLC DEFLJ DEFLO DEFLK DEFLG DEFLH DEFLL DEFLQ DEFLM DEFQP TZ]M TZ]CP TZ]CC TZ]CJ TZ]CO TZ]CK TZ]CG TZ]CH TZ]JG TZ]JH TZ]JL TZ]JQ TZ]JM TZ]OP TZ]OC TZ]OJ TZ]OO ZDTJ ZDTC REDE?
IJKLG IJOGP IJJJG IJCPP ICMLG ICQGP ICLJG ICHPP ICKLG ICOGP ICJJG ICCPP IMLG IQGP ILJG IHPP IKLG IOGP IJJG ICPP CPCJ CCOL CJHJ COQL CGCJ CHOL CLHJ CQQL JPCJ JCOL JJHJ JOQL JGCJ JHOL JLHJ OPGM OPGM OPGM OPGM OPGM OPGM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM IJJHM ICLLQ ICHGO ICGJQ ICKPO ICJLQ ICCGO
NDDC RDSTD RUSD>V ESDTWX VYPSDZV NDDJ NGZ<?J NGZ<?O TZ]JK TZ]JO TZ]JJ TZ]JC TZ]JP TZ]CM TZ]CQ TZ]CL TZ]Q TZ]L TZ]H TZ]G TZ]K TZ]O TZ]J TZ]C TZ]P DEFC DEFJ DEFO DEFK DEFG DEFH DEFL DEFQ
OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM OPGM JLHJ JHOL JGCJ JOQL JJHJ JCOL JPCJ CQQL CLHJ CHOL CGCJ COQL CJHJ CCOL CPCJ ICPP IJJG IOGP ICPJQ IMPO ILLQ IHGO IGJQ IKPO IJLQ ICGO CPML CJJJ COKL CKLJ CGML CLJJ JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM
DEFM DEFCP DEFCC DEFCJ DEFCO DEFCK DEFCG DEFCH DEFCL DEFCQ DEFCM DEFJP DEFJC DEFJJ DEFJO DEFJK DEFJG DEFJH DEFJL DEFJQ DEFJM DEFOP DEFOC DEFOJ DEFOO DEFOK DEFOG DEFOH DEFOL DEFOQ DEFOM DEFKP DEFKC DEFKJ DEFKO DEFKK DEFKG DEFKH DEFKL DEFKQ DEFKM DEFGP DEFGC DEFGJ DEFGO DEFGK DEFGG
IKLG IHPP ILJG IQGP IMLG ICCPP ICJJG ICOGP ICKLG ICHPP ICLJG ICQGP ICMLG IJCPP IJJJG IJOGP IJKLG IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM IOPGM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM JJHM CQCJ CHQL CGHJ CKOL COCJ CCQL CPHJ ICQL IOCJ IKOL IGHJ IHQL IQCJ IMOL ICPHJ ICCQL ICOCJ ICKOL ICGHJ ICHQL ICQCJ
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
DESCRIPTION
(NO) INPUT/ OUTPUT (43) VSS1,VSS2 (49,64) V1-V5 (71-67) (61) SEG1-SEG80 (89-143, (1-25) COM0-COM33 (72-88, 26-42) OSC1,OSC2 (45,44) C1,C2 (63,62) Input (OSC1), Output (OSC2) Input Oscillator When internal oscillator, connect external resistor. external clock used, connect OSC1. External resistor/oscillator (OSC1) External capacitance Output Common output Common signal output drive. Input Output Input voltage voltage converter generate drive voltage(Vci -4.5V). Segment output Segment signal output drive. Power supply Bias voltage level driving. Power supply logical circuit(+3V,+5V) 0V(GND) NAME DESCRIPTION INTERFACE
RESET (46) (48)
Input Input
External voltage converter(2 times times), capacitance input these pins must connected external capacitance. Reset Initialized Select instruction times converter output Three times converter output When "High", Instruction selected Table When "Low", Instruction selected Table value converted times. three times converter, same capacitance that C1-C2 should connected here. value converted three times.
V5OUT2(65)
Output
capacitance
V5OUT3(66)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
DESCRIPTION (continued)
(NO) INPUT/ OUTPUT (47) Input Interface mode selection Register select/ Chip select Select Interface mode with MPU. When "Low" Serial mode, When "High" 4-bit/8-bit mode. mode, used register selection input. When RS/CS "High", Data register selected. When RS/CS "Low", Instruction register selected. serial mode, used chip selection input. When RS/CS "Low", selected. When RS/CS "High", selected.(Low access enable) NAME DESCRIPTION INTERFACE
RS/CS (50)
Input
RW/SID (51)
Input
mode, used read/write selection input. Read write/Serial input When RW/SID "High", read operation. When RW/SID "Low", write operation. data serial mode, used data input pin. Read write enable/Serial clock Data bit/Serial output data Data mode, used read write enable signal. serial mode, used serial clock input pin. 8-bit mode, used lowest bi-directional data bit. During 4-bit mode, Open this pin. serial mode, used serial data output pin. read operation, open this pin. 8-bit mode, used order bidirectional data bus. During 4-bit mode serial mode, open these pins. 8-bit mode, used high order bidirectional data bus. case 4-bit mode, used both high order. used Busy Flag output. During serial mode, open these pins.
E/SCLK (49)
Input
DB0/SOD (53)
Input Output/Output
DB1-DB3 (5456)
Input. Output
DB4-DB7 (5760)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
FUNCTION DESCRIPTION
System Interface This chip three kinds interface type with serial, 4-bit 8-bit bus. Serial bus(4-bit/8-bit) selected input, 4-bit 8-bit selected instruction register. During read write operation, 8-bit registers used. data register (DR), other instruction register(IR). data register(DR) used temporary data storage place being written into read from DDRAM/CGRAM/SEGRAM, target selected address setting instruction. Each internal operation, reading from writing into RAM, done automatically. Hence, after reads data, data next DDRAM/CGRAM/SEGRAM address transferred into automatically. Also after writes data data transferred into DDRAM/CGRAM/SEGRAM automatically. Instruction register(IR) used only store instruction code transferred from MPU. cannot read instruction data. select register, RS/CS input 4-bit/8-bit mode(IM "High") serial mode(IM "Low").
Table Various kinds operations according bits. Operation Instruction Write operation (MPU writes Instruction code into Read Busy flag(DB7) address counter (DB0 DB6) Data Write operation (MPU writes data into Data Read operation (MPU reads data from
Busy Flag (BF) When "High", indicates that internal operation being processed. during this time next instruction cannot accepted. read, when High(Read Instruction Operation), through port. Before executing next instruction, sure that High.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display Data (DDRAM) DDRAM stores display data maximum bits characters). DDRAM address address counter (AC) hexadecimal number. (refer Fig-1.) Fig-1. DDRAM Address
Fig-1. DDRAM Address Display 5-dot font width character 5-dot line display case line display with 5-dot font, address range DDRAM 4FH. (Refer Fig-2)
Fig-2. 1-line 32ch. display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
5-dot line display case line display with 5-dot font, address range DDRAM 27H, 67H. (refer Fig-3)
Fig-3. 2-line 32ch. display (5-dot font width)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
5-dot line display case line display with 5-dot font, address range DDARM 00H-13H, 20H-33H, 40H-53H, 60H-73H. (refer Fig-4)
(After Shift
Right)
Fig-4. 4-line 16ch. display (5-dot font width)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display 6-dot font width character When this device used 6-dot font width mode, SEG79 SEG80 must open 6-dot line display case line display with 6-dot font, address range DDRAM 00H-4FH. (Refer Fig-5)
Fig-5. 1-line 26ch. display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
6-dot line display case line display with 6-dot font, address range DDRAM 00H-27H, 40H-67H. (refer Fig-6)
Fig-6. 2-line 26h. display (6-dot font width)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
6-dot line display case line display with 6-dot font, address range DDARM 00H-13H, 20H-33H, 40H-53H, 60H-73H. (refer Fig-7)
(After Shift
Right)
Fig-7. 4-line 13ch. display (6-dot font width)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Timing Generation Circuit Timing generation circuit generates clock signals internal operations.
Address Counter (AC) Address Counter(AC) stores DDRAM/CGRAM/SEGRAM address, transferred from After writing into (reading from) DDRAM/CGRAM/SEGRAM, automatically increased (decreased) When "Low" "High", read through DB0~DB6 ports.
Cursor/Blink Control Circuit controls cursor/blink ON/OFF black/white inversion cursor position.
Driver Circuit Driver circuit common segment signals driving. Data from SEGRAM/CGRAM/CGROM transferred 80-bit segment latch serially, which then stored 80-bit shift latch. When each common selected 34-bit common register, segment data also output through segment driver from 80-bit segment latch. 1-line display mode, COM0 COM17 have 1/17 duty, 2-line 4-line mode, COM0 COM33 have 1/33 duty ratio.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
CGROM (Character Generator ROM) CGROM 8-dot character pattern. (refer Table Table CGROM Character Code Table
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
CGRAM (Character Generator RAM) CGRAM 8-dot characters. writing font data CGRAM, user defined character used. (Refer Table
Table Relationship between Character Code(DDRAM) Character Pattern(CGRAM) Character pattern
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Character pattern
When BE(Blink Enable bit) "High", blink controlled bit. displaying 5-dot font width, when "1", enabled dots will blink, when "1", enabled dots will blink, when "0", blink will happen. displaying 6-dot font width, when "1", enabled dots will blink, when "1", enabled dots will blink, when "0", blink will happen. Don't care
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
SEGRAM (Segment Icon RAM) SEGRAM segment control data segment pattern data. During 1-line display mode, COM0(COM17) makes data SEGRAM enable display icons. When used 2/4-line display mode COM0(COM33) does that. higher 2-bits blinking control data, lower 6-bits pattern data. (refer Table Fig-8) Table Relationship between SEGRAM address display pattern
Blinking
control Control Blinking Port 5-dot font width blink blink 6-dot font width blink blink
S1~S80 Icon pattern ON/OFF 5-dot font width S1~S78 Icon pattern ON/OFF 6-dot font width Don't care
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
5-dot font width
6-dot font width
Fig-8. Relationship between SEGRAM segment display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INSTRUCTION DESCRIPTION
OUTLINE overcome speed difference between internal clock KS0074 clock, KS0074 performs internal operation storing control information internal operation determined according signal from MPU, composed read/write data bus. (refer Table 6/10) Instruction divided largely four kinds, KS0074 function instructions display methods, data length, etc.) address instructions internal data transfer instructions with internal others address internal automatically increased decreased When "High", KS0074 operated according Instruction 1(Table when "Low", KS0074 operated according Instruction 2(Table 10).
Note During internal operation, Busy Flag (DB7) read High. Busy Flag check must proceeded next instruction. When program with Busy Flag (DB7) checking made, Fosc necessary) executing next instruction falling edge signal after Busy Flag (DB7) goes "Low"
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INSTRUCTION DESCRIPTION "High")
Table Instruction Execution Time (fosc kHz) Write "20H" DDRAM. DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. power down mode bit. :power down mode set, :power down mode disable Assign cursor moving direction. increment, decrement display shift enable bit. make display shift enabled lines bits Shift Enable instruction. "0":display shift disable Segment bi-direction function. Seg80 Seg1, Seg1 Seg80. display/cursor/blink on/off display display off, cursor cursor off, blink blink off. Assign font width, black/white inverting cursor, 4-line display mode control bit. 6-dot font width, 5-dot font width, black/white inverting cursor enable, black/white inverting cursor disable 4-line display mode, 1-line 2-line display mode. 1.53ms
Instruction
Instruction Code
Description
Clear Display Return Home
1.53ms
Power Down Mode
Entry Mode
Display ON/OFF Control
Extended function
39µs
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
(Table continued) Instruction Instruction Code Cursor Display Shift Cursor display shift. display shift, cursor shift, shift right, shift left. (when "1") Determine line display shift "1/0": line display shift enable/disable "1/0": line display shift enable/disable "1/0": line display shift enable/disable "1/0": line display shift enable/disable. (when "0") Determine line horizontal smooth scroll. "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable. interface data length 8-bit, 4-bit), numbers display line when "0", 2-line, 1-line), extension register, RE("0"), shift/scroll enable display shift enable scroll enable. reverse reverse display, normal display. RE("1") CGRAM/SEGRAM blink enable (BE) 1/0" CGRAM/SEGRAM blink enable/disable Description Execution Time (fosc kHz)
Shift Enable
Scroll Enable
Function
RE(0)
RE(1)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
(Table continued) Instruction Instruction Code CGRAM Address SEGRAM Address DDRAM Address Scroll Quantity Read Busy flag Address Write Data Read Data CGRAM address address counter. Description Execution Time (fosc
SEGRAM address address counter.
DDRAM address address counter.
quantity horizontal scroll. known whether during internal operation reading contents address counter also read. busy state, ready state. Write data into internal (DDRAM CGRAM SEGRAM). Read data from internal (DDRAM CGRAM SEGRAM).
Note When program with Busy Flag(DB7) checking made, Fosc necessary) executing next instruction signal after Busy Flag (DB7) goes "Low". Don't care
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display Clear
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, hence, bring cursor left edge first line display. Make entry mode increment (I/D "1").
Return Home
Return Home cursor return home instruction. DDRAM address "00H" into address counter. Return cursor original site return display original status, shifted. Contents DDRAM does change.
Power Down Mode
Power down mode enable instruction. "High", makes KS0074 suppress current consumption except current needed data storage executing next three functions. make output value COM/SEG ports disable voltage converter remove current through divide resistor power supply. This instruction used power sleep mode. When "Low", power down mode becomes disabled.
KS0074
Entry Mode
34COM/80SEG DRIVER CONTROLLER MATRIX
moving direction cursor display. Increment decrement DDRAM address (cursor blink) When "High", cursor/blink moves right DDRAM address increased When "Low", cursor/blink moves left DDRAM address decreased CGRAM/SEGRAM operates same DDRAM, when read from write CGRAM/SEGRAM. When "High", after DDRAM write, display enabled line bits Shift Enable instruction shifted right (I/D "0") left(I/D "1"). will seem cursor does move. When "Low", DDRAM read, CGRAM/SEGRAM read/write operation, shift display like this function performed.
data shift direction segment application set. Data Shift Direction Segment When "Low", segment data shift direction normal order from SEG1 SEG80. When "High", segment data shift direction reverse from SEG80 SEG1. using this instruction, efficiency application board area raised. setting instruction recommended same time level function instruction. must "1".
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display ON/OFF Control
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remained DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register remains data. Cursor Blink ON/OFF control When "High", cursor blink that performs alternate between high data display character cursor position. fosc frequency, blinking interval. When "Low", blink off.
Extended Function
Font Width control When "High", display character font width assigned 6-dot execution time becomes times than that 5-dot font width. user font, specified CGRAM, displayed into 6-dot font width, bit-5 bit-0,including leftmost space CGRAM.(refer Fig-9) When "Low", 5-dot font width set. Black/White Inversion enable When "High", black/white inversion cursor position set. this case display ON/OFF control instruction becomes don't care condition. fosc frequency kHz, inversion intervals. Line mode enable When "High", line display mode set. this case function instruction becomes don't care condition.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
6-bit
6-bit CGRAM character font (6-dot)
CGROM character font (5-dot)
8-bit
8-bit
(CGROM)
(CGRAM)
Fig-9. 6-dot font width CGROM/CGRAM
Cursor Display Shift
Shift right/left cursor position display, without writing reading display data. This instruction used correct search display data.(refer Table During 2-line mode display, cursor moves line after 40th digit line. 4-line mode, cursor moves next line, only after every 20th digit current line. Note that display shift performed simultaneously line enabled DS1-DS4 Shift Enable instruction. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed. During power consumption mode, display shift performed normally.
Table Shift patterns according bits Operation Shift cursor left, ADDRESS COUNTER decreased Shift cursor right, ADDRESS COUNTER increased Shift display left, cursor moves according display Shift display right, cursor moves according display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Shift/Scroll Enable
Horizontal Scroll Line Enable This instruction makes valid shift display line unit. HS1, HS2, indicate each line scrolled, each scroll performed individually each line. line 1-line display mode line 2-line display mode scrolled, "High". line scroll needed 2-line mode, "High". (refer Table
Display Shift Line Enable This instruction selects shifting line shifted according each line mode display shift right/left instruction. DS1, DS2, indicate each line shifted, each shift performed individually each line. "High" (enable) line mode, only line shifted line shifted. When only "High", only half line shifted. bits (DS1 DS4) "Low" (disable), display shifted.
Table Relationship between signal Enable Enabled common signals during shift HS1/DS1 HS2/DS2 HS3/DS3 HS4/DS4 COM1 COM8 COM9 COM16 COM17 COM24 COM25 COM32 part display line that corresponds enabled common signal shifted. Description
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Function
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", means 1-line display mode. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable this instruction, must "Low". Display shift enable selection bit. When "High", enable display shift line. When "Low", enable smooth scroll. This accessed only when input "High". Reverse enable When "High", display data reversed. I.e., black black dots become white. When "Low", display mode normal display.
white dots become
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. When 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", 1-line display mode set. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable When "High", extended function registers, SEGRAM address registers, bit, HS/DS bits shift/scroll enable instruction bits function register accessed. CGRAM/SEGRAM data blink enable "High", makes user font CGRAM segment SEGRAM blinking. quantity blink assigned highest CGRAM/SEGRAM.
CGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU.
SEGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
DDRAM Address
DDRAM address This instruction makes DDRAM data available from MPU. 1-line display mode DDRAM address from "00H" "4FH". 2-line display mode DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H". 4-line display mode DDRAM address from "00H" "13H" line, from "20H" "33H" line, from "40H" "53H" line from "60H" "73H" line.
Scroll Quantity
Setting SQ0, horizontal scroll quantity controlled units. (Refer Table this case KS0074 show hidden areas DDRAM executing smooth scroll from dots.
Table Scroll quantity according bits Function shift shift left 1-dot shift left 2-dot shift left 3-dot shift left 47-dot shift left 48-dot
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Read Busy Flag Address
This instruction shows whether KS0074 internal operation not. resultant High, internal operation progress should wait until Low, which then next instruction performed. this instruction value address counter also read.
Write data
Write binary 8-bit data DDRAM/CGRAM/SEGRAM. selection from DDRAM, CGRAM, SEGRAM, previous address instruction DDRAM address set, CGRAM address set, SEGRAM address set. instruction also determines direction RAM. After write operation, address automatically increased/decreased according entry mode.
Read data from
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, direction determined. data read several times without address instruction before read operation, correct data obtained from second, first data would incorrect, there time margin transfer data. DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction also transfer data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM/SEGRAM read operation, display shift executed correctly. case write operation, increased/decreased read operation after this. this time, indicates next address position, previous data only read read instruction.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INSTRUCTION DESCRIPTION "LOW")
Table Instruction Instruction Instruction Code Clear Display Return Home Write "20H" DDRAM. DDRAM address "00H" from DDRAM address "00H" from return cursor original position shifted. contents DDRAM changed. Assign cursor moving direction. increment, decrement. display shift enable bit. :make entire display shift lines during DDRAM write, "0":display shift disable display/cursor/blink on/off display display off, cursor cursor off, blink blink off. Assign font width, black/white inverting cursor, 4-line display mode control bit. 6-dot font width, 5-dot font width, black/white inverting cursor enable, black/white inverting cursor disable 4-line display mode, 1-line 2-line display mode Cursor display shift. display shift, cursor shift, shift right, shift left Description Execution Time (fosc kHz) 1.53ms
1.53ms
Entry Mode
39µs
Display ON/OFF Control
39µs
Extended function
39µs
Cursor Display Shift
39µs
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
(Table continued) Instruction Instruction Code Determine line horizontal smooth scroll. "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable "1/0" line scroll enable/disable interface data length 8-bit, 4-bit numbers display line when "0", 2-line, 1-line extension register, RE("0"), RE("1") CGRAM/SEGRAM blink enable (BE) 1/0" CGRAM/SEGRAM blink enable/disable CGRAM address address counter. Description Execution Time (fosc kHz)
Scroll Enable
39µs
Function
RE(0)
39µs
RE(1)
39µs
CGRAM Address SEGRAM Address DDRAM Address Scroll Quantity Read Busy flag Address Write Data Read Data
39µs
SEGRAM address address counter.
39µs
DDRAM address address counter.
39µs
quantity horizontal scroll. known whether during internal operation reading contents address counter also read. busy state, ready state. Write data into internal (DDRAM CGRAM SEGRAM). Read data from internal (DDRAM CGRAM SEGRAM).
39µs
43µs 43µs
Note When program with Busy Flag (DB7) checking made, Fosc necessary) executing next instruction falling edge signal after Busy Flag (DB7) goes "Low". don't care
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display Clear
Clear display data writing "20H" (space code) DDRAM address, DDRAM address "00H" into (address counter). Return cursor original status, hence, bring cursor left edge first line display. entry mode increment mode (I/D "1").
Return Home
Return Home cursor return home instruction. DDRAM address "00H" into address counter. Return cursor original site return display original status, shifted. Contents DDRAM does change.
Entry Mode
moving direction cursor display. Increment decrement DDRAM address (cursor blink) When "High", cursor/blink moves right DDRAM address increased When "Low", cursor/blink moves left DDRAM address decreased CGRAM/SEGRAM operates identically DDRAM, when reading from writing CGRAM/SEGRAM. When "High", after DDRAM write, entire display lines shifted right (I/D "0") left(I/D "1"). will seem cursor does moving. When "Low", DDRAM read, CGRAM/SEGRAM read/write operation, shift entire display performed.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Display ON/OFF Control
Control display/cursor/blink ON/OFF register. Display ON/OFF control When "High", entire display turned When "Low", display turned off, display data remained DDRAM. Cursor ON/OFF control When "High", cursor turned When "Low", cursor disappeared current display, register remains data. Cursor Blink ON/OFF control When "High", cursor blink that performs alternate between high data display character cursor position. fosc frequency, blinking interval. When "Low", blink off.
Extended Function
Font Width control When "High", display character font width assigned 6-dot execution time becomes times than that 5-dot font width. user font, specified CGRAM, displayed into 6-dot font width, bit-5 bit-0,including leftmost space CGRAM.(Refer Fig-10) When "Low", 5-dot font width set. Black/White Inversion enable When "High", black/white inversion cursor position set. this case display ON/OFF control instruction becomes don't care condition. fosc frequency kHz, inversion intervals. Line mode enable When "High", line display mode set. this case function instruction becomes don't care condition.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
6-bit
6-bit CGRAM character font (6-dot)
CGROM character font (5-dot)
8-bit
8-bit
(CGROM)
(CGRAM)
Fig-10. 6-dot font width CGROM/CGRAM
Cursor Display Shift
Shift right/left cursor position display without writing reading display data. This instruction used correct search display data.(Refer Table During 2-line mode display, cursor moves line after 40th digit line. 4-line mode, cursor moves next line, only after every 20th digit current line. Note that display shift performed simultaneously line. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed.
Table Shift patterns according bits Operation Shift cursor left, ADDRESS COUNTER decreased Shift cursor right, ADDRESS COUNTER increased Shift display left, cursor moves according display Shift display right, cursor moves according display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Scroll Enable
Horizontal Scroll Line Enable This instruction makes valid shift display line unit. HS1, HS2, indicate each line scrolled, each scroll performed individually each line. line 1-line display mode line 2-line display mode scrolled, "High". line scroll needed 2-line mode, "High". (refer Table
Function
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. speak, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", 1-line display mode set. When "High", 2-line display mode set. When "High", invalid, means 4-line mode independent bit. Extended function registers enable this instruction, must "Low".
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Interface data length control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. Hence, signal select 8-bit 4-bit mode. 4-bit mode, required transfer 4-bit data twice. Display line number control variable only when extended function instruction Low. When "Low", 1-line display mode set. When "High", 2-line display mode set. When "High", invalid, 4-line mode independent bit. Extended function registers enable When "High", extended function registers, SEGRAM address registers, bits scroll enable instruction bits function register accessed. CGRAM/SEGRAM data blink enable "High", makes user font CGRAM segment SEGRAM blinking. quantity blink assigned highest CGRAM/SEGRAM.
CGRAM Address
CGRAM address This instruction makes CGRAM data available from MPU. SEGRAM Address
SEGRAM address This instruction makes SEGRAM data available from MPU.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
DDRAM Address
DDRAM address This instruction makes DDRAM data available from MPU. 1-line display mode DDRAM address from "00H" "4FH". 2-line display mode DDRAM address line from "00H" "27H", DDRAM address line from "40H" "67H". 4-line display mode DDRAM address from "00H" "13H" line, from "20H" "33H" line, from "40H" "53H" line from "60H" "73H" line.
Scroll Quantity
Setting SQ0, horizontal scroll quantity controlled units. (Refer Table 12). this case KS0074 execute smooth scroll from dots.
Table Scroll quantity according bits Function shift shift left 1-dot shift left 2-dot shift left 3-dot shift left 47-dot shift left 48-dot
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Read Busy Flag Address
This instruction shows whether KS0074 internal operation not. resultant High, internal operation progress should wait until become "Low", which then next instruction performed. this instruction value address counter also read.
Write data
Write binary 8-bit data DDRAM/CGRAM/SEGRAM. selection from DDRAM, CGRAM, SEGRAM, previous address instruction DDRAM address set, CGRAM address set, SEGRAM address set. instruction also determines direction RAM. After write operation, address automatically increased/decreased according entry mode.
Read data from
Read binary 8-bit data from DDRAM/CGRAM/SEGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, direction determined. data read several times without address instruction before read operation, correct data from second, first data would incorrect, there time margin transfer data. case DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction also transfer data output data register. After read operation address counter automatically increased/decreased according entry mode. After CGRAM/SEGRAM read operation, display shift executed correctly. case write operation, increased/decreased like read operation after this. this time, indicates next address position, previous data only read read instruction.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INTERFACE WITH
KS0074 transfer data mode (4-bit 8-bit) serial mode with MPU. Hence, both types 8-bit used. case 4-bit mode, data transfer performed twice transfer byte data. When interfacing data length 4-bit, only ports, from DB7, used data bus. first higher 4-bit case 8-bit mode, contents DB7) transferred, then lower 4-bit case 8-bit mode, contents DB3) transferred. transfer performed twice. Busy Flag outputs "High" after second transfer ended. When interfacing data length 8-bit, transfer performed time through ports, from DB7. "Low", serial transfer mode set.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Interface with Mode Interface with 8-bits 8-bits used, KS0074 connect directly with that. this case, port need interface each other. Example timing sequence shown below.
!"!#
!"!#
Example 8-bit Mode Timing Sequence Interface with 4-bits 4-bits used, KS0074 connect directly with this. this case, port need interface each other. transfer performed twice. Example timing sequence shown below.
:-6-:
:-6-:
Example 4-bit Mode Timing Sequence
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Interface with Serial Mode
When port input "Low", serial interface mode started. this time, three ports, SCLK (synchronizing transfer clock), (serial input data), (serial output data), used. KS0074 used with other chips, chip select port (CS) used. setting "Low", KS0074 receive SCLK input. "High", KS0074 reset internal transfer counter. Before transfer real data, start byte transferred. composed succeeding "High" bits, read write control (R/W), register selection (RS), that indicates start byte. Whenever succeeding "High" bits detected KS0074, resets serial transfer counter prepares receive next information. next input data register selection which determine which register used, read write control that determine direction data. Then transferred, which must have "Low" value show start byte. (Refer Write Operation (R/W After start byte transferred from KS0074, 8-bit data transferred which divided into bytes, each byte bit's real data bit's partition token data. example, real data "10110001" D7), then serially transferred data becomes "1011 0000 0001 0000" where bits must "0000" safe transfer. transfer several bytes continuously without changing bit, start byte transfer needed only first starting time. I.e., after first start byte transferred, real data succeeding transferred. Read Operation (R/W After start byte transferred KS0074, receive 8-bit data through port time from LSB. Wait time needed insert between start byte data reading, internal reading from requires some delay. Continuous data reading possible such serial write operation. also needs only start bytes, only some delay between reading operations each byte inserted. During reading operation, KS0074 observes succeeding "High" from MPU. detected, KS0074 restarts serial operation once prepares receive bit. continuous reading operation, port must "Low".
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
)++!
Timing Diagram Serial Data Transfer
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Timing Diagram Continuous Data Transfer
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
APPLICATION INFORMATION ACCORDING PANEL
Panel character line format (5-dot font,1/17 duty)
Panel character line format (5-dot font, 1/33 duty)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Panel character line format (5-dot font, 1/33 bias)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Panel character line format (6-dot font, 1/33 bias)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INITIALIZING
Initializing Internal Reset Circuit When power turned KS0074 initialized automatically power reset circuit. During initialization, following instructions executed, BF(Busy Flag) kept "High"(busy state) initialization. Display Clear instruction Write "20H" DDRAM Functions instruction 8-bit mode 2-line display mode Extension register disable CGRAM/SEGRAM blink Horizontal scroll enable Normal display (Not reversed display) Control Display ON/OFF instruction Display Cursor Blink Entry Mode instruction Increment entire display shift Normal direction segment port Extension Function instruction 5-dot font width character display Normal cursor (8th line) 4-line display mode, 2-line mode because N("1")
Enable Shift instruction 0000 Scroll line disable 0000 Shift line disable
scroll Quantity instruction 000000 scroll
Initializing Hardware RESET input When RESET "Low", KS0074 initialized like case power reset. During power reset operation, this ignored.
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
INITIALIZING INSTRUCTION
8-bit interface mode
Power
Wait more than after rises 4.5V (DL="1") Function
Condition:
4-bit interface 8-bit interface 1-line mode 2-line mode
Wait more than 39µs Dsplay ON/OFF Control Wait more than 39µs ClearDsplay display display cursor cursor blink blink
Wait more than 1.53ms decrement mode increment mode entire shift entire shift
Entry Mode
Initialization
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
4-bit interface mode
Power
Wait more than after rises 4.5V (DL="0") Function
Condition:
4-bit interface 8-bit interface 1-line mode 2-line mode
Wait more than 39µs
Function
Wait more than 39µs Dsplay ON/OFF Control display display cursor cursor blink blink
Wait more than
Clear Dsplay
Wait more than 1.53ms
Entry ModeSet
decrement mode increment mode entire shift entire shift
Initialization
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
EXAMPLE INSTRUCTION DISPLAY CORRESPONDENCE
"Low"
1.Power Supply Initialized internal power reset circuit. DISPLAY
2.Function 8-bit, 1-line, RE(0)
3.Display ON/OFF Control Display/Cursor
4.Entry Mode Increment
5.Write Data DDRAM Write
6.Write Data DDRAM Write
7.Write Data DDRAM Write
Write data DDRAM Write SAMS_
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Write data DDRAM Write
SAMSU_
Write data DDRAM Write
SAMSUN_
Write data DDRAM Write
SAMSUNG_
Cursor Display Shift Cursor shift right
SAMSUNG
Entry Mode Entire display shift enable
SAMSUNG
Write data DDRAM Write
AMSUNG
Write data DDRAM Write
MSUNG
Write data DDRAM Write
SUNG KS0_
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Write data DDRAM Write
KS00_
Write data DDRAM Write
KS007_
Write data DDRAM Write
KS0073_
Cursor Display Shift Cursor shift left
KS0073
Write Data DDRAM Write
KS0074_
Return Home
SAMSUNG KS0074
Clear Display
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
"High"
Power Supply Initialized internal power reset circuit.
Function 8-bit, RE(1)
Extended Function 5-font, 4-line
Function RE(0)
Display ON/OFF Control Display/Cursor
Write data DDRAM Write
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
22#3
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
"!&0 22#3&&
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
'()%*&''(
'()%*&'
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
&''(
SAMSUNG KS0074
DRIVER CONTROLLER
&''(
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
FRAME FREQUENCY
1/17 duty cycle
1-line selection period
COM1
Frame Frame
Item 5-dot font width 1-line selection period Frame frequency clocks 79.4Hz
Display Font Width 6-dot font width clocks 66.2Hz fosc clock 3.7µs)
1/33 duty cycle
COM1
Frame Frame
Item 5-dot font width 1-line selection period Frame frequency clocks 81.8Hz
Display Font Width 6-dot font width clocks 68.2Hz fosc clock
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
POWER SUPPLY DRIVING PANEL
When external power supply used
When internal booster used
(Boosting three times)
Boosted output voltage should exceed maximum value driving voltage. Especially, voltage over 4.3V should input reference voltage (Vci) when boosting three times. voltage over 5.5V should input reference voltage (Vci) when boosting twice. value resistance, according number lines, duty ratio bias, shown below. (Refer Table Table Duty Ratio Power Supply Driving Item Number lines Duty ratio Bias Divided resistance 1/17 Data 1/33 1/6.7 2.7R
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
MAXIMUM ABSOLUTE RATE
Characteristic Power Supply Voltage Power Supply Voltage Input Voltage Operating Temperature Storage Temperature Symbol VLCD TOPR TSTG Value -0.3 +7.0 -15.0 +0.3 -0.3 +0.3 +125 Unit
Voltage greater than above damage circuit (VDDV1V2V3V4V5)
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
ELECTRICAL CHARACTERISTICS
Characteristics (VDD 2.7V 5.5V, Ta=-30 Characteristic Operating Voltage Supply Current Symbol Condition Internal oscillation external clock. (VDD=3.0V,fosc=270KHz Input Voltage (Except OSC1) VIH1 VIL1 VDD=2.7 VDD=3.0 Input Voltage (Osc1) Output Voltage (DB0 DB7) Output Voltage(2) (Except DB7) Voltage Drop VIH2 VIL2 VOH1 VOL1 VOH2 VOL1 VdCOM VdSEG Input Leakage Current Input Current VIN=0V VIN=0V, VDD=3V (PULL Internal Clock (external External Clock duty Voltage Converter Out2 (Vci 4.5V) Voltage Converter Out3 (Vci 2.7V) Voltage Converter Input Driving Voltage VLCD VDD-V5 Bias 1/6.7 Bias 13.0 13.0 VOUT3 VOUT2 C=1µF, IOUT 0.25mA, fOSC=270KHz -4.3 -5.1
0.15
Unit
0.7VDD -0.3 -0.3 0.7VDD 0.75VDD 0.8VDD
0.2VDD 0.2VDD 0.2VDD 0.2VDD -120
IOH=-0.1mA IOL=0.1 IO=-40 IO=40 ±0.1mA
fOSC
Rf=91k (VDD=5V)
-3.0
-4.2
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Characteristics
(VDD=4.5 5.5V, Ta=-30 Mode Item Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (refer Fig-15) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (refer Fig-16) Setup Time Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) Serial Interface Mode (refer Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tsu1 tsu2 tR,tF tR,tF tsu1 tsu2 Unit
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
Characteristics (continued)
(VDD=2.7 4.5V, Ta=-30 Mode Item Cycle Time Rise Fall Time Pulse Width (High, Low) Write Mode (refer Fig-15) Setup Time Hold Time Data Setup Time Data Hold Time Cycle Time Rise Fall Time Pulse Width (High, Low) Read Mode (refer Fig-16) Setup Time Hold Time Data Output Delay Time Data Hold Time Serial Clock Cycle Time Serial Clock Rise/Fall Time Serial Clock Width (High, Low) Serial Interface Mode (refer Fig-17) Chip Select Setup Time Chip Select Hold Time Serial Input Data Setup Time Serial Input Data Hold Time Serial Output Data Delay Time Serial Output Data Hold Time Symbol tsu1 tsu2 tR,tF tR,tF tsu1 tsu2 1000 1000 Unit
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
VIH1
VIL1 tsu1
VIL1 VIH1 VIL1 VIH1 tSU2 VIH1 VIL1
VIL1
VIL1
DB0~DB7
VIL1
Valid Data
VIH1 VIL1
Fig-15. Write Mode
VIH1
VIL1 VIH1 VIH1 VIL1 VOH1 VIH1 VIL1 VOH1 VOL1 VIL1 VIH1
DB0~DB7
VOL1
Valid Data
Fig-16. Read Mode
KS0074
34COM/80SEG DRIVER CONTROLLER MATRIX
VIL1 tSU1 VIH1 VIL1
VIH1 VIL1 tSU2
VIH1 VIL1
VIL1 VIH1 VIL1
SCLK
VOH1 VOL1
Fig-17. Serial Interface Mode Reset Timing (VDD 5.5V, +85oC) Item Reset level width (refer Fig-18) Symbol tRES Unit
tRES
RESET
Fig-18. Reset Timing Diagram

34COM/80SEG DRIVER CONTROLLER MATRIX KS0074 matrix driver control

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