DRIVER CONTROLLER June. 1999. Ver. Tae-Kwang, Park parktk@sa
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KS0032
DRIVER CONTROLLER
June. 1999. Ver.
Tae-Kwang, Park parktk@samsung.co.kr
Contents this document subject change without notice. part this document reproduced transmitted form means, electronic mechanical, purpose, without express written permission Driver Team.
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
KS0032 Specification Revision History Version Original ECKON added circuit added Page (4/5) (3/5) (3/5) (2/5) Page E_RD signal description changed E_RD: Active signal writing command 6800 mode high enable signal reading command 8080 mode. E_RD: Active signal writing command high enable signal reading command 6800 mode, enable signal reading command 8080 mode. Page DRIVER OUTPUT added Page Power timing added Page IDD1 (VDD 2.4~3.6V): 150µA 50µA Page IDD1 (VDD 3.6~5.5V): 250µA 80µA Page CGROM character size changed from 254. Page RW_WR active active high Page RW_WR active enable Page Wait more than 1.2us Busy Check delete Busy Check" Page Wait more than 1.2us Busy Check delete Busy Check" Jun.1999 Jun.1999 May.1999 Apr.1999 Content Date Feb.1999 Mar.1999
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
CONTENTS
INTRODUCTION FEATURES BLOCK DIAGRAM CONFIGURATION CENTER COORDINATES. DESCRIPTION POWER SUPPLY. SYSTEM CONTROL INTERFACE DRIVER OUTPUT TEST. FUNCTIONAL DESCRIPTION. MICROPROCESSOR INTERFACE ADDRESS COUNTER (AC).10 DISPLAY DATA (DDRAM) CHARACTER GENERATOR (CGROM) CHARACTER GENERATOR (CGRAM) DRIVER CIRCUIT INSTRUCTION DESCRIPTION.14 INITIALIZING.18 HARDWARE RESET.18 INSTRUCTION INITIALIZING WITH RESET DRIVING POWER SUPPLY CIRCUIT INTERFACE INTERFACING WITH 8080-SERIES MICROPROCESSORS.23 INTERFACING WITH 6800-SERIES MICROPROCESSORS.23 APPLICATION INFORMATION PANEL.24 FRAME FREQUENCY.28 MAXIMUM ABSOLUTE RATE.29 ELECTRICAL CHARACTERISTICS.30 CHARACTERISTICS.30 CHARACTERISTICS
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
INTRODUCTION
This character driver controller liquid crystal matrix display systems display 2-line characters with dots format. capable interfacing various microprocessors, supporting 4-bit 8-bit parallel mode. Voltage follower bias circuit built
FEATURES
Driver Output Circuits common outputs segment outputs Applicable Duty Ratio Font size Display size 2-line characters Duty 1/16 Contents outputs characters
On-chip Display Data Character Generator (CGROM): 10,160 bits (254 characters dots) Character Generator (CGRAM): bits characters dots) Display Data (DDRAM): bits characters 2-line) 8-bit parallel interface with 6800-series 8080-series 4-bit parallel interface with 6800-series 8080-series Simple instruction bi-directional types application available) Hardware reset (RESETB) Internal oscillator circuit Voltage follower bias circuit Automatic power reset circuit Supply voltage (VDD): 5.5V driving voltage (VLCD VSS): 6.0V Max.
Microprocessor Interface
Function
On-chip Analog Circuit
Operating Voltage Range
Power Consumption Package Type Gold bumped chip
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
BLOCK DIAGRAM
ECKON Power Reset (POR) RESETB Input Buffer RW_WR E_RD Parallel Interface 4-/8-bit (6800/8080 -series) Instruction Register (IR)
DIRC
Oscillator
Timing Generator
Instruction Decoder bits Shift Register
COM1 Common COM16 Driver
Address Counter Data Register (DR)
Display Data (DDRAM) bits bits Shift Register
Data Output Register (OR)
Character Generator (CGROM) 10,160 bits
bits Latch Circuit
SEG1 Segment SEG80 Driver
Busy Flag Character Generator (CGRAM) bits
Cursor Blink Controller
Driving Voltage Selector
Voltage Follower Bias Resistor
Segment Data Conversion DIRS
Figure Block Diagram
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
CONFIGURATION
(0,0)
KS0032
DUMMY_PAD
Figure KS0032 Chip Configuration Table KS0032 Dimensions Item Chip size pitch Bumped size Bumped height Align Coordinate
30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm 30µm
Size 5430 (Typ.) 1410
Unit
(-2600, +605)
(+2600, +590) 60µm
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
CENTER COORDINATES
Table Center Coordinates [Unit:
Name
DUMMY ECKON RESETB RW_WR E_RD TEST DIRC DIRS DUMMY COM1 COM2 COM3 COM4 COM5 COM6
-1935 -1845 -1755 -1665 -1575 -1485 -1395 -1305 -1215 -1125 -1035 -945 -855 -765 -675 -585 -495 -405 -315 -225 -135 1035 1125 1215 1305 1395 1485 1575 1665 1755 1845 1935 2605 2605 2605 2605 2605 2605
-595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -595 -555 -485 -415 -345 -275 -205
Name
COM7 COM8 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 DUMMY DUMMY SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46
2605 2605 2605 2605 2605 2605 2605 2605 2605 2415 2345 2275 2205 2135 2065 1995 1925 1855 1785 1715 1645 1575 1505 1435 1365 1295 1225 1155 1085 1015 -105 -175 -245 -315 -385
-135
Name
SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 DUMMY DUMMY SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9
-455 -525 -595 -665 -735 -805 -875 -945 -1015 -1085 -1155 -1225 -1295 -1365 -1435 -1505 -1575 -1645 -1715 -1785 -1855 -1925 -1995 -2065 -2135 -2205 -2275 -2345 -2415 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605 -2605
-135 -205 -275 -345 -415 -485 -555
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
DESCRIPTION
POWER SUPPLY
Table Description Name Supply Supply Power supply Ground Bias voltage Input driving driving voltage outputs. Voltages should have following relationship; These voltages generated following table. bias bias (4/5) (3/5) (2/5) (1/5) Description
SYSTEM CONTROL
Table Description (Continued) Name ECKON Description Clock source selection input When ECKON "High", External clock used system clock, internal oscillator circuit turned OFF. When ECKON "Low", internal oscillator used. External clock input (When ECKON "High") must fixed "High" "Low" when internal oscillation circuit used (When ECKON "Low"). interface selection input "Low", 8080-series "High", 6800-series direction selection input When DIRC "Low", COM1 COM2 COM15 COM16 When DIRC "High", COM16 COM15 COM2 COM1 direction selection input When DIRS "Low", SEG1 SEG2 SEG79 SEG80 When DIRS "High", SEG80 SEG79 SEG2 SEG1
DIRC
DIRS
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
INTERFACE
Table Description (Continued) Name RESETB Description Reset input Initialization performed "Low" level sensing RESETB signal. Chip selection input KS0032 selected while "Low". Register selection input When "Low", instruction register When "High", data register 8080-series interface mode, this connected active high write signal. 6800-series interface mode, this connected MPU. When RW_WR "High", read mode When RW_WR "Low", write mode 8080-series interface mode, this connected enable read signal. 6800-series interface mode, this connected enables read write command according RW_WR signal. When 8-bit interface mode, used bi-directional data During 4-bit mode, only used. this case pins don't care (connect "High", "Low" open).
RW_WR
E_RD
DRIVER OUTPUT
Table Description (Continued) Name COM1 COM16 SEG1 SEG80 Description Common signal output character display Segment signal output character display
TEST
Table Description (Continued) Name TEST Description Test This used normal operation should connect "Low".
*NOTE: DUMMY These pins should opened (floated).
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
KS0032 kinds interface type with MPU: 4-bit 8-bit bus. 4-bit 8-bit selected instruction register, 6800-series 8080-series selected pin. Table Various Kinds Interface according 6800 series 8080 series 8-bit 4-bit 8-bit 4-bit RW_WR E_RD
NOTE: Don't care ("High", "Low" Open) (H): fixed "High" (VDD) (L): fixed "Low" (VSS)
"High" 6800-series MPU, "Low" 8080-series "High" 8-bit mode, "Low" 4-bit mode CSB: "High" chip selected, "Low" chip selected "High" data register, "Low" instruction register RW_WR: read write indicating signal 6800 mode, active high signal writing command 8080 mode. E_RD: Active signal writing command high enable signal reading command 6800 mode, enable signal reading command 8080 mode.
Parallel Interface During writing operation, 8-bit registers, data register (DR) instruction register (IR), used. data register (DR) used temporary data storage place being written into DDRAM CGRAM. Target selected address instruction. Instruction register (IR) used only store instruction code transferred from MPU. select register, input used. During reading operation, 8-bit output data register (OR) used. output data register (OR) used temporary data storage place being read from DDRAM CGRAM. Destination selected address instruction. After address set, first reading 8-bit mode (first second reading 4-bit mode) dummy cycle (figure valid data comes from second reading 8-bit mode (from reading 4-bit mode). dummy cycle makes address counter (AC) indicate correct address. recommended address before writing. instruction read operation supported indicating internal operation being processed (Busy Flag). 4-bit mode, needed transfer 4-bit data (through DB7) times. high order bits (for 8-bit mode DB7) transferred before order bits (for 8-bit mode DB3) read write transaction. pins floated this 4-bit mode. After RESETB operation, KS0032 considers first 4-bit data from high order bits 4-bit mode.
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
RW_WR E_RD
Instruction rite Busy Flag Read Dummy Data Read
Valid Data
Valid Data Read
Data rite
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (6800-series Mode)
RW_WR E_RD
Instruction rite Busy Flag Read Dummy Data Read
Valid Data
Valid Data Read
Data rite
Figure Timing Diagram 8-bit Parallel Mode Data Transfer (8080-series Mode)
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
RW_WR E_RD
Upper 4-bit Lower 4-bit
Instruction rite
Busy Flag Address Read
Dummy Data Read
Valid Data Read
Data rite
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (6800-series Mode)
RW_WR E_RD
Upper 4-bit Lower 4-bit
Instruction rite
Busy Flag Addr Read
Dummy Data Read
Valid Data Read
Data rite
Figure Timing Diagram 4-bit Parallel Mode Data Transfer (8080-series Mode) Busy Flag When "High" read status operation, indicates that internal operation busy status accept only read status instruction. cycle time correct, microprocessor needs check this flag before each instruction, except display clear instruction.
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
ADDRESS COUNTER (AC)
Address Counter (AC) KS0032 stores DDRAM CGRAM address. After writing into reading from DDRAM CGRAM, automatically increased decreased according entry mode.
DISPLAY DATA (DDRAM)
DDRAM stores display data maximum bits characters). DDRAM address address counter (AC) hexadecimal number.
Display shift performed
Display shift left performed
Display shift right performed Figure DDRAM Address
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
CHARACTER GENERATOR (CGROM)
CGROM 8-dot characters. CGROM character code CGRAM character data area. Table CGROM Character Code (00)
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
CHARACTER GENERATOR (CGRAM)
CGRAM 8-dot characters. writing font data CGRAM, user defined character used. Table Relationship between Character Code (DDRAM) Character Pattern (CGRAM) Character code (DDRAM data) CGRAM address CGRAM data Pattern number
(00h)
Pattern
(01h)
Pattern
NOTE: Don't care
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
DRIVER CIRCUIT
Driver circuit common segment signals driving LCD. Data from CGRAM CGROM transferred 80-bit segment register serially, then they stored 80-bit shift latch. COM1 COM16 have 1/16 duty ratio. bi-directional function selected DIRS input, shift direction selected DIRC input. Table Data Shift Direction DIRS High data shift direction SEG1 SEG2 SEG3 SEG78 SEG79 SEG80 SEG80 SEG79 SEG78 SEG3 SEG2 SEG1
Table Data Shift Direction DIRC High data shift direction COM1 COM2 COM3 COM14 COM15 COM16 COM16 COM15 COM14 COM3 COM2 COM1
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
INSTRUCTION DESCRIPTION
Table Instruction Table Instruction *Clear display
Description Write "20H" DDRAM DDRAM address "00H" from DDRAM address from cursor returns position. contents DDRAM changed. Assign cursor moving direction enable shift entire display display (D), cursor (C), blinking cursor control cursor moving display shift control bit, direction, without changing DDRAM data interface data length (DL: 4-bit 8-bit) instruction CGRAM address address counter. DDRAM address address counter. Whether internal operation known reading contents address counter also read Write data into DDRAM CGRAM Read data from DDRAM CGRAM
Return home
Entry mode Display control Cursor display shift Function CGRAM address DDRAM address Read busy flag address Write data Read data
("-": Don't care)
NOTES: Instruction execution time depends internal process time KS0032, therefore necessary provide time larger than interface cycle time (tc) between execution successive instructions. "Clear Display" instruction 850µs execution time (when fosc 40.0kHz), check Busy flag wait more than 850µs after using "Clear Display" instruction.
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
Clear Display
Clear display data writing "20H" (space code CGROM) DDRAM address, DDRAM address "00H" into (address counter). this instruction, CGROM address "20H" have space code. display position shifted then returns original positions. Namely, when display data shifted cursor blinking displayed, bring cursor left edge first line display. makes entry mode increment (I/D "High"). Return Home
Return Home instruction field makes cursor return home. DDRAM address from cursor returns position. contents DDRAM changed. Entry Mode
moving direction cursor display after data writing reading instruction.
I/D: Increment decrement DDRAM CGRAM address (cursor blink) After DDRAM CGRAM data write/read operation, DDRAM/CGRAM address increased (I/D "High") decreased (I/D "Low") case DDRAM data transfer operation cursor blink turned cursor blink moves right (I/D "High") left (I/D "Low"), CGRAM data transfer operation, cursor blink does move. Shift entire display When DDRAM read (CGRAM read/write) operation "Low", entire display shift. Only when "High" DDRAM write operation, entire display shift according value (I/D "1": shift left, "0": shift right). Display Control
Control display cursor/blink register
Display Control When "High", entire display turned When "Low", entire display turned OFF, display data remained DDRAM. Cursor Control When "High", cursor turned When "Low", cursor disappeared current display, register remains data. Cursor Blink Control When "High", cursor blink that performs alternate between high data (black pattern) display character cursor position. When "Low", blink OFF.
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Cursor Display Shift
Without writing reading display data, shift right left cursor position display. This instruction used correct search display data (refer table 10). Note that display shift performed simultaneously line. When displayed data shifted repeatedly, each line shifted individually. When display shift performed, contents address counter changed. Table Shift Patterns According Bits Function Operation Shift cursor left, decreased Shift cursor right, increased Shift display left, cursor moves according display Shift display right, cursor moves according display
Interface Data Length Control When "High", means 8-bit mode with MPU. When "Low", means 4-bit mode with MPU. When 4-bit mode, needs transfer 4-bit data times. CGRAM Address
CGRAM address This instruction makes CGRAM data available from user defined character pattern. CGRAM address from 0Fh. DDRAM Address
DDRAM address Before writing reading data into from RAM, address Address instruction. Next, when data written read succession, address automatically increased (when "High") decreased (when "Low"). address ranges (1st line) (2nd line).
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
Read Busy Flag Address
This instruction shows whether KS0032 internal operation not. resultant "High", means internal operation progress have wait until "Low", then next instruction performed. this instruction read also value address counter. Write Data
Write binary data DDRAM CGRAM. selection from DDRAM CGRAM previous address instruction (DDRAM address set, CGRAM address set). After write operation, address automatically increased decreased according entry mode. Read Data
Read binary data from DDRAM CGRAM. selection previous address instruction. address instruction performed before this instruction, data that read first invalid, because direction determined. read data several times without address instruction before read operation, correct data from second, first data would incorrect, because there time margin transfer data. case DDRAM read operation, cursor shift instruction plays same role DDRAM address instruction: also transfers data output data register. After read operation address counter automatically increased decreased according entry mode. After CGRAM read operation, display shift executed correctly. case write operation, after this operation, increased/decreased like read operation. this time, indicates next address position, read only previous data read instruction. address dummy data, correct data come from second read transaction. After reading operation, address increased automatically.
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
INITIALIZING
HARDWARE RESET
When power turned KS0032 initialized automatically power reset circuit (refer figure case RESETB becomes "Low" durable state more than 1.2µs (VDD 3V), KS0032 initialized too. During initialization, following instructions executed, (Busy Flag) kept "High" (busy state) initialization. Display Clear DDRAM data "20H" Return Home Address counter "00H" Entry Mode Instruction Address counter increment mode. Entire display shift disabled. Display Control Instruction cursor blink display Function Instruction 8-bit interface mode CGRAM DDRAM Address address counter "00H".
tRDD
0.9VDD 0.1VDD 0.1VDD
tOFF
0.1VDD
Rising Time Power Time
tRDD tOFF
Note: upper power conditions satisfied power sequence, internal Power Reset (POR) circuit will operates normally.
Figure Power Timing
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
RESETB Internal Reset Time
Reset Pulse Width Reset Time
Note: indicates minimum RESETB duration activate internal reset signal indicates reset completion time internal circuit from start internal reset signal (when fosc 40.0kHz).
Figure RESET Timing
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
INSTRUCTION INITIALIZING WITH RESET
8-bit Interface Mode (fosc 40.0kHz) VDD-VSS Power When Using RESETB input Initializing Wait until Power Stable Reset (RESETB "Low") Wait more than 1.2µs Release Reset (RESETB "High") Wait more than When just Using Internal Power Reset Circuit
Wait more than 20ms after rises
Command Input
Function
Entry Mode Display Control
Initialization
Address Data Write
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
4-bit Interface Mode (fosc 40.0kHz) VDD-VSS Power When Using RESETB Input Initializing Wait until Power Stable Reset (RESETB "Low") Wait more than 1.2µs Release Reset (RESETB "High") Wait more than When just Using Internal Power Reset Circuit
Wait more than 20ms after rises
Command Input
Function
Entry Mode
Display Control
Initialization
Address Data Write
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
DRIVING POWER SUPPLY CIRCUIT
Power Supply circuit produces panel driving voltage power consumption. driving Power Supply circuit consists external voltage input voltage follower.
KS0032
External Power Supply
Recommended Capacitance value 4.7µF Figure Driving Power Connection
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
INTERFACE
INTERFACING WITH 8080-SERIES MICROPROCESSORS
IORQ DECODER
KS0032
E_RD RW_WR RESETB RESETB
(8080-series) RESET
Figure Interfacing with 8080-series
INTERFACING WITH 6800-SERIES MICROPROCESSORS
RESET RESETB DECODER
KS0032
E_RD RW_WR RESETB
(6800 -series)
Figure Interfacing with 6800-series
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
APPLICATION INFORMATION PANEL
Chip Bottom Lower View (DIRC "0", DIRS "0")
SEG80 SEG79 SEG78 SEG77 SEG76 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM8 COM7 COM6 COM2 COM1
BOTTOM VIEW
COM16 COM15 COM11 COM10 COM9
Figure Chip Bottom Lower View Interfacing with Panel
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
Chip Bottom Upper View (DIRC "1", DIRS "1")
COM9 COM10 COM11 COM15 COM16
BOTTOM VIEW
SEG1 SEG2 SEG3 SEG4 SEG5 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
COM1 COM2 COM6 COM7 COM8
Figure Chip Bottom Upper View Interfacing with Panel
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Chip Lower View (DIRC "0", DIRS "1")
SEG1 SEG2 SEG3 SEG4 SEG5 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80
COM16 COM15 COM11 COM10 COM9
VIEW
COM8 COM7 COM6 COM2 COM1
Figure Chip Lower View Interfacing with Panel
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
Chip Upper View (DIRC "1", DIRS "0")
COM1 COM2 COM6 COM7 COM8
VIEW
SEG80 SEG79 SEG78 SEG77 SEG76 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
COM9 COM10 COM11 COM15 COM16
Figure Chip Upper View Interfacing with Panel
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
FRAME FREQUENCY
1-line Selection Period
COM1
FRAME FRAME
1-line Selection Period Clock Pulses Division Frame 25.0µs 12.8ms Clock 25.0µs fosc 40.0kHz) Frame Frequency 12.8ms 78Hz
Figure Frame Frequency
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
MAXIMUM ABSOLUTE RATE
Table Maximum Absolute Rate Characteristics Power supply voltage Power supply voltage Input voltage Operating temperature Storage temperature Symbol TOPR TSTG Value -0.3 +7.0 -0.3 -0.3 +0.3 +125 Unit
NOTE1: voltage levels based NOTE2: Voltage greater than above damage circuit. Voltage level: Voltage level:
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
Table Characteristics (VDD 2.4V 3.6V, Item Operating voltage Symbol IDD1 Condition Display operation without load access from Access operation from fcyc 200kHz 50µA 50µA VLCD Min. Typ. Max. 0.7VDD 40.0 Input leakage current resistance RSEG Frame frequency External clock frequency driving voltage VLCD ILEAK RCOM 0.3VDD Unit
Supply current (VDD
IDD2 Input voltage
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
Table Characteristics (Continued) (VDD 3.6V 5.5V, Item Operating voltage Symbol IDD1 Condition Display operation without load access from Access operation from fcyc 200kHz 50µA 50µA VLCD Min. Typ. Max. 0.7VDD 40.0 1000 Input leakage current resistance RSEG Frame frequency External clock frequency driving voltage VLCD ILEAK RCOM 0.3VDD Unit
Supply current (VDD
IDD2 Input voltage
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
CHARACTERISTICS
6800-series Interface Write Instruction Table Characteristics (6800-series Write Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time setup time hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time setup time hold time Symbol tSU1 tSU2 tSU1 tSU2 Min. Typ. Max. Unit
tSU1 RW_WR E_RD Figure Write Mode Timing (6800-series Interface) tSU2
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
8080-series Interface Write Instruction Table Characteristics (8080-series Write Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time setup time hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time setup time hold time Symbol tSU1 tSU2 tSU1 tSU2 Min. Typ. Max. Unit
tSU1 RW_WR Figure Write Mode Timing (8080-series Interface) tSU2
KS0032
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
6800-series Interface Read Instruction Table Characteristics (6800-series Read Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time output delay time output hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time output delay time output hold time Symbol tR,tF tR,tF Min. Typ. Max. Unit
RW_WR E_RD toDB7 Figure Read Mode Timing (6800-series Interface)
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
KS0032
8080-series Interface Read Instruction Table Characteristics (8080-series Read Instruction) Condition Characteristic cycle time Pulse rise fall time pulse width high 2.4V 3.6V, pulse width setup time hold time output delay time output hold time cycle time Pulse rise fall time pulse width high 3.6V 5.5V, pulse width setup time hold time output delay time output hold time Symbol tR,tF tR,tF Min. Typ. Max. Unit
E_RD
Figure Read Mode Timing (8080-series Interface)
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