Devices APEX Conversion September 2001, ver. Introduction

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Devices APEX Conversion September 2001, ver. Introduction

Datasheet Thumbnail

Top Searches for this datasheet

HardCopy
Devices APEX Conversion
September 2001, ver.
Introduction
HardCopydevices enable high-density APEX20K device technology used high-volume applications where significant cost reduction desired. HardCopy devices physically functionally compatible with APEX 20KE APEX 20KC devices. They combine time-tomarket advantage, performance, flexibility APEX devices with ability move high-volume, low-cost devices production. conversion process from APEX device HardCopy device fully automated, with customer involvement limited providing Quartus® software-generated output files.
Features.
Preliminary Information
HardCopy devices manufactured using 0.18-µm CMOS six-layer-metal fabrication process Preserves functionality configured APEX 20KE APEX 20KC device Pin-compatible with APEX 20KE APEX 20KC devices Meets exceeds timing configured APEX 20KE APEX 20KC devices Optional emulation original programmable logic device (PLD) programming sequence High-performance, low-power device MultiCorearchitecture integrating embedded memory look-up table (LUT) logic used register-intensive functions Embedded system blocks (ESBs) used implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, content-addressable memory (CAM) Customization performed through metallization layers High-density architecture 400,000 million typical gates (see Table 51,840 logic elements (LEs) 442,368 bits that used without reducing available logic
Altera Corporation
A-DS-HARDCOPY-1.0
HardCopy Devices APEX Conversion
Preliminary Information
Table HardCopy Device Features Feature
Maximum system gates Typical gates ESBs Maximum bits Phase-locked loops (PLLs) Maximum macrocells Maximum user pins Note Table
Note HC20K400
1,052,000 400,000 16,640 212,992 1,664
HC20K600
1,537,000 600,000 24,320 311,296 2,432
HC20K1000
1,772,000 1,000,000 38,400 327,680 2,560
HC20K1500
2,392,000 1,500,000 51,840 442,368 3,456
embedded IEEE Std. 1149.1 Joint Test Action Group (JTAG) boundary-scan circuitry contributes 57,000 additional gates.
.and more Features
Low-power operation 1.8-V supply voltage (see Table MultiVoltI/O support 1.8-V, 2.5-V, 3.3-V interfaces ESBs offering power-saving mode Flexible clock management circuitry with four phase-locked loops (PLLs) Built-in low-skew clock tree eight global clock signals ClockLockfeature reducing clock delay skew ClockBoostfeature providing clock multiplication division ClockShiftfeature providing clock phase delay shifting Powerful features Compliant with peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision 3.3-V operation bits Support high-speed external memories, including DDR, synchronous dynamic (SDRAM), static (SRAM) input output LVDS channels Fast times complex logic MultiVolt support 1.8-V, 2.5-V, 3.3-V interfaces Individual tri-state output enable control each Output slew-rate control reduce switching noise Support advanced standards, including LVDS, LVPECL, PCI-X, AGP, CTT, SSTL-3 SSTL-2, GTL+, HSTL Class Supports hot-socketing operation
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table HardCopy Device Supply Voltages Feature
Internal supply voltage (VCCINT) MultiVolt interface voltage levels (VCCIO) Note Table
HardCopy devices 5.0-V tolerant using external resistor.
Voltage
HardCopy device implementation features Customized interconnect each design HardCopy devices preserve APEX device MegaLABstructure, LEs, ESBs, IOE, PLLs, LVDS circuitry four metal layers customizable customer designs Completely automated proprietary design conversion flow Testability analysis Automatic test pattern generation (ATPG) Automatic place route Static timing analysis Static functional verification Physical verification
Tables through show HardCopy device ball-grid array (BGA) FineLine BGApackage options, counts, sizes. Table HardCopy Device Package Options Count Device
HC20K400 HC20K600 HC20K1000 HC20K1500
Note
652-Pin
Table HardCopy Device FineLine Package Options Count Note Device
HC20K400 HC20K600 HC20K1000 HC20K1500
672-Pin
1,020-Pin
Altera Corporation
HardCopy Devices APEX Conversion Data Sheet Note Tables
counts include dedicated input clock pins.
Preliminary Information
Table HardCopy Device Package Sizes Feature
Pitch (mm) Area (mm2) Length width
652-Pin
1.27 2,025 45.0 45.0
Table HardCopy Device FineLine Package Sizes Feature
Pitch (mm) Area (mm2) Length width
672-Pin
1.00
1,020-Pin
1.00 1,089
General Description
HardCopy devices extend flexibility high-density PLDs costeffective, high-volume production solution. conversion process from Altera® HardCopy device offers seamless migration highdensity system-on-a-programmable-chip (SOPC) design low-cost alternative device with minimal risk. Using HardCopy devices, Altera's SOPC solutions leveraged from prototype production, while reducing costs speeding time-to-market. significant benefit HardCopy devices that customers need involved device conversion process. Unlike applicationspecific integrated circuit (ASIC) development, HardCopy design flow does require generation test benches, test vectors, timing functional simulation. HardCopy conversion process only requires Quartus software-generated output files from fully functional APEX 20KE APEX 20KC device. Altera performs conversion delivers functional prototypes seven weeks. risk-free alternative ASICs, HardCopy devices customizable, fullfeatured devices created Altera's proprietary design conversion methodology. They based Altera's industry-leading high-density device architecture area-efficient sea-of-logic-elements (SOLE) core.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
HardCopy devices retain same features APEX 20KE APEX 20KC devices, which combine strength LUT-based product-term-based devices conjunction with same embedded memory structures. routing resources that were programmable APEX device family replaced custom interconnect, resulting considerable size reduction subsequent cost saving. SRAM configuration cells original replaced HardCopy devices metal elements, which define function each logic element (LE), embedded memory, cell device. These resources connected each other using same metallization layers. Once HardCopy device been manufactured, functionality device fixed programming possible. Altera performs conversion original design equivalent HardCopy device using proprietary design conversion flow. conversion HardCopy device begins with user design that been implemented APEX 20KE APEX 20KC device. Table shows device equivalence HardCopy APEX devices. Table HardCopy APEX Device Equivalence HardCopy Device
HC20K1500 HC20K1000 HC20K600 HC20K400
APEX 20KE Device
EP20K1500E EP20K1000E EP20K600E EP20K400E
APEX 20KC Device
EP20K1500C EP20K1000C EP20K600C EP20K400C
ensure HardCopy device performance functionality, APEX design must completely debugged before committing design HardCopy device conversion.
HardCopy device implementation begins with extracting Quartus software-generated SRAM Object File (.sof) converting connectivity information into structural Verilog netlist. This netlist then placed routed similar fashion gate array. There dedicated routing channels. router exploit available metal layers four) route over cells other functional blocks. Altera's proprietary architecture design methodology will guarantee virtually 100% routing APEX 20KE APEX 20KC design compiled fitted successfully using Quartus software. Place route timing-driven will comply with timing constraints original design specified Quartus software. Figure shows diagram HardCopy device architecture.
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Figure HardCopy Device Architecture
Elements Strip auxiliary gates (SOAG)
PLLs
strip auxiliary gates (SOAG) Altera proprietary feature designed into HardCopy device used during HardCopy implementation process. SOAG structures configured into several different types functions through metallization. example, high fanout signals require adequate buffering, buffers built SOAG cells this purpose. HardCopy devices include same advanced features APEX 20KE APEX 20KC devices, such enhanced standard support, content-addressable memory (CAM), additional global clocks, enhanced ClockLock circuitry. Table lists features included HardCopy devices.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table HardCopy Device Features Feature
MultiCore system integration Hot-socketing support 32-/64-bit, 33-MHz 32-/64-bit, 66-MHz MultiVolt Full support Full support Full compliance Full compliance 1.8-V, 2.5-V, 3.3-V VCCIO VCCIO selected bank bank 5.0-V tolerant with external resistor Clock delay reduction clock multiplication Drive ClockLock output off-chip External clock feedback ClockShift circuitry LVDS support four PLLs ClockShift, clock phase adjustment Eight 1.8-V, 2.5-V, 3.3-V, 5.0-V 3.3-V PCI-X 3.3-V GTL+ LVCMOS LVTTL True-LVDSand LVPECL data pins LVDS LVPECL clock pins HSTL Class PCI-X SSTL-2 Class SSTL-3 Class Dual-port FIFO
HardCopy Devices
ClockLock support
Dedicated clock input pins standard support
Memory support
HardCopy devices tested using ATPG vectors prior shipment. fully synchronous designs near 100%, fault coverage achieved through built-in full-scan architecture. ATPG vectors allow designer focus simulation design verification.
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Because configuration HardCopy devices built-in during manufacture, they cannot configured in-system. However, APEX 20KE APEC 20KC device configuration sequence must emulated, HardCopy device this capability.
device features APEX 20KE APEX 20KC devices available HardCopy devices. detailed description these device features, refer APEX Programmable Logic Device Family Data Sheet APEX 20KC Programmable Logic Device Family Data Sheet. Several differences must considered before design ready implementation HardCopy technology:
Differences Between HardCopy APEX Devices
HardCopy device only customizable time manufactured. Make sure that original APEX device undergone thorough testing end-system before deciding proceed with conversion HardCopy device because changes made HardCopy device after been manufactured. ESBs that configured will power-up uninitialized HardCopy device. possible configure, "pre-load," memory part configuration sequence, then overwrite when device normal functional mode. This pre-loaded memory feature available HardCopy devices. design contains with assumed data values power-up, then HardCopy device will operate expected. design uses this feature, then should recompiled without memory pre-load. ESBs configured fully supported. JTAG boundary scan order HardCopy device different compared APEX device. HardCopy BSDL file that describes re-ordered boundary scan chain should used. BSDL files HardCopy devices different from corresponding APEX 20KE APEX 20KC devices. Download correct HardCopy BSDL file from Altera's site http://www.altera.com.
advanced 0.18-µm aluminum metal process used support both APEX 20KE APEX 20KC devices. performance improvement achieved size reduction metal interconnect optimization more than offsets need copper this case. Altera guarantees that target HardCopy device will provide same better performance corresponding APEX 20KC device.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Configuration Options
three different configuration options available HardCopy device are: Instant Delay, Configuration Sequence Emulation. Each mode described below.
Instant mode, HardCopy device available shortly after device receives power. on-chip power-on-reset circuit will reset registers. CONF_DONE output will tri-stated once power-on reset (POR) elapsed. configuration device configuration input signals necessary. Delay mode, HardCopy device will perform similar fashion Instant mode, except that there will additional delay (nominal), during which time device will held reset stage. CONF_DONE output pulled during this time then tri-stated after have elapsed. configuration devices configuration input signals necessary this option. Configuration Sequence Emulation mode, HardCopy device undergoes emulation full configuration sequence configured external processor device. this mode, CONF_DONE signal tri-stated after correct number clock cycles. This mode useful where there some dependency configuration sequence (e.g., multi-device configuration processor initialization). this mode, device expects configuration control data input signals.
Speed Grades
Because HardCopy devices customized, speed grading performed. HardCopy devices will meet timing requirements original fastest speed grade. Generally, HardCopy device will have higher fMAX than corresponding PLD, speed increase will vary design-by-design basis.
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Quartus IIGenerated Output Files
HardCopy conversion process requires several Quartus softwaregenerated files. These output files listed briefly explained below.
SRAM Object File (.sof) contains necessary information needed configure Compiler Report File (.csf.rpt) parsed extract useful information about design Verilog atom-based netlist file (.vo) used check HardCopy netlist information file (.pin) contains user signal names configuration information Delay Information File (.sdo) used check original timing completed HardCopy timing requirements file describes necessary timing information design. template this text file available download from Altera site http://www.altera.com.
conversion process consists several steps. First, netlist constructed from SOF. Then, netlist checked ensure that built-in scan test structures will operate correctly. netlist then into place-and-route engine, design interconnect generated. Static timing analysis ensures that timing constraints met, static functional verification techniques employed ensure correct device conversion. After successfully completing these stages, physical verification device takes place, metal mask layers taped fabricate HardCopy device.
Conversion Flow
Design conversion HardCopy devices occurs several steps, which outlined this section shown Figure conversion uses both proprietary third-party tools.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Figure HardCopy Conversion Flow Diagram
.sof
Metal Polygons
Physical Switch Programming
Netlist Generator
Verilog Structural Netlist
Testability
Testability Violations
Testability Violations
Generate Test Vectors
ATPG Vectors
Test Vectors
Place Route
PostLayout Timing
Static Timing Analysis
Netlist
Timing Violations
Formal Verification
Netlist
Functionality
Changed
Netlist
Final Netlist
Physical Verification
Tapeout
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Netlist Generation
Using Altera proprietary conversion tool, converted into Verilog structural netlist. This netlist describes each structural element (IOE, ESB, PLL, LVDS circuitry) design configured each structural element connected other structural elements. information that describes structural element configuration converted into physical coordinate format that metal elements implemented pre-defined HardCopy base array.
Testability Audit
Once Verilog netlist available, audit performed testability violations. This audit ensures that built-in scan chain structures will work reliably during testing HardCopy devices. Certain circuit structures such gated clocks, gated resets, oscillators, shots, other type asynchronous circuit structures will make performance scan chain structures unreliable. Thus, during this testability audit such circuit structures detected disabled when device into test mode.
Placement
netlist read into place-and-route tool which then optimizes placement every that used design. optimization based netlist connectivity addition timing constraints design. placement IOEs fixed. After placement complete, scan chain ordering information generated that scan paths connected.
Test Vector Generation
test vectors ensure that memory bits function correctly. ATPG vectors test logic. These vectors ensure that high stuckat-fault coverage achieved. target fault coverage figure HardCopy devices least 95%. Once testability audit completed successfully scan chains have been re-ordered, ATPG test vectors generated. Once test vector generation complete, they simulated verify correct operation.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Routing
Routing commence parallel with test vector generation. Routing involves generating physical interconnect between every element design. this stage, physical design rule violations fixed. example, nodes with large fan-outs need buffered, otherwise transition time these signals will slow power consumption device will increase. SOAG structures used this purpose. other types physical design rule violations also fixed during this stage, such antenna violations.
Extracted Delay Calculation
Once routing complete, interconnect parasitic capacitance resistance information generated. This converted into Standard Delay Format File (.sdf) with delay calculation tool. Timing minimum delays generated addition maximum delays.
Static Timing Analysis Timing Closure
timing design checked corrected after place route using post-layout generated SDF. Setup time violations corrected ways. First, extra buffers, which created using SOAG resources, inserted speed slow signals. Second, buffer insertion does completely setup violation, placement re-optimized. Setup time violations rare HardCopy devices because size considerably smaller than equivalent APEX 20KE APEX 20KC device. Statistically, interconnect loading distance much smaller HardCopy devices, device will operate higher clock frequency. Hold-time violations fixed inserting delay elements into fast data paths. delay elements also built SOAG resources. Once timing violation corrections have been implemented netlist, placement routing updated reflect changes. This process iterated until timing violations removed. Typically only single iteration required after initial place route. Finally, static functional verification tested after this stage double-check netlist integrity.
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Formal Verification
After change netlist, integrity must verified through static functional verification formal verification) techniques involves showing that versions design functionally identical when certain constraints applied. example, netlist after test fixes must logically equivalent netlist before test fixes when test mode disabled. This technique does rely customer-supplied functional simulation vectors.
Physical Verification
Before manufacturing metal customization layers, physical programming information must verified. This stage involves crosschecking physical design rule violations layout database, also checking that circuit physically implemented correctly. These processes commonly known running design rule check (DRC) layout versus schematic (LVS) verification.
Manufacturing
Metallization masks created manufacture HardCopy devices. After manufacturing, parts tested using test vectors that were developed part implementation process.
Testing
HardCopy devices fully tested part manufacturing process. user-specific simulation vectors required this purpose, every HardCopy device utilizes full scan path technology. This means that every node inside chip both controllable observable through more package pins device. scan paths, "scan chains," exercised through ATPG. This ensures high-confidence level that manufacturing defects detected. Every register HardCopy device belongs scan chain. Scan chains test features that exist ASICs ensure that access internal nodes design possible. With scan chains, defective parts screened during manufacturing process. Scan chain registers constructed combining original register with 2-to-1 multiplexer. normal user mode, multiplexer transparent user. scan mode, registers device connected into long shift register that ATPG vectors scanned into device. Several independent scan chains exist HardCopy device. Figure shows diagram scan register.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Figure HardCopy Scan Chain Circuitry
scan_in
Register
regular_data_in scan_enable
scan_out
addition scan circuitry, which designed test IOEs, every contains dedicated test circuitry that bits inside memory array tested correct operation. Access memory also facilitated through scan chains. also offers test mode which reconfigured into block. this mode, data scanned into registers written into memory. ESBs configured product-term logic ROM, write enable signal will have effect memory array data. When test mode disabled (default), reverts desired user functionality. Figure shows test mode configuration.
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Figure Test Mode Configuration
scan_in Memory Array
data
waddr
scan_in
raddr
scan_out
scan_out scan_clock ESB_scan_enable ESB_test_enable
PLLs tested through built-in self test (BIST) circuitry test point additions. test circuitry disabled once device installed into user system that device then behaves expected normal functional mode.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
HardCopy devices provide JTAG circuitry that complies with IEEE Std. 1149.1-1990 specification. HardCopy devices support JTAG instructions shown Table BSDL files HardCopy devices different from corresponding APEX 20KE APEX 20KC parts. Download correct HardCopy BSDL file from Altera's site http://www.altera.com.
Table HardCopy JTAG Instructions JTAG Instruction
SAMPLE/PRELOAD
Description
SAMPLE/PRELOAD allows snapshot signals device pins captured examined during normal device operation permits initial data pattern output device pins. also used SignalTap embedded logic analyzer. Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins Places 1-bit bypass register between pins, which allows data pass synchronously through selected devices adjacent devices during normal device operation Selects 32-bit USERCODE register places between pins, allowing USERCODE serially shifted Selects IDCODE register places between pins, allowing IDCODE serially shifted
EXTEST BYPASS
USERCODE IDCODE
HardCopy device instruction register length bits; USERCODE register length bits. Tables show boundary-scan register length device IDCODE information HardCopy devices. Table HardCopy Boundary-Scan Register Length Device
HC20K400 HC20K600 HC20K1000 HC20K1500
Boundary-Scan Register Length
1,506 1,806 2,190 2,502
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table 32-Bit HardCopy Device IDCODE Device Version Bits)
HC20K400 HC20K600 HC20K1000 HC20K1500 Notes Table
most significant (MSB) left. IDCODE's least significant (LSB) always
IDCODE Bits) Part Number Bits)
1000 0100 0000 0000 1000 0110 0000 0000 1001 0000 0000 0000 1001 0101 0000 0000
Manufacturer Identity Bits)
0110 1110 0110 1110 0110 1110 0110 1110
Bit)
0000 0000 0000 0000
Figure shows timing requirements JTAG signals. Figure HardCopy JTAG Waveforms
tJPZX tJSSU Signal Captured Signal Driven tJSH JPCO JPXZ JPSU
tJSZX
tJSCO
tJSXZ
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table shows JTAG timing parameters values HardCopy devices. Table HardCopy JTAG Timing Parameters Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ clock period clock high time clock time JTAG port setup time JTAG port hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance Capture register setup time Capture register hold time Update register clock output Update register high impedance valid output Update register valid output high impedance
Parameter
Unit
more information using JTAG circuitry Altera devices, Application Note (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing Altera Devices).
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Operating Conditions
Tables through provide information absolute maximum ratings, recommended operating conditions, operating conditions, capacitance 1.8-V HardCopy devices. Note
-0.5 -0.5 -0.5 bias Under bias packages, under bias
Table HardCopy Device Absolute Maximum Ratings Symbol
CCINT CCIO input voltage output current, Storage temperature Ambient temperature Junction temperature
Parameter
Supply voltage
Conditions
With respect ground
Unit
Table HardCopy Device Recommended Operating Conditions Symbol
CCINT CCIO
Parameter
Supply voltage internal logic input buffers Supply voltage output buffers, 3.3-V operation Supply voltage output buffers, 2.5-V operation (3), (3), (3), (2),
Conditions
1.71 (1.71) 3.00 (3.00) 2.375 (2.375) -0.5
1.89 (1.89) 3.60 (3.60) 2.625 (2.625) CCIO
Unit
Input voltage Output voltage Junction temperature Input rise time (10% 90%) Input fall time (90% 10%)
commercial industrial
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table HardCopy Device Operating Conditions Symbol
Notes (6), (7),
1.7, VCCIO -0.5
Parameter
High-level LVTTL, CMOS, 3.3-V input voltage Low-level LVTTL, CMOS, 3.3-V input voltage 3.3-V high-level LVTTL output voltage 3.3-V high-level LVCMOS output voltage
Conditions
0.8, VCCIO
Unit
CCIO 3.00 -0.1 CCIO 3.00
CCIO VCCIO VCCIO
3.3-V high-level output voltage -0.5 CCIO 3.00 3.60 2.5-V high-level output voltage -0.1 CCIO 2.30 CCIO 2.30 CCIO 2.30 3.3-V low-level LVTTL output voltage 3.3-V low-level LVCMOS output voltage CCIO 3.00 (10) CCIO 3.00 (10)
3.3-V low-level output voltage CCIO 3.00 3.60 (10) 2.5-V low-level output voltage CCIO 2.30 (10) CCIO 2.30 (10) CCIO 2.30 (10)
Input leakage current (11) -0.5 Tri-stated leakage -0.5 current (11) supply current (standby) (All ESBs power-down mode) ground, load, toggling inputs, speed grade ground, load, toggling inputs, speed grades
CONF
Value pull-up resistor before during configuration emulation
CCIO (12) CCIO 2.375 (12) CCIO 1.71 (12)
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table HardCopy Device Capacitance Symbol
CINCLK COUT
Note (13) Conditions
Parameter
Input capacitance Input capacitance dedicated clock Output capacitance
Unit
VOUT
Notes Tables through
Operating Requirements Altera Devices Data Sheet. Minimum input -0.5 During transitions, inputs undershoot -0.5 overshoot input currents less than periods shorter than Numbers parentheses industrial-temperature-range devices. Maximum rise time must rise monotonically. pins (including dedicated inputs, clock, I/O, JTAG pins) driven before VCCINT VCCIO powered. Typical values CCINT CCIO These values specified under HardCopy device recommended operating conditions, shown Table page Refer Application Note (Using Selectable Standards Altera Devices) VIH, VIL, VOH, VOL, parameters when VCCIO APEX 20KE input buffers compatible with 1.8-V, 2.5-V 3.3-V (LVTTL LVCMOS) signals. Additionally, input buffers 3.3-V compliant. Input buffers also meet specifications GTL+, CTT, AGP, SSTL-2, SSTL-3, HSTL. parameter refers high-level TTL, PCI, CMOS output current. This value specified normal device operation. value vary during power-up. pull-up resistance values will lower external source drives higher than VCCIO. Capacitance sample-tested only.
(10) (11) (12) (13)
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Tables through list operating specifications supported standards. These tables list minimal specifications only; HardCopy devices exceed these specifications. Table LVTTL Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO VCCIO
Table LVCMOS Specifications Symbol
VCCIO
Parameter
Power supply voltage range High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
-0.3
Maximum
VCCIO
Units
VCCIO -0.1 VCCIO
VCCIO
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table 2.5-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 -0.3
Maximum
2.625 VCCIO
Units
-0.1
Table 1.8-V Specifications Symbol
VCCIO
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
0.65 VCCIO
Maximum
VCCIO 0.35 VCCIO
Units
VCCIO 0.45
0.45
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table 3.3-V Specifications Symbol
VCCIO
Parameter
supply voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
VCCIO -0.5
Typical
Maximum
VCCIO VCCIO
Units
VCCIO IOUT -500 IOUT 1,500
VCCIO
VCCIO
Table 3.3-V PCI-X Specifications Symbol
VCCIO VIPU LPIN
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage Input leakage current High-level output voltage Low-level output voltage Inductance
Conditions
Minimum
VCCIO -0.5 VCCIO
Typical
Maximum
VCCIO 0.35 VCCIO
Units
VCCIO IOUT -500 IOUT 1500
-10.0 VCCIO
10.0
VCCIO 15.0
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table 3.3-V LVDS Specifications Symbol
VCCIO
Parameter
supply voltage Differential output voltage Change between high Change between high Differential input threshold Receiver input voltage range Receiver differential input resistor (external APEX devices)
Conditions
Minimum
3.135
Typical
Maximum
3.465
Units
Output offset voltage
1.125
1.25
1.375
-100
Table GTL+ Specifications Symbol
VREF
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF
Typical
Maximum
1.65 1.12
Units
VREF 0.65
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18
Units
-7.6
0.57 0.57
Table SSTL-2 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF 0.04 1.15 VREF 0.18 -0.3
Typical
VREF 1.25
Maximum
2.625 VREF 0.04 1.35 VCCIO VREF 0.18
Units
-15.2 15.2
0.76 0.76
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Table SSTL-3 Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
VREF 0.05 VREF -0.3
Typical
VREF
Maximum
VREF 0.05 VCCIO VREF
Units
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table HSTL Class Specifications Symbol
VCCIO VREF
Parameter
supply voltage Termination voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.71 VREF 0.05 0.68 VREF -0.3
Typical
VREF 0.75
Maximum
1.89 VREF 0.05 0.90 VCCIO VREF
Units
VCCIO
Table LVPECL Specifications Symbol
VCCIO tDSKEW
Parameter
Output Supply Voltage Low-level input voltage High-level input voltage Low-level output voltage High-level output voltage Input voltage differential Output voltage differential Rise fall time 80%) Differential skew Output load Receiver differential input resistor
Minimum
3.135 1,300 2,100 1,450 2,275
Typical
Maximum
3.465 1,700 2,600 1,650 2,420
Units
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table 3.3-V Specifications Symbol
VCCIO VREF
Parameter
supply voltage Reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current
Conditions
Minimum
3.15 0.39 VCCIO VCCIO
Typical
Maximum
3.45 0.41 VCCIO VCCIO VCCIO
Units
IOUT -500 IOUT 1500 VCCIO
VCCIO
VCCIO
Table Specifications Symbol
VCCIO VTT/VREF
Parameter
supply voltage Termination reference voltage High-level input voltage Low-level input voltage Input leakage current High-level output voltage Low-level output voltage
Conditions
Minimum
1.35 VREF
Typical
Maximum
1.65
Units
VREF VCCIO VREF VREF
Output leakage VOUT VCCIO current (when output high
Notes Tables through
parameter refers high-level output current. parameter refers low-level output current. This parameter applies open-drain pins well output pins. VREF specifies center point switching range.
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Figure shows output drive characteristics HardCopy devices. Figure Output Drive Characteristics HardCopy Devices
Typical Output Current (mA) VCCINT VCCIO Room Temperature Typical Output Current (mA)
VCCINT VCCIO 2.5V Room Temperature
Output Voltage
Output Voltage
Typical Output Current (mA) VCCINT 1.8V VCCIO 1.8V Room Temperature
Output Voltage
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Figure shows timing model bidirectional timing. Figure Synchronous Bidirectional External Timing
Register Dedicated Clock
tXZBIDIR tZXBIDIR tOUTCOBIDIR
Bidirectional
CLRN
Output Register
CLRN
Register
tINSUBIDIR tINHBIDIR
Input Register
CLRN
Tables describe HardCopy device external timing parameters. Table HardCopy Device External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL
Note Conditions
Clock Parameter
Setup time with global clock register Hold time with global clock register Clock-to-output delay with global clock output register Setup time with clock input register Hold time with clock input register Clock-to-output delay with clock output register
Altera Corporation
Preliminary Information
HardCopy Devices APEX Conversion
Table HardCopy Device External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL
Note Condition
Parameter
Setup time bidirectional pins with global clock LAB-adjacent input register Hold time bidirectional pins with global clock LAB-adjacent input register Clock-to-output delay bidirectional pins with global clock register Synchronous output enable register output buffer disable delay Synchronous output enable register output buffer enable delay Setup time bidirectional pins with clock LAB-adjacent input register Hold time bidirectional pins with clock LAB-adjacent input register
Clock-to-output delay bidirectional pins with clock register Synchronous output enable register output buffer disable delay with Synchronous output enable register output buffer enable delay with
Note Tables
These timing parameters sample-tested only.
Tables show external timing parameters HC20K1500 devices. Table HC20K1500 External Timing Parameters Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL
Unit
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Table HC20K1500 External Bidirectional Timing Parameters Symbol
tINSUBIDIR tINHBIDIR tOUTCOBIDIR tXZBIDIR tZXBIDIR tINSUBIDIRPLL tINHBIDIRPLL tOUTCOBIDIRPLL tXZBIDIRPLL tZXBIDIRPLL Note Tables
Timing information preliminary. Final timing information will available future version this data sheet.
Unit
Altera Corporation
Preliminary Information
Hard Copy Devices APEX Conversion
Notes:
Altera Corporation
HardCopy Devices APEX Conversion
Preliminary Information
Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 544-7104 Literature Services: lit_req@altera.com
Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service markds Altera Corporation U.S. other countries. Altera acknowledges trademarks other organizations their respective products services mentioned this document. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 2001 Altera Corporation. rights reserved.
Printed Recycled Paper.
Altera Corporation

Devices APEX Conversion September 2001, ver. Introduction

Top Searches for this datasheet

Other recent searches