OBSOLETE HISTORICAL REFERENCE ONLY Complete Monolithic 12-Bit Con
|
|
|
Top Searches for this datasheet
SP574B/674B/1674B/774B 12-Bit Sampling Converters
OBSOLETE HISTORICAL REFERENCE ONLY
Complete Monolithic 12-Bit Converters
with Sample-Hold, Reference, Clock Tri- state Outputs Full Nyquist Sampling Sample Rates Choice Sampling Rates 40kHz, 66kHz, 100kHz 125kHz Power Dissipation 110mW 12-Bit Linearity Over Temperature Commercial, Industrial Military Temperature Ranges Next-Generation Replacement 574A, 674A, 1674A, 774A Devices
DESCRIPTION.
SP574B/674B/1674B/774B (SPx74B) Series complete 12-bit successive-approximation converters integrated single with tri-state output latches, internal reference, clock sample-hold. "B-Series" features true Nyquist sampling while maintaining compatibility with prior versions. They drop-in replacements older 574A/ 674A/1674A/774A type devices.
DB11 DB10 DGND
NIBBLE
NIBBLE THREE-STATE BUFFERS CONTROL
NIBBLE
12-BIT
COMP
12-BIT CAPACITANCE OFFSET/GAIN TRIM
CONTROL LOGIC
7.5K
7.5K 7.5K
VLOGIC
12/8
AGND
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
ABSOLUTE MAXIMUM RATINGS
Digital Common +16.5V VLOGIC Digital Common Analog Common Digital Common Control Inputs Digital Common -0.5V VLOGIC +0.5V (CE, 12/8, R/C) Analog Input Voltage Range ±30% Analog Inputs Analog Common ±16.5V (REF OFF, 10VIN) 20VIN Analog Common ±24V Indefinite short common Momentary short Power Dissipation 1000mW Lead Temperature, Soldering 300°C, 10Sec 45°C/W MTBF-25°C Ground Base 2.915 million hours MTBF-125°C Missile Launch 10.16 thousand hours
OBSOLETE HISTORICAL REFERENCE ONLY
CAUTION: (ElectroStatic Discharge) sensitive device. Permanent damage occur unconnected devices subject high energy electrostatic fields. Unused devices must stored conductive foam shunts. Personnel should properly grounded prior handling this device. protective foam should discharged destination socket before devices removed.
Inputs exceeding +30% -30% will cause erratic performance.
SPECIFICATIONS
(Typical 25°C with +15V, VLOGIC unless otherwise noted.)
PARAMETER MIN. TYP. MAX. UNIT RESOLUTION models Bits ANALOG INPUTS Input Ranges Bipolar Unipolar +10, Input Impedance SP574B/SP674B Volt Input 3.75 6.25 Volt Input SP1674B/SP774B Volt Input 1.875 3.125 Volt Input 7.45 12.42 Nyquist Frequency SP574B SP674B SP1674B SP774B 62.5 DIGITAL INPUTS Logic Inputs R/C, 12/8 Logic +2.4 +5.5 Logic -0.3 +0.8 Current ±0.1 Capacitance 12/8 Control Input Hardwire VLOGIC DIGITAL COMMON DIGITAL OUTPUTS Logic Outputs DB11-DB0, Logic +2.4 Logic +0.4 Leakage (High State) Capacitance Parallel Data Output Codes Unipolar Positive true binary Bipolar Positive true offset binary INTERNAL REFERENCE Output Voltage 10.00 ±0.1 Output Current
CONDITIONS
-0.3V +5.5V Input +5.5V Input
ISOURCE 500µA ISINK 1.6mA Data bits only
Note
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
SPECIFICATIONS (continued)
(Typical 25°C with +15V, VLOGIC unless otherwise noted.)
OBSOLETE HISTORICAL REFERENCE ONLY
PARAMETER CONVERSION TIME SP574B 12-Bit Conversion 8-Bit Conversion SP674B 12-Bit Conversion 8-Bit Conversion SP1674B 12-Bit Conversion 8-Bit Conversion SP774B 12-Bit Conversion 8-Bit Conversion ACCURACY Linearity Error Differential Linearity Error Offset Unipolar Bipolar Full Scale (Gain) Error STABILITY Unipolar Offset Bipolar Offset Gain (Scale Factor)
MIN.
TYP.
MAX.
UNIT
CONDITIONS
11.2
±1.0 ±0.5 ±0.3 ±0.6 ±0.3 ±0.45 ±0.15 ±0.5 ±0.22 ±0.4 ±0.12 ±0.8 ±0.5 ±0.6 ±0.25 ±2.5
Bits Bits Bits Bits
25°C TMIN TMAX 25°C TMIN TMAX Note 25°C TMIN TMAX 25°C TMIN TMAX Note
full scale; TMIN TMAX Note adjustment 25°C With adjustment 25°C adjustment 25°C With adjustment 25°C adjustment 25°C With adjustment 25°C adjustment 25°C With adjustment 25°C adjustment 25°C With adjustment 25°C adjustment 25°C With adjustment 25°C
ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C
TMIN TMAX TMIN TMAX TMIN TMAX TMIN TMAX TMIN TMAX TMIN TMAX TMIN TMAX
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
SPECIFICATIONS (continued)
(Typical 25°C with +15V, VLOGIC unless otherwise noted.)
OBSOLETE HISTORICAL REFERENCE ONLY
PARAMETER MIN. POWER REQUIREMENTS +4.5 VLOGIC ILOGIC SP574B SP674B SP1674B SP774B +11.4 SP574B SP674B SP1674B SP774B POWER DISSIPATION SP574B SP674B SP1674B SP774B ENVIRONMENTAL Operating Temperature Range Storage Temperature Range
TYP.
MAX. +5.5
UNIT
CONDITIONS
+16.5 12.5 12.5
+125 +150
Notes: Available external loads. External load should change during conversion. When supplying external load operating +12V supply, buffer amplifier must provided reference output. Minimum resolution which missing codes guaranteed. Externally adjustable zero. Calibration information. Fixed resistor between Specifications identical models unless otherwise noted.
TYPICAL DYNAMICS Measurement/Model SP574B Test Conditions: Sampling Rate Input Frequency (FIN SFDR SINAD 72.5
SP674B 72.5
SP1674B 72.5
SP774B 72.5
Unit
Note: Refer Figure typical Nyquist sampling rate.
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
ASSIGNMENTS.
FUNCTION VLOGIC 12/8 GND(AC) N/C* 10VIN FUNCTION DB11(MSB) DB10 DB0(LSB)
OBSOLETE HISTORICAL REFERENCE ONLY
CIRCUIT OPERATION. SPx74B complete monolithic capacitor DAC-based 12-bit analog-to-digital converters with integral voltage reference, comparator, successive-approximation register (SAR), sample-and-hold, clock, output buffers control circuitry. high level integration SPx74B Series means they require external components. When control section SPx74B initiates conversion command, clock enabled successive-approximation register reset zeros. Once conversion cycle begins, stopped restarted data available from output buffers. SAR, timed clock, sequences through conversion cycle returns end-of-convert flag control section ADC. clock then disabled control section, output status goes low, control section enabled allow data read external command. internal SPx74B 12-bit CDAC sequenced starting from beginning conversion cycle provide output voltage from CDAC that equal input signal voltage (which divided input voltage divider network). comparator determines whether addition each successively-weighted voltage causes CDAC output voltage summation greater less than input voltage; less, left more, turned off. After testing bits, contains binary code which accurately represents input signal within ±1/2 LSB. internal reference provides voltage reference CDAC with excellent stability over temperature time. reference trimmed 10.00 Volts supply external load addition that required drive reference input resistor (1mA) offset resistor (1mA) when operating with ±15V supplies. SPx74B used with ±12V supplies, external current must supplied over full temperature range, external buffer amplifier recommended. external load SPx74B reference must remain constant during conversion.
20VIN DIG. *This connected inside device tied -15V, ground, left floating.
FEATURES. SPx74B Series feature standard bipolar unipolar input ranges 20V. Input ranges controlled bipolar offset laser-trimmed specified linearity, gain offset accuracy. Power requirements +12V +15V with maximum dissipation 150mW specified voltages. Conversion times 8µs, 10µs, 15µs 25µs available, units with 50ppm/°C temperature coefficients flexible matching specific application requirements. SPx74B Series available nine product grades each conversion time. models specified over 70°C commercial temperature range; models specified over -40°C +85°C industrial temperature range; models specified over -55°C +125°C military temperature range. Package options include 28-pin CDIP, 28-pin plastic (both narrow wide), 28-pin PLCC 28-pin SOIC.
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
OBSOLETE HISTORICAL REFERENCE ONLY
SAMPLE-AND-HOLD FUNCTION Although there sample-and-hold circuit classical sense, sampling nature capacitive makes SPx74B appear have built-in sample-and-hold. sample-and- hold function CDAC architecture optimized provide full Nyquist sampling maximum sampling rate. Because function included circuitry, majority specifications included within specifications. Note that some system architectures external sample-and-hold. built-in function SPx74B will provide additional isolation. Once internal sample taken CDAC capacitance, input SPx74B disconnected from input. This prevents transients occurring during conversion from being inflicted upon attached buffer. other 574/ 674-type circuits will cause transient load current input which will upset buffer output error conversion itself. addition, isolation input after acquisition time SPx74B allows opportunity release HOLD external sample- and-hold start tracking next sample. This will increase system throughput with your existing components. When using external S/H, SPx74B acts other 574-type device because internal transparent. sample/hold function SPx74B inherent capacitor structure, timing characteristics determined internally generated clock. However, multiplexer operation, internal eliminate need external S/H. operation function internal SPx74B
controlled through normal control line (refer Figure When line makes negative transition, SPx74B starts timing sampling conversion. first clock cycles allocated signal acquisition input CDAC (this time defined tACQ). Following these cycles, input sample taken held. conversion follows this cycle with duration controlled internal clock cycle, which determined specific product model. Note that because sample taken relative transition, tACQ also traditional "aperture delay" this internal sample hold. Since tACQ measured clock cycles, duration will vary with internal clock frequency. Offset, gain linearity errors circuit, well effects droop rate, included overall specs SPx74B. USING SPX74B SERIES Typical Interface Circuit SPx74B complete converter that fully operational when powered issued Start Convert Signal. Only external components necessary. SPx74B Series have four standard input ranges: +10V, +20V, ±10V. Figure depicts typical interface circuit operating SPx74B unipolar input mode. Figure depicts typical interface circuit operating SPx74B bipolar input mode. Further information given following sections these connections, first considerations concerning board layout achieve best operation. each application this device, strict attention must given power supply decoupling, board layout reduce pickup between analog digital sections), grounding. Digital timing, calibration analog signal source must considered correct operation. achieve specified accuracy, double-sided printed circuit board with copper ground plane component side recommended. Keep analog signal traces away from digital lines. best board such that there analog section digital section with single point ground connection between through bead. this possible, analog
Copyright 2000 Sipex Corporation
t(ACQ) ACQUISITION TIME
WAIT CONVERT SIGNAL CDAC VOLTAGE VOLTS
CONVERSION
WAIT READ
ACQUISITION TIME APERTURE DELAY TIME 0.12 tCONVERT
Figure Sample-and-Hold Function
SP574B/674B/1674B/774B
12-Bit Sampling Converters
OUTPUT BITS 12-BITS OSCILLATOR 100K -15V +15V 100K ANALOG INPUTS 12-BITS SAMPLE/HOLD STROBE CDAC COMP 12-BIT VLOGIC 10µF DGND 0.1µF CONTROL LOGIC NIBBLE NIBBLE NIBBLE
12/8
OBSOLETE HISTORICAL REFERENCE ONLY
THREE-STATE BUFFERS CONTROL
VREF
OFFSET/GAIN TRIM NETWORK
VREF 10µF 0.1µF +15V AGND N.C.
Figure Unipolar Input Connections
signals between ground traces cross digital lines right angles only. Grounding Considerations ground path from analog digital ground should resistance possible accommodate ground currents present with this device. analog ground current approximately while digital ground analog digital common pins should tied together close package possible guarantee best performance. code-dependent currents flow through VLOGIC terminals through analog digital common pins. Power Supplies supply voltages SPx74B must kept quiet possible from noise pickup also regulated from transients drops. Because part 12-bit accuracy, voltage spikes supply lines cause several deviations output. Switching power supply noise problem. Careful filtering shielding should employed prevent noise from being picked converter.
SP574B/674B/1674B/774B
Capacitor bypass pairs needed from each supply respective ground filter noise counter problems caused variations supply current. 10µF tantalum 0.1µF ceramic type parallel between VLOGIC (pin digital common (pin15), (pin analog common (pin sufficient. generated internally grounded connected negative supply SPx74B being used upgrade already existing design. CALIBRATION CONNECTION PROCEDURES Unipolar calibration procedure consists adjusting converter's most negative output ideal value offset adjustment, then adjusting most positive output ideal value gain adjustment. Starting with offset adjustment referring Figure midpoint first increment should positioned origin output code this, input +1/2 +1.22mV range +2.44mV range should applied SPx74B. Adjust offset potentiometer code transition flickers between 0000 0000 0000 0000 0000 0001.
Copyright 2000 Sipex Corporation
12-Bit Sampling Converters
OBSOLETE HISTORICAL REFERENCE ONLY
gain adjustment should done positive full scale. ideal input corresponding last code change applied. This 11/2LSB below nominal full scale which +9.9963V range +19.9927V range. Adjust gain potentiometer flicker between codes 1111 1111 1110 1111 1111 1111. calibration necessary intended application, replace with metal film resistor remove network analog input range range. Bipolar gain offset errors listed specifications adjusted zero using potentiometers (See Figure adjustment needed, either both pots replaced metal film resistor. calibrate, connect analog input signal range ±10V range. First apply input voltage above negative full scale which -4.9988V range -9.9976V ±10V range. Adjust offset potentiometer flicker between output codes 0000 0000 0000 0000 0000 0001. Next, apply input voltage 11/2 below positive full scale which +4.9963V range
+9.9927V ±10V range. Adjust gain potentiometer flicker between codes 1111 1110 1111 1111 1111. Alternative potentiometer provides gain adjust ranges. some applications, full scale 10.24V (for 2.5mV) 20.48 (for 5.0mV) more convenient. these, replace metal film resistor. Then provide gain adjust 10.24 range, potentiometer series with 20.48V range, 1000 potentiometer series with CONTROLLING SPx74B SPx74B operated most microprocessor systems control input pins on-chip logic. also operated "stand-alone" mode enabled input pin. Full microprocessor control consists selecting 12-bit conversion cycle, initiating conversion, reading output data when ready. output read options choosing either 12-bits once 8-bits followed 4-bits left-justified format. five control inputs TTL/CMOS compatible include 12/8, these inputs controlling converter's operation
OUTPUT BITS
CONTROL LOGIC
12/8
NIBBLE
NIBBLE
NIBBLE
THREE-STATE BUFFERS CONTROL
12-BITS OSCILLATOR 12-BIT ANALOG INPUTS ±10V 12-BITS SAMPLE/HOLD STROBE CDAC COMP VLOGIC 10µF DGND 0.1µF
VREF OFFSET/GAIN TRIM NETWORK
VREF
10µF 0.1µF N.C. AGND
+15V
Figure Bipolar Input Connections
SP574B/674B/1674B/774B 12-Bit Sampling Converters Copyright 2000 Sipex Corporation
shown Table internal control logic shown simplified schematic Figure
OBSOLETE HISTORICAL REFERENCE ONLY
Conversion Start conversion initiated logic transition three inputs: R/C, shown Table last three reach correct state starts conversion, one, three dynamically controlled. nominal delay from each same three change state simultaneously. order assure that particular input controls start conversion, other should setup least 50ns earlier. Refer convert mode timing specifications. Convert Start timing diagram shown Figure output signal status flag goes high only when conversion progress. While high, output buffers remain high impedance state that data read. Also, when high, additional Start Convert will reset converter reinitiate conversion. Note, changes state after conversion begins, additional Start Convert command will latch state possibly cause wrong cycle length that conversion (8-versus 12-bits).
Conversion Length conversion start transition latches state shown Figure Table latched state determines conversion stops with 8-bits high) continues 12-bits low). bits read following 8-bit conversion, three LSB's will logic will logic "1". latched because also involved enabling output buffers explained elsewhere. other control inputs latched. Stand-Alone Operation simplest interface control line connected R/C. other controls must tied known states follows: 12/8 wired high, wired low. output data arrives words 12-bits each. limits duty cycle shown Figures duty cycle within including extremes shown specifications. general, data read when high unless also high, indicating conversion progress. Reading Output Data output data buffers remain high impedance state until following four conditions met: high, low, high low. data lines become active response these four conditions, output data according conditions control lines 12/8 timing diagram this process shown Figure When 12/8 high, data outputs become active simultaneously input ignored. 12/8 input usually tied high low; TTL/ CMOS compatible. When 12/8 low, output separated into 8-bit bytes shown below: BYTE BYTE2 xxxx xxxx xxxx 0000 This configuration makes easy connect 8-bit data shown Figure control connected least significant address order store output data into consecutive memory locations. When pulled low, MSB's enabled only. When high, MSB's disabled, bits through forced zero four LSB's enabled. byte format "left justified data" shown above considered have decimal point binary left byte
12/8
OPERATION None None Initiate 12-Bit Conversion Initiate 8-Bit Conversion
Initiate 12-Bit Conversion Initiate 8-Bit Conversion Initiate 12-Bit Conversion
Initiate 8-Bit Conversion Enable 12-Bit Output Enable MSB's Only Enable LSB's plus Trailing Zeroes
Table SPx74B Control Input Truth Table
SP574B/674B/1674B/774B 12-Bit Sampling Converters Copyright 2000 Sipex Corporation
OBSOLETE HISTORICAL REFERENCE ONLY
toggled without damage converter time. Break-before-make action guaranteed between data bytes. This assures that outputs which strapped together Figure will never enabled same time. Figure seen that read operation usually begins after conversion complete low. earlier access needed, read begin later than addition times before goes low.
"NYQUIST" SAMPLING Each SPx74B analog-to-digital converters been designed provide Nyquist sampling (highest input frequency sampling rate) data conversion with degradation performance. This shown Figure Note that Differential Linearity Integral Linearity min/max values well within limits K-version Converter. Also, Typical Nyquist rates shown Figure reflect values listed Typical Dynamics table.
NIBBLE ZERO OVERRIDE NIBBLE INPUT BUFFERS 12/8 EOC8 LATCH EOC12 READ CONTROL NIBBLE
DELAY
Figure SPx74B Control Logic
ADDRESS
12/8 DB11 (MSB)
DATA
SPx74B
(LSB)
Figure Interfacing SPx74B 8-Bit Interface
SP574B/674B/1674B/774B 12-Bit Sampling Converters Copyright 2000 Sipex Corporation
CONVERT MODE TIMING
OBSOLETE HISTORICAL REFERENCE ONLY
tSSC
tHEC
tSRC tHRC
tSAC tHAC tDSC
DB11-
HIGH IMPEDANCE
CHARACTERISTICS
Typical 25°C, +15V +10V, VLOGIC +5V, unless otherwise specified.
PARAMETER tDSC Delay from tHEC Pulse Width tSSC Setup tHSC during High tSRC Setup tHRC during High tSAC Setup tHAC Valid during High Conversion Time1,
MIN.
TYP.
MAX.
UNITS
CONDITIONS
specifications
NOTES: Parameters guaranteed design sample tested. Parameters 100% tested 25°C special orders. 100% tested. TMIN TMAX. Figure Convert Mode Timing
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
READ MODE TIMING
OBSOLETE HISTORICAL REFERENCE ONLY
tSSR tHSR tHRR tSRR
tSAR DB11-
HIGH IMPEDANCE DATA VALID
tHAR
CHARACTERISTICS
Typical 25°C, +15V +12V, VLOGIC +5V, unless otherwise specified.
PARAMETER Access Time From Data Valid After Low2 Output Float Delay2
MIN.
TYP.
MAX.
UNITS
CONDITIONS
tSSR Setup tSRR Setup tSAR Setup tHSR Valid After tHRR High After tHAR Valid After Delay After Data Valid
1000
NOTES: Parameters guaranteed design sample tested. Parameters 100% tested 25°C special orders. Figure Read Mode Timing
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
STAND-ALONE MODE TIMING CHARACTERISTICS
Typical 25°C, VCC= +15V +12V, VLOGIC +5V, =0V, unless otherwise specified.
OBSOLETE HISTORICAL REFERENCE ONLY
PARAMETER tHRL Pulse Width Delay from tHDR Data Valid After Delay After Data Valid
MIN.
MAX.
UNITS
CONDITIONS
1000
tHRH High Pulse Width tDDR Data Access Time
NOTES: Parameters guaranteed design sample tested. Parameters 100% tested 25°C special orders.
tHRL
tHDR DB11-DB0
DATA VALID DATA VALID
Figure Pulse Outputs Enabled After Conversion
tHRH tDDR
HIGH-Z
tHDR
HIGH-Z
DB11-DB0
DATA VALID
Figure High Pulse Outputs Enabled While High, Otherwise High Impedance
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
OBSOLETE HISTORICAL REFERENCE ONLY
Figure Typical Nyquist Sampling Rates
ORDERING INFORMATION
Model Monotonicity Linearity Gain Temperature Range Package Types 25µs Conversion Time SP574BJ Bits ±1.0 SP574BK Bits ±0.5 SP574BA Bits ±1.0 SP574BB Bits ±0.5 SP574BS Bits ±1.0 SP574BT Bits ±0.5 15µs Conversion Time SP674BJ Bits ±1.0 SP674BK Bits ±0.5 SP674BA Bits ±1.0 SP674BB Bits ±0.5 SP674BS Bits ±1.0 SP674BT Bits ±0.5 10µs Conversion Time SP1674BJ Bits ±1.0 SP1674BK Bits ±0.5 SP1674BA Bits ±1.0 SP1674BB Bits ±0.5 SP1674BS Bits ±1.0 SP1674BT Bits ±0.5 Conversion Time SP774BJ Bits ±1.0 SP774BK Bits ±0.5 SP774BA Bits ±1.0 SP774BB Bits ±0.5 SP774BS Bits ±1.0 SP774BT Bits ±0.5 50ppm/°C +70°C 25ppm/°C +70°C 50ppm/°C -40°C +85°C 25ppm/°C -40°C +85°C 50ppm/°C -55°C +125°C 25ppm/°C -55°C +125°C 50ppm/°C +70°C 25ppm/°C +70°C 50ppm/°C -40°C +85°C 25ppm/°C -40°C +85°C 50ppm/°C -55°C +125°C 25ppm/°C -55°C +125°C 50ppm/°C +70°C 25ppm/°C +70°C 50ppm/°C -40°C +85°C 25ppm/°C -40°C +85°C 50ppm/°C -55°C +125°C 25ppm/°C -55°C +125°C 50ppm/°C +70°C 25ppm/°C +70°C 50ppm/°C -40°C +85°C 25ppm/°C -40°C +85°C 50ppm/°C -55°C +125°C 25ppm/°C -55°C +125°C
28-pin, 0.3" wide plastic 28-pin, PLCC 28-pin, 0.3" SOIC 28-pin, 0.6" wide plastic 28-pin, 0.6" Ceramic (consult factory)
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
OBSOLETE HISTORICAL REFERENCE ONLY
Corporation
SIGNAL PROCESSING EXCELLENCE
Sipex Corporation Headquarters Sales Office Linnell Circle Billerica, 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office South Hillview Drive Milpitas, 95035 TEL: (408) 934-7500 FAX: (408) 935-7600
Sipex Corporation reserves right make changes products described herein. Sipex does assume liability arising application product circuit described hereing; neither does convey license under patent rights rights others.
SP574B/674B/1674B/774B
12-Bit Sampling Converters
Copyright 2000 Sipex Corporation
Other recent searches
SN74SSTU32864C - SN74SSTU32864C SN74SSTU32864C Datasheet
SM5659-37 - SM5659-37 SM5659-37 Datasheet
SB120A - SB120A SB120A Datasheet
SB160A - SB160A SB160A Datasheet
DS90LV047A - DS90LV047A DS90LV047A Datasheet
CFAG14432D-TTI-TT - CFAG14432D-TTI-TT CFAG14432D-TTI-TT Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
