APEX 20KE Devices Application Note 2002, ver. Introduct

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APEX 20KE Devices Application Note 2002, ver. Introduct

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Using LVDS
APEX 20KE Devices
Application Note
2002, ver.
Introduction
Because complex designs continually demand more bandwidth, designers need high-performance solution that offers fast data transfer power consumption. address this need, Altera incorporated LVDS technology into APEX20KE devices. LVDS low-voltage swing, general-purpose standard that high-speed, low-power, low-noise advantages. Capable extremely high data transmission rates across variety interconnect media, such printed circuit board (PCB) traces, backplanes, cables, LVDS meets today's complex design requirements high data rates power consumption because low-voltage differential signal that transmit data rates megabits second (Mbps). With LVDS APEX 20KE devices, chip interface with high-speed, lowvoltage backplanes, data channels. This application note explains LVDS standard describes benefit from LVDS-integrated APEX 20KE devices.
LVDS Standards
industry standards define LVDS: IEEE Std. 1596.3 SCI-LVDS ANSI/TIA/EIA-644. Although both standards have similar features, IEEE Std. 1596.3 SCI-LVDS standard supports maximum data transfer rate only Mbps. APEX 20KE devices designed meet ANSI/TIA/EIA-644 standard while supporting maximum data transfer rate Mbps. ANSI/TIA/EIA-644 standard defines driver output receiver input characteristics. Figure shows current-mode LVDS driver works.
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120: Using LVDS APEX 20KE Devices
Figure LVDS Current-Mode Driver
Current Source (~3.5
Driver
Receiver
~350
LVDS Differential Transmission
LVDS standard utilizes low-voltage differential data transmission scheme without requiring input reference voltage. Differential transmission means that every LVDS signal uses lines. voltage difference between lines defines logic state LVDS signal. each signal pair, there true signal complementary signal. differential signal difference between true signal complementary signal (i.e., LVDSRX01p minus LVDSRX01n). differential transmission scheme several advantages over single-ended schemes:
Increased performance Reduced power consumption Minimized electromagnetic interference (EMI) generation
Increased Performance
Low-voltage swing important high performance; smaller voltage swing, faster signal change logic levels. faster transition time (i.e., edge rate), higher potential data rate. provide switching speeds hundreds-of-Mbps range, LVDS standard defines typical low-voltage signal swing signals referenced each other, another static signal level. Therefore, differential standard much smaller switching region. example, same bandwidth low-voltage CMOS (LVCMOS) data achieved with LVDS using one-fourth many pins operating LVDS signals eight times data rate. Figure shows 128-bit LVCMOS data that implemented with LVDS channels pins).
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120: Using LVDS APEX 20KE Devices
Figure LVCMOS LVDS Performance
With LVCMOS (256 Pins)
Microprocessor
128-Bit
APEX 20KE Device
128-Bit
13-Gbps Switch
Memory
With LVDS Pins, Channels)
Microprocessor
LVDS Channels Mbps
APEX 20KE Device
LVDS Channels Mbps
13-Gbps Switch
Memory
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120: Using LVDS APEX 20KE Devices
Power Efficiency
LVDS power-efficient standard. Because LVDS switching voltage (typically mV), power dissipation signal small. Furthermore, current typically channel. Table shows equations that calculate load power dissipation. Table Calculating LVDS Power Dissipation Calculation
power channel (PDC) power channel (PAC) Total power Note:
voltage level because CCIO APEX LVDS driver driven 3.3-V supply.
Equation
2CV2F
Example
11.55 (0.35 1.219 11.55 1.219 12.77
understand LVDS power consumption compares LVTTL, consider following example which both LVDS LVCMOS operating 622.08-Mbps bandwidth. comparison shown Table Table LVDS Power Consumption Compared LVCMOS Power Consumption Parameter
Number pins/channels Frequency Total bandwidth Data voltage swing Power Total power Note:
LVDS
channel 622.08 622.08 0.35 12.77
LVCMOS
pins 77.76 622.08 3.39 27.090
Unit
Mbps
channel operating mode equivalent terms data rate) LVCMOS pins.
Reduced Electromagnetic Interference (EMI)
Using LVDS standard also provides important advantage reduced electromagnetic interference (EMI). radiated noise created from acceleration electric charge within device across transmission medium between devices. Device-generated dependent frequency, output voltage swing, slew rate. low-voltage swing LVDS standard, effects much smaller than CMOS, TTL, other standards.
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Furthermore, LVDS less susceptible common-mode noise because LVDS differential standard. Figure shows that system power supply noise equally coupled both LVDS signals, thus does affect signal quality. Figure System-Level Noise Rejection
Common-mode noise from power supply rejected.
Common-Mode Noise Range
LVDS receiver tolerate maximum ±1-V ground shift between driver receiver ground. recommended input voltage range from Because typical voltage offset common mode range receiver LVDS driver output voltage swing between with respect ground. When there +1-V ground shift, voltage swing ranges from which within input voltage range. Similarly, there -1.0-V shift, output voltage swing ranges from Figure shows ground shift tolerance. Figure Common-Mode Voltage Range
Driver Output Receiver Input
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Deskew Circuitry
APEX 20KE devices incorporate optional deskew circuitry, which used ensure successful data capture high data rates. deskew circuitry used achieve high performance even with substantial board skew. deskew circuitry used increase RSKM parameter seen section "LVDS Timing" page deskew circuitry implemented inside APEX 20KE device compensate board skew data channels, shown Figure Figure Channel-to-Channel Clock-to-Channel Skew
Receiver Cannot Capture Data Data Stream Skewed from Others
Channel
Channel
Clock Channel
Channel Skew
APEX 20KE devices deskew circuitry provide high data transfer rates even with large channel skew board. over-sampling circuit used receiver accurately capture data. data inputs captured four phases same clocks, results examined determine which clock successfully captured data. deskew circuitry compensate skew much ±25% time unit interval (TUI). calibration pattern required phase-align clock with incoming LVDS data. calibration data values depend operating mode LVDS PLL. Like user mode data, first calibration data third after rising edge input clock. calibration data shown Table
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120: Using LVDS APEX 20KE Devices
Table Calibration Data Pattern Deskew Circuitry LVDS Operating Mode
Calibration Pattern
1100 0011100 00111100
Driving dual-function DESKEW high places LVDS inputs calibration mode. calibration pattern must applied minimum three input clock cycles (see Figure device sending deskew pattern, deskew should synchronous falling edge input clock ensure that setup time hold times met. channels calibrated simultaneously. Each LVDS input channel independently align clock with received data account differences channel skew. After channels have been successfully calibrated, LVDS data pins ready transmit receive data. Figure Deskew Circuitry Calibration Waveform Mode
least cycles
DESKEW Input Clock
Input Calibration Data
Byte Boundaries
First valid data (MSB) during user mode
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120: Using LVDS APEX 20KE Devices
Changes temperature voltage affect receiver input skew margin (RSKM). RSKM tolerance difference between input clock input data. deskew circuitry needs re-calibrated often enough ensure skew system never exceeds RSKM. analysis circuit must performed determine RSKM specification violated.
Data Orientation
relationship exists between external clock incoming data. operation Mbps mode, external clock multiplied phase-aligned coincide with sampling window each data bit. Figure shows data orientation data conversion mode, defined QuartusII software's altlvds_rx megafunction. Figure Data Orientation
External Input Slow Clock
LVDS Data Byte
Input Data
Internal Multiplied Clock
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LVDS Timing
This section discusses timing budget, waveforms, specifications LVDS APEX 20KE devices. LVDS allows data transmitted very high speeds. This high data transmission rate results better overall system performance. take advantage fast system performance, designers need understand analyze timing LVDS. LVDS timing analysis different from traditional synchronous timing analysis techniques. Rather than focusing clock-to-output setup times, LVDS timing analysis based skew between data clock signals. High-speed LVDS data transmission requires designers LVDS timing parameters provided Altera other LVDS vendors. Designers must consider board skew, cable skew, clock jitter. This section defines LVDS timing parameters APEX 20KE devices, explains LVDS timing parameters determine design's maximum performance.
Timing Budget
internally generated clock positioned meet requirements timing budget. Figure shows timing diagram that includes relationships between LVDS timing parameters positions. Figure also shows waveforms defining timing specifications high-speed LVDS operation.
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120: Using LVDS APEX 20KE Devices
Figure LVDS Timing Diagram Timing Budget
Timing Diagram
External Input Clock
Time Unit Interval (TUI)
Internal Clock TCCS RSKM Sampling Window (SW) RSKM TCCS
Receiver Input Data
TPPos (min) (min) TPPos (max)
Internal Clock Falling Edge
(max)
TPPos (min)
TPPos (max)
Timing Budget
External Clock
Clock Placement Internal Clock Synchronization
Transmitter Output Data
TCCS RSKM
RSKM
TCCS/2
Receiver Input Data
SW(min)
SW(max)
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Sampling Window
sampling window (SW) period time that input data must stable ensure that successfully sampled LVDS receiver (Rx). receiver requires data stable period time before sampled (setup time) must held period time after sampling (hold time). also defined worstcase setup hold times that take into account worst-case variation clock strobe placement.
Channel-to-Channel Skew
channel-to-channel skew (TCCS) difference between fastest slowest data output transitions, which includes clock-to-output (tCO) variation clock skew transmitter. Skew variation arrival time signals that specified arrive same time. Figure shows diagram TCCS. Figure Channel-to-Channel Skew (TCCS)
LVDS Transmitter Interface
LVDSTX01p
Data[127.0]
Built Parallel-to-Serial Converters LVDSTX16p
TCCS
(8x) (1x) LVDSTXOUTCLK1
Receiver Input Skew Margin
RSKM defined total margin left after accounting sampling window TCCS. RSKM equation shown below: RSKM (TUI TCCS)
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RSKM parameter large enough allow clock jitter, cable board skew, provide extra margin your design. meet system's requirements, designers must consider that jitter system skew exceed RSKM. This equation application's margin shown below: Margin RSKM (input clock jitter system skew) System skew difference propagation delays signals between devices includes skew introduced from cables, connectors, differences signal lengths traces. input clock jitter jitter transmit clock that will received APEX 20KE LVDS PLL.
LVDS Interconnect
System skew made cable skew, connector skew, trace skew. wide variety cables connectors LVDS interconnect available. Cable skew determined cable type, cable length, cable quality normally specified picoseconds unit length. longer cable greater skew. Connector skew normally much less than cable skew. "Zero skew" connectors consist single pins that minimize skew. traces should routed with equal length minimize skew. more information routing LVDS traces, Board Design Guidelines LVDS Systems White Paper. much possible, designers should maintain equal distance between traces LVDS pair. Routing pair traces close together will maximize common-mode rejection ratio (CMRR).
Design Example
This section describes LVDS design example using APEX 20KE-to-APEX 20KE connection data transfer rate Mbps over cable. This design uses Corporation cable (14526-EZ5B) connector (10226-1A10VE). Figure shows design example APEX 20KE-to-APEX 20KE (specifically EP20K400E-1X EP20K600E-1X devices) connection with cable assembly. timing parameters used this example described Table
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120: Using LVDS APEX 20KE Devices
Figure LVDS Design Example
APEX 20KE Device
APEX 20KE Device
design Figure following characteristics: 0.44 TCCS RSKM (TUI TCCS) (1.6 0.44 0.4) Cable skew meter (max) Connector skew (max) (Values obtained from Corporation) Since LVDS balls located outer edge FineLine BGApackages, traces easily routed with skew. skew (based electrical length traces) System skew Cable skew Connector skew skew ps/m Margin RSKM (input clock jitter system skew) Because there positive margin, circuit will operate required speed. longer cable desired, there sufficient margin. this case, APEX 20KE deskew circuit used increase RSKM assure circuit functionality. When designing high-speed data transfer rates, designers must consider various factors that affect margin correct data sampling. completing calculations described this section, designers calculate margin LVDS designs that APEX 20KE devices calculate LVDS transfer speed over cables connectors. Low-skew cables connectors also improve margin overall system performance. APEX 20KE LVDS circuit provides TCCS parameters that allow high-speed LVDS data transfers.
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Table shows LVDS timing specifications terminology. Table LVDS Timing Specifications Terminology LVDS Timing Specification
fLVDSCLK tLHT tHLT
Terminology
LVDS receiver/transmitter input output clock period. LVDS receiver/transmitter input output clock frequency. Low-to-high transmission time. High-to-low transmission time. timing budget allowed skew, propagation delays, data sampling window. (TUI 1/(Receiver Input Clock Frequency Multiplication Factor) tC/w). Maximum LVDS data transfer rate (fLVDSDR 1/TUI). TCCS timing difference between fastest slowest output edges, including variation clock skew. clock included TCCS measurement. RSKM timing margin between clock input data input user board design, which allows LVDS cable skew jitter LVDS PLL. RSKM (TUI TCCS SW)/2. This parameter defines period time during which data must valid order correctly captured. setup hold times determine ideal strobe position within sampling window. (max) (min). Peak-to-peak input jitter LVDS PLLs. output jitter LVDS PLLs. Duty cycle LVDS transmitter output clock. Lock time LVDS transmitter receiver PLLs.
fLVDSDR Channel-to-channel skew (TCCS)
Receiver input skew margin (RSKM)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (RMS) tDUTY tLOCK
LVDS Timing Specifications
Tables show LVDS timing specifications described Figure Table Table LVDS Multiplication Rate Symbol
(LVDS mode)
Description
Width parallel data multiplication factor
Value
Unit
Integer Integer Integer
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Table EP20K400E EP20K600E LVDS Timing Requirement (Part Symbol Conditions Commercial Speed Grade
mode mode mode fLVDSCLK mode mode mode tLHT tHLT mode mode mode fLVDSDR mode (fLVDSDR 1/TUI) mode (fLVDSDR 1/TUI) mode (fLVDSDR 1/TUI) TCCS RSKM mode deskew maximum fLVDSDR) mode deskew maximum fLVDSDR) mode deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) 9.52 9.52 5.71
Commercial Speed Grade
11.43 11.43 6.88
Industrial Speed Grade
12.80 11.43 6.88 4.167 4.762 612.5
Unit
87.5 87.5 145.25
78.125 87.5 145.25 Mbps Mbps Mbps
1.190 tC/w 1.361 tC/w 1.429 tC/w w/tC w/tC w/tC
4.167 1.429 tC/w 4.762 1.633 tC/w 1.721 tC/w w/tC w/tC w/tC
4.167 1.600 tC/w 4.762 1.633 tC/w 612.5 1.721 tC/w w/tC w/tC w/tC
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Table EP20K400E EP20K600E LVDS Timing Requirement (Part Symbol Conditions Commercial Speed Grade
fLVDSDR Mbps fLVDSDR Mbps Input jitter (peak-topeak) Output jitter (RMS) tDUTY tLOCK 0.25% 0.25% 0.25%
Commercial Speed Grade
Industrial Speed Grade
Unit
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Table EP20K1000E EP20K1500E LVDS Timing Requirement (Part Symbol Conditions Commercial Speed Grade
mode mode mode fLVDSCLK mode mode mode tLHT tHLT mode mode mode fLVDSDR mode (fLVDSDR 1/TUI) mode (fLVDSDR 1/TUI) mode (fLVDSDR 1/TUI) TCCS RSKM mode deskew maximum fLVDSDR) mode deskew maximum fLVDSDR) mode deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) mode (with deskew maximum fLVDSDR) 10.67 9.52 5.71
Commercial Speed Grade
12.80 11.43 6.88
Industrial Speed Grade
12.80 11.43 6.88 4.167 4.762 612.5
Unit
93.75
78.125 87.5 145.25
78.125 87.5 145.25 Mbps Mbps Mbps
1.333 tC/w 1.361 tC/w 1.429 tC/w w/tC w/tC w/tC
4.167 1.600 tC/w 4.762 1.633 tC/w 1.721 tC/w w/tC w/tC w/tC
4.167 1.600 tC/w 4.762 1.633 tC/w 612.5 1.721 tC/w w/tC w/tC w/tC
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Table EP20K1000E EP20K1500E LVDS Timing Requirement (Part Symbol Conditions Commercial Speed Grade
Input jitter (peak-topeak) Output jitter (RMS) tDUTY tLOCK fLVDSDR Mbps 0.25%
Commercial Speed Grade
0.25%
Industrial Speed Grade
0.25%
Unit
Receiver Transmitter Data Valid Windows
internally generated LVDS PLLs properly phase-aligned serial-to-parallel converter data capture, data sampling window must properly positioned with respect clock. location sampling window data transmit windows defined this section. They compatible with source-synchronous LVDS buffers offered National Semiconductor Texas Instruments. input timing waveform shown Figure compatible with National Semiconductor Corporation (NSC) Texas Instruments, Inc. (TI) source synchronous LVDS devices, there 2-bit cycle phase delay from input clock input data.
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Figure Input Timing Waveform
Input Clock (Differential Signal) Previous Cycle Input Data (Single-ended Signal)
Note
Current Cycle
Next Cycle
tsw0 (min) tsw0 (max) tsw1 (min) tsw1 (max) tsw2 (min) tsw2 (max) tsw3 (min) tsw3 (max) tsw4 (min) tsw4 (max) tsw5 (min) tsw5 (max) tsw6 (min) tsw6 (max) tsw7 (min) tsw7 (max)
Note:
timing specifications referenced differential voltage.
output timing waveform Figure shows relationship between output LVDS clock serial output data stream.
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Figure Output Timing Waveform
Output Clock (Differential Signal) Previous Cycle Output Data (Single-ended Signal) TPPos0 (min) TPPos0 (max) TPPos1 (min) TPPos1 (max) TPPos2 (min) TPPos2 (max) TPPos3 (min) TPPos3 (max) TPPos4 (min) TPPos4 (max) TPPos5 (min) TPPos5 (max) TPPos6 (min) TPPos6 (max) TPPos7 (min) TPPos7 (max) Current Cycle
Next Cycle
Note:
timing specifications referenced differential voltage.
Tables through define positions receiver transmitter data valid windows maximum data rates LVDS modes shown Figures 12). Tables define sampling window each with respect receiver input clock. Tables define switching time between transmitted data bits with respect transmitter output clock. transmitter, data valid transmitter data pins from TPPos[n] (maximum) TPPos[n+1] (minimum).
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There Automated LVDS Positions Calculator Altera site (http://www.altera.com), which will calculate positions based your specific design settings.
Table LVDS Receiver Sampling Window Positions Mode (840-Mbps Transfer) Symbol
tSW0 tSW1 tSW2 tSW3 tSW4 tSW5 tSW6 tSW7
Parameter
Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position
Minimum
0.38 1.57 2.76 3.95 5.14 6.33 7.52 8.71
Typical
0.60 1.79 2.98 4.17 5.36 6.55 7.74 8.93
Maximum
0.82 2.01 3.20 4.39 5.58 6.77 7.96 9.15
Unit
Table LVDS Transmitter Switching Characteristics Mode (840-Mbps Transfer) Symbol
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos7
Parameter
Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position
Minimum
-0.20 0.99 2.18 3.37 4.56 5.75 6.94 8.13
Typical
0.00 1.19 2.38 3.57 4.76 5.95 7.14 8.33
Maximum
0.20 1.39 2.58 3.77 4.96 6.15 7.34 8.53
Unit
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Table LVDS Receiver Sampling Window Positions Mode (735-Mbps Transfer) Symbol
tSW0 tSW1 tSW2 tSW3 tSW4 tSW5 tSW6
Parameter
Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position Sampling window position
Minimum
0.39 1.75 3.11 4.47 5.83 7.19 8.55
Typical
0.68 2.04 3.40 4.76 6.12 7.48 8.84
Maximum
0.97 2.33 3.69 5.05 6.41 7.77 9.13
Unit
Table LVDS Transmitter Switching Characteristics Mode (735-Mbps Transfer) Symbol
TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6
Parameter
Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position
Minimum
-0.20 1.16 2.52 3.88 5.24 6.60 7.96
Typical
0.00 1.36 2.72 4.08 5.44 6.80 8.16
Maximum
0.20 1.56 2.92 4.28 5.64 7.00 8.36
Unit
Table LVDS Receiver Sampling Window Positions Mode (700-Mbps Transfer) Symbol
tSW0 tSW1 tSW2 tSW3
Parameter
Sampling window position Sampling window position Sampling window position Sampling window position
Minimum
0.42 1.85 3.28 4.71
Typical
0.71 2.14 3.57 5.00
Maximum
1.00 2.43 3.86 5.29
Unit
Table LVDS Transmitter Switching Characteristics Mode (700-Mbps Transfer) Symbol
TPPos0 TPPos1 TPPos2 TPPos3
Parameter
Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position Transmitter output pulse position
Minimum
-0.20 1.23 2.66 4.08
Typical
0.00 1.43 2.86 4.28
Maximum
0.20 1.63 3.06 4.48
Unit
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LVDS Electrical Specifications
Table shows recommended operating conditions LVDS block.
Table 3.3-V LVDS Specifications Symbol
VCCINT VCCIO Note:
Devices that have suffix their ordering codes have maximum
Parameter
Supply voltage internal logic input buffers Supply voltage Differential output voltage Change between Output offset voltage Change between Differential input threshold Receiver differential input resistor
Conditions
1.71 3.15
1.80 3.30
1.89 3.45
Units
1.125 -100 1.250
1.375
Data Conversion Modes
successful transmission high data rates supported LVDS. minimizes skew phase-aligns clock parallel-to-serial serial-to-parallel data converters. EP20K400E larger devices, ClockLockPLLs configured LVDS interfaces. LVDS used input block, another used output block. Figure shows block diagram APEX 20KE LVDS PLLs, including LVDS-specific names.
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Figure LVDS Block Diagram
Dedicated Clocks LVDSTXOUTCLK1p
LVDSTXINCLK1p CLK4p
tx_inclock inclock
tx_outclock
clock1 clock0
rx_outclock rx_inclock
clock1 clock0 PLL3 inclock
LVDSRXINCLK1p CLK3p
PLL4
clock1 inclock CLK2p fbin CLKLK_FB2p CLKLK_OUT2p PLL2 clock0
clock1 PLL1 clock0 inclock CLK1p fbin CLKLK_FB1p
CLKLK_OUT1p
Notes:
These ports only used LVDS mode. PLL3 PLL4 used either LVDS general-purpose PLL.
When using LVDS, clocks multiplied support high-speed data transfer rates convert between LVDS CMOS data. multiply input clock dedicated data conversion circuitry. general-purpose recommended LVDS bypass mode. Figure shows connections LVDS receiver side. Figure LVDS Block Diagram
Allows conversion 8-bit parallel CMOS Data
LVDS Clock
LVDS
Dedicated Silicon Serial-to-Parallel Converter
Dedicated Clock
LVDS used boost LVDS input clock internally clocking LVDS data. also phase-aligns clock with incoming data.
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incoming serial LVDS channels either bypass serial-toparallel converter. parallel converter operate different dataconversion modes (e.g., LVDS operating modes). When operating mode, dedicated LVDS circuitry bypassed, data directly feeds logic elements (LEs). generated clock from LVDS receiver (PLL3) also used clock internal logic within device. Figure shows block diagram LVDS receiver circuitry. Figure Dedicated LVDS Receiver Circuitry Block Diagram
APEX 20KE LVDS Interface
Serial Data Mbps
data[7.0] Mbps Built-In Serial-to-Parallel Converter
LVDSRXINCLK Clock
PLL3
Dedicated Clock
Figure shows block diagram LVDS transmitter circuitry. transmitter (PLL4) driven externally output receiver (PLL3) internal global line, dedicated clock pins However, output general-purpose PLLs cannot drive transmitter (PLL4). output transmitter driven off-chip clock other LVDS devices system.
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Figure Dedicated LVDS Transmitter Circuitry Block Diagram
APEX LVDS Interface data[7.0] Mbps Built-In Parallel-to-Serial Converter
Serial Data Mbps
PLL4
LVDSTXOUTCLK
Internal Global Clocks (G1,
more information ClockLock ClockBoostcircuitry, refer Application Note (Using ClockLock ClockBoost Features APEX Devices). Figure shows LVDS receiver transmitter internally interface with logic other devices system. There input LVDS channels input block, with LVDS used clock serial-to-parallel converter receiver. PLLs (PLL3 receiver PLL4 transmitter) generate phase-locked clock signals serial-to-parallel parallel-to-serial data converters. receiver input channels, transmitter output LVDS channels. LVDS receiver converts maximum LVDS signals into parallel data bits, which feeds internal within device. Similarly, LVDS transmitter converts maximum on-chip data bits into LVDS data streams, using 8-to-1 parallel-to-serial converter.
LVDS Interface
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Figure LVDS Receiver Transmitter Interface
Loadable Shift Register Synchronization Registers Loadable Shift Register
LVDSTX01p LVDSTX01n
LVDSRX01p LVDSRX01n
User Logic
LVDSTXOUTCLK1p LVDSRXINCLK1p LVDSRSINCLK1n
LVDSTXOUTCLK1n PLL4
PLL3
LVDSTXINCLK1p LVDSTXINCLK1n
internal LVDS clocks have maximum multiplication rate. LVDS transmitter ability drive locked clock off-chip. external transmitter clock output output data signals in-phase. Every cycle transmit receive clock data-up bits input output data-are sampled LVDS channels. LVDS input pins pins located right side device. Each LVDS receiver channel interfaces with dedicated shift registers drives lines. Similarly, LVDS output pins also pins located left side device. Each LVDS transmitter channel interfaces with dedicated shift registers, driven adjacent MegaLAB structure.
APEX 20KE Structure
APEX 20KE devices have eight programmable banks dedicated LVDS blocks. Figure shows representation APEX 20KE banks LVDS blocks. LVDS receiver block located right, transmitter block located left.
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Figure APEX 20KE Banks
Bank Bank
Bank
LVDS Transmitter Block Bank
Regular Blocks Support LVTTL LVCMOS 2.5-V 1.8-V 3.3-V PCI-X GTL+ SSTL-3 Class SSTL-2 Class HSTL Class Individual Power
Bank LVDS Receiver Block
Bank
Bank
Note:
Bank
more information placing pins within LVDS blocks, "Guidelines Using LVDS Blocks" page
EP20K400E larger devices support using LVDS dedicated clock signals LVDS data bypass mode. EP20K400E larger devices with suffix their ordering codes support LVDS modes. EP20K300E devices support using LVDS dedicated clock signals LVDS data bypass mode 652-pin ball-grid array (BGA) 672-pin FineLine packages. EP20K200E smaller devices support using LVDS dedicated clock signals. EP20K300E smaller devices, suffix indicates that device includes PLLs. APEX 20KE devices, including devices without suffix their ordering codes, support LVDS dedicated clocks.
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LVDS support summarized Table Table LVDS Support APEX 20KE Devices Device Density
EP20K200E smaller EP20K300E EP20K400E larger
Feature
LVDS Clock LVDS pins LVDS Clock LVDS pins LVDS Clock LVDS pins
Devices with PLLs
Input, output, feedback supported Input, output, feedback mode Input, output, feedback modes
Devices without PLLs
Input supported Input mode Input mode
LVDS transmitter receiver blocks support standards used input, output, bi-directional pins first pins that border LVDS blocks input only maintain acceptable noise level internal VCCIO supply. programmable element (IOE) blocks have individual power planes with separate VCCIO pins each bank. VCCIO planes support 3.3-V, 2.5-V, 1.8-V levels. pins used LVDS standards, always connect LVDS power bus-associated VCCIO pins When used LVDS, LVDS blocks support standards supported APEX 20KE devices.
Board Termination
LVDS standard requires termination resistor between signals receiver side. This termination resistor generates differential output voltage (VOD) receiver input. termination resistor should match differential load impedance (typically values range between Figure shows LVDS board termination receiver.
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Figure LVDS Board Termination Receiver
Transmitting Device Receiving Device
multi-drop configurations where transmitter drives multiple receivers, only termination resistor used, should placed furthest receiver from transmitter device, shown Figure Figure Multi-Drop Configuration Termination
LVDS Design Guidelines
Because high data transmission rates used with LVDS, skew problem. prevent skew maintain signal integrity, follow recommendations below:
Keep stub lengths less than (0.5 inch). Place drivers receivers close connectors possible. Match electrical lengths LVDS lines. Minimize distance between traces pair LVDS lines maximize Common Mode Rejection Ratio (CMRR). Separate TTL/CMOS signals from LVDS signals onto different board layers. multi-layer with ground plane beneath LVDS lines. Avoid degree bends multiple vias. same number bends vias each signal pair match delays. good decoupling techniques. four surface-mount bypass capacitors (2.2 0.01 0.001 placed close GND_CKLK3/VCC_CKLK3 GND_CKLK4/VCC_CKLK4 pairs eliminate switching noise. These capacitors vertically stacked conserve board space. Place parallel termination resistor receiver input. Match trace differential impedance with load impedance (100
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Software
This section provides information implementing LVDS standard Quartus software. LVDS easily implemented APEX devices using Quartus software altlvds megafunction, saving design time reducing board space.
LVDS Paired Labeling
Information dual-purpose paired LVDS pins displayed same text string other information pin, similar other pins that have secondary functions such INIT_DONE. example, Figure page shown I/O, LVDSRXINCLK1p. LVDS pins have specific naming convention: LVDS names begin with LVDS. next characters data pins indicate whether they belong receiver (RX) transmitter (TX), followed two-digit channel <number> which ranges from last character name indicates polarity; positive polarity negative polarity. Table summarizes LVDS names. Table LVDS Naming Convention (Part Names
LVDSRX<number>p LVDSRX<number>n LVDSTX<number>p LVDSTX<number>n LVDSRXINCLK1p LVDSRXINCLK1n LVDSTXINCLK1p LVDSTXINCLK1n LVDSTXOUTCLK1p LVDSTXOUTCLK1n CLK1p CLK1n CLK2p CLK2n CLK3p CLK3n CLK4p
Function
Receiver positive data Receiver negative data Transmitter positive data Transmitter negative data Receiver input clock positive Receiver input clock negative Transmitter input clock positive Transmitter input clock negative Transmitter output clock positive Transmitter output clock negative Dedicated clock positive (PLL Dedicated clock negative (PLL Dedicated clock positive (PLL Dedicated clock negative (PLL Dedicated clock positive (PLL Dedicated clock negative (PLL Dedicated clock positive (PLL
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Table LVDS Naming Convention (Part Names
CLK4n CLKLK_FB1p CLKLK_FB1n CLKLK_FB2p CLKLK_FB2n CLKLK_OUT1p CLKLK_OUT1n CLKLK_OUT2p CLKLK_OUT2n
Function
Dedicated clock negative (PLL Dual-purpose ClockLock feedback positive (PLL Dual-purpose ClockLock feedback negative (PLL Dual-purpose ClockLock feedback positive (PLL Dual-purpose ClockLock feedback negative (PLL Dual-purpose ClockLock output positive (PLL Dual-purpose ClockLock output negative (PLL Dual-purpose ClockLock output positive (PLL Dual-purpose ClockLock output negative (PLL
dedicated clock pins (CLK1p, CLK2p, CLK3p, CLK4p) support LVDS have optional dual-purpose negative polarity pins associated with them. feedback pins (CLKLK_FB1p, CLKLK_FB2p) output pins (CLKLK_OUT1p, CLKLK_OUT2p) also support LVDS following same convention dedicated clock pins. Figure shows LVDS receiver Floorplan Editor. receiver data channel, represented LVDSRX01p LVDSRX01n, feeds dedicated serial-to-parallel converter. LVDS clock (LVDSRXINCLK1p, LVDSINCLK1n) clocks serial-to-parallel converter. serial-toparallel converter shown filled rectangle adjacent register associated with each positive polarity LVDS data clock pin.
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Figure LVDS Receiver Floorplan Editor
LVDS Positions
Data synchronization necessary successful data transmission high frequencies. Figure shows data orientation receiver channel operating mode. Unlike calibration mode, first data current clock cycle third because first bits belong previous cycle. Similar positioning exists most significant bits (MSBs) least significant bits (LSBs) after deserialization, seen Table
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Figure Order Channel LVDS Data
Table shows conventions LVDS naming. Table LVDS Naming Receiver Data Channel Number
Internal CMOS 8-bit Parallel Data Position
Position
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altlvds Megafunction
Figures show symbols altlvds megafunction transmitter receiver, respectively. Each module represents dedicated LVDS silicon present APEX 20KE devices well dedicated LVDS PLLs that present clock generation. single module represents either multiple LVDS channels. Figure altlvds Megafunction Transmitter Module Symbol
Figure altlvds Megafunction Receiver Module Symbol
Figures through show AHDL Function Prototype (port name order also apply Verilog HDL) VHDL Component Declaration sample scripts both LVDS transmitter receiver.
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Figure AHDL Function Prototype (Transmitter) FUNCTION altlvds_tx tx_inclock, sync_inclock, tx_pll_enable) WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, REGISTERED_INPUT, MULTI_CLOCK, INCLOCK_PERIOD, OUTCLOCK_DIVIDE_BY, INTENDED_DEVICE_FAMILY) RETURNS tx_outclock, tx_locked);
Figure VHDL Component Declaration (Transmitter) COMPONENT altlvds_tx GENERIC (NUMBER_OF_CHANNELS: NATURAL; DESERIALIZATION_FACTOR: NATURAL; OUTCLOCK_DIVIDE_BY: NATURAL:= REGISTERED_INPUT: STRING:= "ON"; MULTI_CLOCK: STRING:= "OFF"; INCLOCK_PERIOD: NATURAL); CLOCK_SETTING: STRING:= "UNUSED"); INTENDED_DEVICE_FAMILY: STRING:= "APEX 20KE"); PORT (tx_in: DOWNTO tx_inclock: STD_LOGIC; sync_inclock: STD_LOGIC:= '0'; tx_pll_enable: STD_LOGIC:= tx_out: DOWNTO tx_outclock, tx_locked: STD_LOGIC); COMPONENT;
Figure AHDL Function Prototype (Receiver) FUNCTION altlvds_rx (rx_in[NUMBER_OF_CHANNELS-1.0], rx_inclock, rx_deskew, rx_pll_enable) WITH (NUMBER_OF_CHANNELS, DESERIALIZATION_FACTOR, REGISTERED_OUTPUT, INCLOCK_PERIOD, INTENDED_DEVICE_FAMILY) RETURNS rx_outclock, rx_locked);
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Figure VHDL Component Declaration (Receiver) COMPONENT altlvds_rx GENERIC(NUMBER_OF_CHANNELS: NATURAL; DESERIALIZATION_FACTOR: NATURAL; REGISTERED_OUTPUT: STRING "ON"; INCLOCK_PERIOD: NATURAL; CLOCK_SETTING: STRING "UNUSED"); INTENDED_DEVICE_FAMILY: STRING:= "APEX20KE"); PORT (rx_in: DOWNTO rx_inclock: STD_LOGIC; rx_deskew: STD_LOGIC '0'; rx_pll_enable: STD_LOGIC:= rx_out: DOWNTO rx_outclock, rx_locked: STD_LOGIC); COMPONENT; altlvds megafunction input output ports described Tables respectively. Table lists parameters that used configure altlvds megafunction. Table Input Ports altlvds Megafunction Port Name Required Description LVDS Transmitter Input Ports
tx_in[] Input data Input port [(DESERIALIZATION_FACTOR) (NUMBER_OF_CHANNELS-1.0)] wide. LVDSTXINCLK cannot clock registers; Quartus software will return error LVDSTXINCLK tries clock registers. When using LVDSTXINCLK mode, MULTI_CLOCK parameter MULTI_CLOCK parameter turned must sync_inclock port. Input port [NUMBER_OF_CHANNELS-1.0] wide. more information rx_deskew port, contact Altera Applications.
Notes
tx_inclock
LVDS reference input clock
sync_inclock tx_pll_enable rx_in[] rx_inclock rx_deskew rx_pll-enable
Optional clock input registers Enable control LVDS LVDS input data channel LVDS reference input clock Specifies whether activate calibration mode Enable control LVDS
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Table Output Ports altlvds Megafunction Port Name Required Description LVDS Transmitter Output Ports
tx_out[] tx_outclock tx_locked Serialized LVDS data signal External reference clock Gives status LVDS When locked, this signal VCC. When fails lock, this signal GND. Output port [NUMBER_OF_CHANNELS- 1.0] wide.
Notes
LVDS Receiver Output Ports
rx_out[] Deserialized data signal Output port [(DESERIALIZATION_FACTOR) (NUMBER_OF_CHANNELS-1.0)] wide. This signal only used clock internal logic. When locked, this signal VCC. When fails lock, this signal GND.
rx_outclock rx_locked
Internal reference clock Gives status LVDS
Table altlvds Megafunction Parameters (Part Parameter Type Required Description
LVDS Transmitter Parameters
NUMBER_OF_CHANNELS DESERIALIZATION_FACTOR REGISTERED_INPUT Integer Integer String Specifies number LVDS channels. Specifies number bits channel. Values Indicates whether tx_out[] tx_in[]port should registered. Values "ON" "OFF." omitted default "ON." Indicates whether sync_inclock port used input registering. Values "ON" "OFF." omitted default "OFF." Specifies period frequency input clocks. default time unit
MULTI_CLOCK
String
INCLOCK_PERIOD
String
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Table altlvds Megafunction Parameters (Part Parameter Type Required Description
LVDS Transmitter Parameters
OUTCLOCK_DIVIDE_BY Integer Specifies period tx_outclock port [(INCLOCK_PERIOD) (OUTCLOCK_DIVIDE_BY)]. default value this parameter value DESERIALIZATION_FACTOR parameter. APEX 20KE devices, OUTCLOCK_DIVIDE_BY DESERIALIZATION_FACTOR This parameter used modeling behavioral simulation purposes. Create with MegaWizard Plug-in Manager calculate value this parameter.
INTENDED_DEVICE_FAMILY
String
LVDS Receiver Parameters
NUMBER_OF_CHANNELS DESERIALIZATION_FACTOR REGISTERED_OUTPUT Integer Integer String Specifies number LVDS channels. Specifies number bits channel. Values Indicates whether rx_out[] port should registered. Values "ON" "OFF." omitted, default "ON." Specifies period frequency rx_inclock port. default time unit This parameter used modeling behavioral simulation purposes. Create with MegaWizard Plug-in Manager calculate value this parameter.
INCLOCK_PERIOD
String
INTENDED_DEVICE_FAMILY
String
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MegaWizard Interface
MegaWizard® interface allows users customize LVDS megafunction. MegaWizard Plug-In Manager automatically generates following files:
Component Declaration File (.cmp) that used VHDL Design Files (.vhd) Include File (.inc) that used Text Design Files (.tdf) Verilog Design Files (.v) Quartus Block Symbol File (.bsf) that used Quartus Block Design Files (.bdf) Custom Megafunction variation file (TDF, VHD, file)
MegaWizard Plug-In Manager invoked ways:
Choosing MegaWizard Plug-In Manager command from Tools menu, seen Figure Selecting MegaWizard Plug-In Manager from Symbol dialog Block Editor, seen Figure
Figure Invoking MegaWizard Plug-In Manager from Tools Menu
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Figure Invoking MegaWizard Plug-In Manager from Block Editor
MegaWizard Plug-In Manager takes step-by-step approach generating customized LVDS transmitter receiver modules. Each page MegaWizard Plug-In Manager allows user select from customizable features that tailors modules needs design. Figure displays third page altlvds megafunction MegaWizard Plug-In Manager when instantiating LVDS transmitter. Figure shows third page receiver instantiation. These pages allow user customize LVDS transmitter receiver modules.
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Figure Page altlvds Transmitter MegaWizard Plug-In Manager
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Figure Page altlvds Receiver MegaWizard Plug-In Manager
Described below various customizable features that available MegaWizard interface:
Number channels this option allows user select number LVDS channels used design. desired value either typed selected from pop-up menu, maximum channels. This simplifies complexity design that only transmitter receiver module needs instantiated represent multiple LVDS channels. Deserialization factor this option specifies number bits channel. user either type select from pop-up menu. Clock frequency/period this option specifies clock frequency period LVDS input clock. LVDS transmitter/receiver this option specifies function LVDS module. Register inputs/outputs specifies whether register inputs transmitter outputs receiver. signals registered adjacent MegaLAB structure, then registered inputs/outputs option must turned
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rx_pll_enable/tx_pll-enable option: optional input ports receiver transmitter which enable control LVDS PLL. tx_locked /rx_locked port this option enables locked transmitter receiver. When phaselocked loop (PLL) locks onto incoming clock generates internal clock, locked signal driven high. remains high long input clock remains within specification. synchronization clock this option activates synchronization clock transmitter. this option activated, synchronization clock must have same frequency phase transmitter clock order avoid hold time violations. synchronization clock, registered_input option must set. registered_input option: from MegaWizard interface, check Register Inputs box, then check synchronization clock box. more guidelines designing LVDS with APEX 20KE devices, "Guidelines Using LVDS Blocks" page rx_deskew input port this option activates deskew input port receiver that used calibrate module.
MegaWizard Examples
Figure shows altlvds transmitter module generated MegaWizard Plug-In Manager with input frequency MHz. channels used with deserialization factor this example, sync_inclock input tx_locked output both used well input registers. Figure 50-MHz 16-Channel LVDS Transmitter
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Figure shows instantiation LVDS receiver with channels input frequency MHz. deserialization factor rx_deskew, rx_outclock, output registers used this example. Figure 50-MHz 16-Channel LVDS Receiver
Examples
following examples show altlvds megafunction transmitter mode receiver mode, respectively, both VHDL Verilog HDL. These examples instantiate LVDS modules connect them input output pins. VHDL LVDS transmitter 16-channel module operating mode with input clock MHz. transmitter's output clock module mode through tx_outclock pin. status monitored from tx_locked pin. input registers also used. Figure lvds_tx.vhd (Part library ieee; ieee.std_logic_1164.all; entity lvds_tx port tx_in: tx_inclock: sync_inclock: tx_out: tx_outclock: tx_locked: lvds_tx;
std_logic_vector(127 downto std_logic; std_logic; std_logic_vector(15 downto std_logic; std_logic
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Figure lvds_tx.vhd (Part architecture apex lvds_tx component altlvds_tx generic (number_of_channels: positive; deserialization_factor: positive; registered_input: string "ON"; multi_clock: string "OFF"; inclock_period: positive; clock_setting: string "UNUSED" port tx_in: std_logic_vector downto tx_inclock: std_logic; sync_inclock: std_logic '0'; tx_out: std_logic_vector (number_of_channels-1 downto tx_outclock: std_logic; tx_locked: std_logic component; begin U0:altlvds_tx generic number_of_channels deserialization_factor inclock_period 9524 port tx_in tx_in, tx_inclock tx_inclock, sync_inclock sync_inclock, tx_out tx_out, tx_outclock tx_outclock, tx_locked tx_locked apex;
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LVDS receiver 16-channel module operating mode with input clock MHz. receiver's output clock cannot directly output pin; therefore, feeds clock port register. Figure lvds_rx.vhd (Part library ieee; ieee.std_logic_1164.all; entity lvds_rx port rx_in: rx_inclock: rx_deskew: rx_out: rx_outclock: rx_locked: inpin: outpin: clear: preset: lvds_rx;
std_logic_vector(15 downto std_logic; std_logic; std_logic_vector(127 downto std_logic; std_logic; std_logic; std_logic; std_logic; std_logic
architecture apex lvds_rx component altlvds_rx generic number_of_channels: positive; deserialization_factor: positive; registered_output: string "ON"; inclock_period: positive; clock_setting: string:= "UNUSED" port rx_in: downto rx_inclock: std_logic; rx_deskew: std_logic '0'; rx_out: number_of_channels-1 downto rx_outclock: std_logic; rx_locked: std_logic component; component
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Figure lvds_rx.vhd (Part port std_logic; std_logic; clrn: std_logic; std_logic; std_logic component; signal clock: std_logic; begin altlvds_rx generic number_of_channels deserialization_factor inclock_period 9524 port rx_in rx_in, rx_inclock rx_inclock, rx_deskew rx_deskew, rx_out rx_out, rx_outclock clock, rx_locked rx_locked port inpin, clock, clrn clear, preset, outpin); apex;
Verilog following examples show altlvds megafunction Verilog both transmitter receiver, respectively. LVDS transmitter 16-channel module, operating with input clock deserialization factor output clock directly tx_outclock output pin.
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Figure lvds_tx.v module lvds_tx (tx_in, tx_inclock, tx_out, tx_outclock, tx_locked); input[127:0] tx_in; input tx_inclock; output[15:0] tx_out; output tx_outclock; output tx_locked; altlvds_tx (.tx_in (tx_in), .tx_inclock (tx_inclock), .tx_out (tx_out), .tx_outclock (tx_outclock), .tx_locked (tx_locked)); defparam U0.number_of_channels U0.deserialization_factor= U0.registered_input "On", U0.multi_clock "Off", U0.inclock_period 9524; endmodule
receiver also 16-channel module with input clock frequency deserialization factor output clock clock port register since cannot directly output pin. Figure lvds_rx.v module lvds_rx rx_in, rx_inclock, rx_deskew, rx_out, rx_locked, inpin, outpin); input[15:0] rx_in; input rx_inclock; input rx_deskew; output[127:0] rx_out; output rx_locked; input inpin; output outpin; pll_out; altlvds_rx (.rx_in (rx_in), .rx_inclock (rx_inclock), .rx_deskew (rx_deskew), .rx_out (rx_out), .rx_outclock (pll_out), .rx_locked (rx_locked)); defparam U0.number_of_channels U0.deserialization_factor= U0.registered_output "ON", U0.inclock_period 9524; (.d(inpin), .q(outpin), .clk(pll_out)); endmodule
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Synthesis with Third-Party Tools
synthesize design successfully third-party tools such Synplify, FPGA Compiler/II, FPGA Express, LeonardoSpectrum, LVDS design component must treated black box. declaring module black box, synthesis tools will refrain from synthesizing module. However, correct port connections will made output EDIF netlist file (.edf) Verilog Quartus mapping file (.vqm). When netlist file brought into Quartus software, native synthesis black-boxed module automatically performed. LVDS module must first generated MegaWizard Plug-In Manager, which involves specifying name module ports that used. Below examples LVDS transmitter design VHDL Verilog several third-party tools. file named mylvds_tx MegaWizard-generated file.
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Figure Exemplar Synplify FPGA Compiler/II: lvds_tx.vhd library ieee; ieee.std_logic_1164.all; entity lvds_tx port tx_in: tx_inclock: sync_inclock: tx_out: tx_outclock: tx_locked: lvds_tx;
std_logic_vector(127 downto std_logic; std_logic; std_logic_vector(15 downto std_logic; std_logic
architecture apex lvds_tx component mylvds_tx port tx_in: tx_inclock: sync_inclock: tx_out: tx_outclock: tx_locked: component;
std_logic_vector(127 downto std_logic; std_logic; std_logic_vector(15 downto std_logic; std_logic
attribute black_box: boolean; attribute black_box mylvds_tx: component true; begin U0:mylvds_tx port (tx_in tx_in, tx_inclock tx_inclock, sync_inclock sync_inclock, tx_out tx_out, tx_outclock tx_outclock, tx_locked tx_locked); apex;
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Figure Exemplar LeonardoSpectrum: lvds_tx.vhd library ieee; ieee.std_logic_1164.all; entity lvds_tx port tx_in: tx_inclock: sync_inclock: tx_out: tx_outclock: tx_locked: lvds_tx;
std_logic_vector(127 downto std_logic; std_logic; std_logic_vector(15 downto std_logic; std_logic
architecture apex lvds_tx component mylvds_tx port tx_in: tx_inclock: sync_inclock: tx_out: tx_outclock: tx_locked: component;
std_logic_vector(127 downto std_logic; std_logic; std_logic_vector(15 downto std_logic; std_logic
attribute noopt: boolean; attribute noopt mylvds_tx: component true; begin U0:mylvds_tx port (tx_in tx_in, tx_inclock tx_inclock, sync_inclock sync_inclock, tx_out tx_out, tx_outclock tx_outclock, tx_locked tx_locked); apex;
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code below demonstrates black-boxing Verilog using same transmitter module generated MegaWizard Plug-In Manager. Figure Exemplar Synplify/FPGA Complier/II: lvds_tx.v module mylvds_tx (tx_in, tx_inclock, tx_out, tx_outclock, tx_locked); /*synthesis black_box*/ input[127:0] tx_in; input tx_inclock; output[15:0] tx_out; output tx_outclock; output tx_locked; endmodule module lvds_tx (tx_in, tx_inclock, tx_out, tx_outclock, tx_locked); input[127:0] tx_in; input tx_inclock; output[15:0] tx_out; output tx_outclock; output tx_locked; mylvds_tx (.tx_in (tx_in), .tx_inclock (tx_inclock), .tx_out (tx_out), .tx_outclock (tx_outclock), .tx_locked (tx_locked)); endmodule Figure Exemplar LeonardoSpectrum: lvds_tx.v module mylvds_tx (tx_in, tx_inclock, tx_out, tx_outclock, tx_locked); input[127:0] tx_in; input tx_inclock; output[15:0] tx_out; output tx_outclock; output tx_locked; endmodule higher level file module lvds_tx (tx_in, tx_inclock, tx_out, tx_outclock, tx_locked); input[127:0] tx_in; input tx_inclock; output[15:0] tx_out; output tx_outclock; output tx_locked; mylvds_tx (.tx_in (tx_in), .tx_inclock (tx_inclock), .tx_out (tx_out), .tx_outclock (tx_outclock), .tx_locked (tx_locked)); //exemplar attribute NOOPT TRUE endmodule
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Quartus software must configured that recognizes netlist file from third-party synthesis tool. synthesis tool selected from Tool Settings dialog (Project menu) Quartus software, seen Figure More information regarding Quartus software's integration with third-party tools found Altera site Figure Tool Settings Quartus Software
Testbenches
following testbench examples, which used third-party simulators such ModelSim, show functionality LVDS behavioral model. receiver's output connected directly transmitter's input. deskew asserted, calibration pattern applied first. this done correctly, model will allow data exit transmitter. test pattern enters receiver's input port subsequently leaves transmitter's output port after clock cycles latency. When running this test bench, ensure that time resolution simulator picoseconds. More information receiver calibration found following VHDL Verilog testbench examples.
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Figure VHDL HDL: lvds_test.vhd (Part LIBRARY ieee; ieee.std_logic_1164.ALL; ieee.std_logic_arith.ALL; ieee.std_logic_unsigned.ALL; std.textio.ALL; ENTITY lvds_test lvds_test; ARCHITECTURE testbench lvds_test SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL rx_in rx_inclock rx_deskew synch_inclock: tx_out tx_outclock rx_out rx_outclock lvds_data_clk: std_logic_vector(3 downto "0000"; std_logic '1'; std_logic '0'; std_logic '0'; std_logic_vector(3 downto std_logic; std_logic_vector(31 downto std_logic; std_logic '1';
TYPE rx_buffer ARRAY(0 std_logic; BEGIN Instantiate LDVS Receiver altlvds_rx GENERIC number_of_channels deserialization_factor inclock_period 9524, registered_output "ON") PORT rx_in rx_in, rx_inclock rx_inclock, rx_deskew rx_deskew, rx_out rx_out, rx_outclock rx_outclock); Instantiate LVDS Transmitter altlvds_tx GENERIC number_of_channels deserialization_factor inclock_period 128000, registered_input "ON") tx_in rx_out,
PORT
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Figure VHDL HDL: lvds_test.vhd (Part tx_inclock rx_inclock, sync_inclock synch_inclock, tx_out tx_out, tx_outclock tx_outclock); Create 7,812,500 clock PROCESS(rx_inclock) BEGIN rx_inclock rx_inclock AFTER PROCESS; Create 62,500,000 lvds data clock synch data inputs PROCESS(lvds_data_clk) BEGIN lvds_data_clk lvds_data_clk AFTER PROCESS; PROCESS VARIABLE deskew_pattern std_logic_vector(23 downto "000011110000111100001111"; VARIABLE test_pattern std_logic_vector(15 downto "0000011000000001"; VARIABLE integer range VARIABLE deskew_cnt: integer range BEGIN deskew_cnt THEN deskew_cnt THEN rx_deskew '1'; rx_in(0) deskew_pattern(deskew_cnt -24); rx_in(1) deskew_pattern(deskew_cnt -24); rx_in(2) deskew_pattern(deskew_cnt -24); rx_in(3) deskew_pattern(deskew_cnt -24); deskew_cnt deskew_cnt wait until ((lvds_data_clk'event) (lvds_data_clk '1')); ELSIF THEN rx_deskew '0'; rx_in(0) test_pattern(cnt); rx_in(1) test_pattern(cnt); rx_in(2) test_pattern(cnt); rx_in(3) test_pattern(cnt); wait until ((lvds_data_clk'event) (lvds_data_clk '1')); ELSE
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Figure VHDL HDL: lvds_test.vhd (Part PROCESS; testbench;
Figure Verilog HDL: lvds_test.v (H4) (Part `timescale 1ps/1ps module lvds_test(); [3:0] rx_in; rx_inclock; rx_deskew; synch_inclock; wire [3:0] tx_out; wire tx_outclock; wire [31:0] rx_out; wire rx_outclock; lvds_data_clk; [23:0] deskew_pattern; [15:0] test_pattern; [3:0] cnt; [5:0] deskew_cnt; altlvds_rx L0(.rx_in(rx_in), .rx_inclock(rx_inclock), .rx_deskew(rx_deskew), .rx_out(rx_out), .rx_outclock(rx_outclock)); defparam L0.number_of_channels defparam L0.deserialization_factor defparam L0.registered_output "ON"; defparam L0.inclock_period 128000; altlvds_tx L1(.tx_in(rx_out), .tx_inclock(rx_inclock), .sync_inclock(synch_inclock), .tx_out(tx_out), .tx_outclock(tx_outclock)); defparam L1.number_of_channels defparam L1.deserialization_factor defparam L1.registered_input "ON"; defparam L1.inclock_period 128000; initial begin rx_in 4'b0000;
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rx_deskew 1'b0;
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Figure Verilog HDL: lvds_test.v (H4) (Part synch_inclock 1'b0; deskew_cnt 6'b000001; 4'b0000; deskew_pattern 24'b000011110000111100001111; test_pattern 16'b1000011110000001; initial begin rx_inclock 1'b1; forever #64000 rx_inclock ~rx_inclock; initial begin lvds_data_clk 1'b1; forever #8000 lvds_data_clk ~lvds_data_clk; always@(posedge lvds_data_clk) begin (deskew_cnt begin (deskew_cnt begin rx_deskew 1'b1; rx_in[0] deskew_pattern[deskew_cnt-24]; rx_in[1] deskew_pattern[deskew_cnt-24]; rx_in[2] deskew_pattern[deskew_cnt-24]; rx_in[3] deskew_pattern[deskew_cnt-24]; deskew_cnt deskew_cnt else (cnt begin rx_deskew 1'b0; rx_in[0] test_pattern[cnt]; rx_in[1] test_pattern[cnt]; rx_in[2] test_pattern[cnt]; rx_in[3] test_pattern[cnt]; else endmodule
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Quartus LVDS Reporting
Quartus software reports LVDS usage compilation report file. report file documents information pertaining LVDS resource usage placement APEX device under following categories:
Package Pins Control Signals Global Other Fast Signals LVDS ClockLock
This section briefly describes each category.
Package Pins
This category report file indicates function location package pins. LVDS pins displayed with their names numbers, seen Figure example. Figure Package Pins Category Report File
Quartus software adheres previously discussed banking rules will place non-LVDS outputs LVDS-enabled banks. such configurations, design yields no-fit, indicating that these nonLVDS outputs illegally placed. more information using standards Quartus software, refer Application Note (Using Standards Quartus Software).
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Control Signals
Control Signals category reports control signals that present design. LVDS control signals, such input clocks output clocks, reported seen Figure output clocks denoted either pll_clk0 pll_clk1. pll_clk1 output clock directly transmitter mode. Figure Control Signals Category Report File
Global Other Fast Signals
Global Other Fast Signals category displays globally routed signals design. When LVDS used, only PLL-generated clocks synchronization clocks routed globally seen Figure number fan-out nodes global signal also displayed. Figure Global Other Fast Signals Category Report File
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120: Using LVDS APEX 20KE Devices
LVDS
This category reports LVDS usage design, seen Figure instance name displayed along with function deserialization factor. Both output clocks LVDS modules also shown. LVDS category omitted when LVDS used APEX device. Figure LVDS Section Report File
ClockLock
ClockLock category report file, seen Figure gives specifications each that used. input frequency indicated well various resulting clock frequencies after multiplication deserialization factor. Figure ClockLock Section Report File
Floorplanner
Floorplanner gives visual representation internal routing placement logic within device. Figure shows Floorplan view LVDS transmitter. transmitter divided between more colored blocks: LVDS located adjacent transmitter output clock pins (LVDSTXOUTCLK1p LVDSTXOUTCLK1n), individual parallelto-serial converters located adjacent each pair LVDS data-out pins (e.g., LVDSTX01p LVDSTX01n).
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120: Using LVDS APEX 20KE Devices
Figure Floorplan View LVDS Transmitter
Figure appears equations LVDS_PLLTX_1, single parallel-to-serial converter appears LVDSTX_1. logic cells that appear right LVDS modules represent additional logic that consumed during implementation. transmitter's locked clock (pll_clk1) driven off-chip mode through transmitter output clock pins.
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120: Using LVDS APEX 20KE Devices
Quartus software displays LVDS receiver module similar fashion, seen Figure receiver divided between more colored blocks: LVDS located adjacent receiver input clock pins (LVDSRXINCLK1p LVDSRXINCLK1n), individual serial-to-parallel converters located adjacent LVDS data-in pins (LVDSRX01p LVDSRX01n). appears LVDS_PLLRX_1, serial-to-parallel converter appears LVDSRX_1 this example. logic cells that appear left LVDS modules represent additional logic that consumed during implementation. Because receiver output clock cannot externally, does fan-out pins Floorplan view. Figure Floorplanner View LVDS Receiver
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120: Using LVDS APEX 20KE Devices
Simulation Quartus
Quartus development tool provides users with capability conveniently efficiently simulate LVDS design. Vector waveform files (.vwf), which used inputs native simulation tool, created within Quartus software. simulation model LVDS receiver essentially serialization shift-register that driven LVDS data channel clocked LVDS multiplied serialization value. shift-register drives bank data registers clocked original clock. LVDS transmitter module inverse receiver. data register driven internal parallel data signals clocked original LVDS clock. then loads shift-register that drives LVDS output clocked multiplied output LVDS PLL. more information simulation Quartus software, Quartus Help. Figure shows results example functional simulation LVDS transmitter. 16-channel transmitter operating with synchronization clock activated deserialization factor Figure Example Functional Simulation Waveform LVDS Transmitter
locked tx_locked remains high long input frequency valid. input clock tx_inclock synchronization clock syn_inclock must have exact same phase frequency module function correctly. clocks must also have same frequency specified design files. frequency differs, Simulator will warn that unable lock onto incoming clocks. incoming data tx_in synchronized with input clocks tx_inclock syn_inclock. output data tx_out synchronized with output clock tx_outclock that same frequency input clock. output clock same frequency input clock, (not internally multiplied clock), because only version PLL-generated clock out. output data transitions times within period clock, indicating that deserialization factor
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120: Using LVDS APEX 20KE Devices
Figure shows results example functional simulation deskew circuitry LVDS receiver. deskew rx_deskew asserted least three clock cycles after locks onto incoming clock deskew calibration pattern applied channels. deskew prematurely de-asserted deskew calibration pattern incorrect, Quartus software will warn that deskew de-asserted invalid time. Figure Example Functional Simulation Waveform Receiver Calibration
Figure shows results example functional simulation LVDS receiver. locked rx_locked asserted long incoming clock signal valid. valid frequency determined value that MegaWizard Plug-In Manager. this frequency does correspond, simulation will indicate that could lock onto incoming clock signal. Figure Example Functional Simulation Waveform LVDS Receiver
incoming data synchronized with incoming clock signal rx_inclock. input data transitions times within incoming clock period, indicating that deserialization factor output data synchronized with output clock receiver module, which displayed figure. Figure indicates mapping performed Quartus software single receiver channel operating mode MHz. functional simulation waveforms show that data current clock cycle rx_inclock (beginning 41.66 maps appropriate positions, indicated Table page first data current clock cycle accepted until 45.83 which immediately after last bits previous cycle accepted.
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120: Using LVDS APEX 20KE Devices
Figure Mapping Sample Waveform
Guidelines Using LVDS Blocks
When using differential signaling receiver and/or transmitter LVDS blocks, cannot place non-differential output pins within pads LVDS receiver transmitter blocks. cannot place single-ended outputs LVDS block pins when using differential signaling channels. Using switching outputs LVDS block pins (except LOCK pin) could affect True-LVDS pins degrade performance. switching outputs LOCK because rarely changes. shown Figure output pins must least pads away from LVDS receiver transmitter blocks unless separated power ground pin. two-pad guideline also applies dedicated LVDS clock pins global clock pins when using differential signaling. cannot place output pins within pads LVDS clock pins (both dedicated non-dedicated) unless separated power ground pin. unused True-LVDS pins input pins without compromising acceptable noise level VCCIO plane. Show Pads view Quartus Floorplan Editor used order.
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120: Using LVDS APEX 20KE Devices
Figure Placement Bank Adjacent LVDS Blocks
Regular banks
Other pads inputs outputs
Shared VCCIO
pads next LVDS inputs Pads LVDS non-LVDS inputs
LVDS receiver transmitter block LVDS pads
Required Guidelines LVDS APEX 20KE Devices
information this section when designing LVDS with APEX 20KE devices. Altera recommends that read these guidelines before laying boards. Global line always used designs using LVDS receiver. There registers internal megafunction that clocked using clock generated LVDS receiver PLL. Therefore, global line will used even rx_outclock port feeding clock input ports design files. registers necessary synchronization between LVDS block core created internally megafunction under following circumstances:
When LVDS receiver mode. mode case, there extra hold registers required output LVDS block. When registered outputs megafunction disabled, these hold registers will still exist. When LVDS receiver mode registered outputs enabled megafunction.
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120: Using LVDS APEX 20KE Devices
only case where registers created inside megafunction when LVDS receiver mode registered outputs disabled. this case LVDS receiver will function correctly unless data into core logic (LEs, ESBs). this case, rx_outclock required, result, global line still necessary. LVDSTXINCLK pins cannot feed core logic (LEs, ESBs) because data transfer from core logic LVDS transmitter block creates hold time violations. Care should taken when designing with LVDSTXINCLK pins. following cases, altlvds transmitter megafunction must have MULTI_CLOCK setting sync_inclock port must used. global clock pin(s) that feeds sync_inclock must same phase frequency LVDSTXINCLK pins.
Required when LVDS transmitter modes, which have extra hold registers instantiated megafunction input LVDS transmitter block. even disable registered inputs megafunctions, these hold registers will still exist. When LVDS transmitter mode registered inputs enabled megafunction.
easiest implement dual frequency applications LVDSRXINCLK feed receiver dedicated clock feed transmitter PLL. When designing with LVDS transmitter receiver blocks, pads around LVDS signal cannot used output pin. Quartus software will report error message violating two-pad rule next LVDS pins. These pads input only because LVDS blocks share same VCCIO supply with bank that located Noise from switching non-LVDS output pins would degrade LVDS performance LVDS block.
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120: Using LVDS APEX 20KE Devices
Packaging
inductance capacitance 1.27-mm 1.0-mm FineLine packages makes them ideal LVDS feature. balls used LVDS signals located outer rows balls FineLine package. Figure shows LVDS ball placement 672-pin FineLine package EP20K400E, EP20K600E, EP20K1000E devices. marked pins include LVDS input signals LVDS clock input left side package (bottom view). LVDS output signals, clock signal, clock output signal shown right side package.
Figure Location LVDS Balls 672-Pin FineLine Package
LVDSTXINCLK LVDSTXOUTCLK
LVDS input pairs placed outer rows balls minimize skew.
LVDS Transmitter Data Channels
LVDSRXINCLK
Applications
APEX devices offer different LVDS modes with multiple ways connect receiver transmitter LVDS PLLs. interface multiple LVDS devices using method that accommodates your design needs. following LVDS applications supported with APEX 20KE devices:
Point-to-point configurations Multi-drop LVDS Bypassing dedicated LVDS converter circuitry
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120: Using LVDS APEX 20KE Devices
Point-to-Point Configurations
Point-to-point LVDS applications involve devices communicating data LVDS. point-to-point communication, receiver clocked from either sources: same source transmitting devices output clock generated transmitting devices. Figures show both cases. high performance, source synchronous clocking scheme shown Figure Standard timing parameters (setup time clock-to-output) must taken into consideration application shown Figure source synchronous application, designers should follow LVDS timing budget defined "Data Orientation" page Figure Transmitter Clocks Receiver
Device
External Clock
Device
Data
Channels Internal Logic Bridges Clock Domain FIFO Internal Logic Optionally Clocked Different Frequency
Clock
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120: Using LVDS APEX 20KE Devices
Figure Receiver PLLs Clocked Board Clock
Device Device
Data
Channels Internal Logic Bridges Clock Domain FIFO Internal Logic Optionally Clocked Different Frequency
Clock
Multi-Drop Configurations
Multi-drop configurations have transmitter multiple receivers. transmitter clock from source device clocks LVDS PLLs receiving devices. Performance affected number loads that transmitter required drive. Preliminary information shows that APEX 20KE device support loads MHz. Contact Altera Applications up-to-date information multi-drop configurations. Figure shows multi-drop configuration with four loads.
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120: Using LVDS APEX 20KE Devices
Figure Multi-Drop Configuration
Receivers Transmitter
Clock Data
Channels
Bypassing Dedicated LVDS Converter Circuitry
data rate LVDS signals that less than Mbps, data bypass dedicated serial-to-parallel converters feed directly, shown Figure global clock either general-purpose bypass globally clock registers directly. used phase shifting clock with respect data achieve maximum timing. setup hold times sufficient meet Mbps requirements. this application method, clock data running same rate. clock standard, general-purpose PLLs used with multiplication clock registers. general-purpose supports LVDS signals operate input frequency MHz.
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120: Using LVDS APEX 20KE Devices
Figure Data Feeds Directly
DATA
IOE, Registers
General Purpose
Summary
APEX 20KE device first offer system-on-aprogrammable-chip (SOPC) LVDS solution. LVDS integration brings higher data transmission rates broader bandwidth, with lower power consumption. LVDS also improves interface performance simplifies board design minimizing number devices used interface with backplanes. LVDS-integrated APEX 20KE devices raise standard solve challenge tomorrow's complex design demands. Electrical Characteristics Voltage Differential Signaling (LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National Standards Institute/Telecommunication Industry Association/Electronic Industries Association. information contained Application Note (Using LVDS APEX 20KE Devices) version supersedes information published previous versions.
References
Revision History
Version
following change made Application Note (Using LVDS APEX 20KE Devices) version 1.3:
Updated Figure
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120: Using LVDS APEX 20KE Devices
Version
following changes were made Application Note (Using LVDS APEX 20KE Devices) version 1.2:
Updated Figure Updated Note Figure Updated Figure Updated "Guidelines Using LVDS Blocks" page
Version
following changes were made Application Note (Using LVDS APEX 20KE Devices) version 1.1:
Corrected equation margin page Updated Table include note rx_outclock. Corrected Figures
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Copyright 2002 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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APEX 20KE Devices Application Note 2002, ver. Introduct

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