October 1997 Revised April 2002 High Speed CMOS Logic 3-to-8 Line

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October 1997 Revised April 2002 High Speed CMOS Logic 3-to-8 Line

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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
October 1997 Revised April 2002
High Speed CMOS Logic 3-to-8 Line Decoder/ Demultiplexer Inverting Non-Inverting
Ordering Information
PART NUMBER CD54HC138F CD54HC138F3A CD74HC138E CD74HC138M CD54HCT138F CD54HCT138F3A CD74HCT138E CD74HCT138M CD54HC238F3A CD74HC238E CD74HC238M CD74HC238NSR CD54HCT238F3A CD74HCT238E CD74HCT238M NOTES: When ordering, entire part number. suffix obtain variant tape reel. Wafer this part number available which meets electrical specifications. Please contact your local sales office customer service ordering information. TEMP. RANGE (oC) PACKAGE CERDIP CERDIP PDIP SOIC CERDIP CERDIP PDIP SOIC CERDIP PDIP SOIC CERDIP PDIP SOIC
Features
Select Eight Data Outputs Active 138, Active High
/Title (CD74 HC138 CD74 HCT13 CD74 HC238 CD74 HCT23 /Subject (High Speed
Port Memory Selector Three Enable Inputs Simplify Cascading Typical Propagation Delay 13ns 15pF, 25oC Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Description
'HC138, 'HC238, 'HCT138, 'HCT238 high speed silicon gate CMOS decoders well suited memory address decoding data routing applications. Both circuits feature power consumption usually associated with CMOS circuitry, have speeds comparable power Schottky logic. Both circuits have three binary select inputs (A0, A2). device enabled, these inputs determine which eight normally high outputs HC/HCT138 series will which normally outputs HC/HCT238 series will high. active active high enables (E1, provided ease cascading decoders. decoder's outputs drive power Schottky equivalent loads.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2002, Texas Instruments Incorporated
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Pinout
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238 (CERDIP) CD74HC138, CD74HCT138, CD74HCT238 (PDIP, SOIC) CD74HC238 (PDIP, SOIC, SOP) VIEW
(Y7) (Y0) (Y1) (Y2) (Y3) (Y4) (Y5) (Y6)
Signal names parentheses 'HC138 'HCT138.
Functional Diagram
HC/HCT HC/HCT
TRUTH TABLE 'HC138, 'HCT138 INPUTS ENABLE ADDRESS OUTPUTS
NOTE: High Voltage Level, Voltage Level, Don't Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
TRUTH TABLE 'HC238, 'HCT238 INPUTS ENABLE ADDRESS OUTPUTS
NOTE: High Voltage Level, Voltage Level, Don't Care
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, IGND .±50mA
Thermal Information
Package Thermal Impedance, (see Note PDIP Package 67oC/W SOIC Package 73oC/W Package 64oC/W Maximum Junction Temperature 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range (TA) -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 ±0.1 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load (Note NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. -2.1 -0.02 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT A0-A2 UNIT LOADS 1.25
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
Switching Specifications Input
TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay Address Output
SYMBOL
tPLH, tPHL 50pF
15pF 50pF
CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238
Switching Specifications Input
(Continued) 25oC Output Transition Time (Figure tTLH, tTHL 50pF Power Dissipation Capacitance, (Notes Input Capacitance TYPES Propagation Delay Address Output tPLH, tPHL 50pF 15pF Enable Output HC/HCT138 Enable Output HC/HCT238 Output Transition Time (Figure Power Dissipation Capacitance, (Notes Input Capacitance NOTES: used determine dynamic power consumption, gate. VCC2 (CPD where: Input Frequency, Output Load Capacitance, Supply Voltage. tPLH, tPHL 50pF tPLH, tPHL 15pF tTLH, tTHL 50pF 15pF 15pF -40oC 85oC -55oC 125oC UNITS
PARAMETER Enable Output HC/HCT138
SYMBOL
TEST CONDITIONS
tPLH, tPHL 50pF
Test Circuits Waveforms
INPUT tTLH tPHL tPLH INPUT tTHL 2.7V 1.3V 0.3V tTLH INVERTING OUTPUT tPHL tPLH 1.3V
tTHL
INVERTING OUTPUT
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
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Copyright 2002, Texas Instruments Incorporated

October 1997 Revised April 2002 High Speed CMOS Logic 3-to-8 Line

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