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CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238

October 1997 - Revised April 2002

CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238
Data sheet acquired from Harris Semiconductor SCHS147D
October 1997 - Revised April 2002
High Speed CMOS Logic 3-to-8 Line Decoder / Demultiplexer Inverting and Non-Inverting
Ordering Information
PART NUMBER CD54HC138F CD54HC138F3A CD74HC138E CD74HC138M CD54HCT138F CD54HCT138F3A CD74HCT138E CD74HCT138M CD54HC238F3A CD74HC238E CD74HC238M CD74HC238NSR CD54HCT238F3A CD74HCT238E CD74HCT238M NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOP 16 Ld CERDIP 16 Ld PDIP 16 Ld SOIC
Features
· Select One Of Eight Data Outputs Active Low for 138, Active High for 238
/ Title (CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8) / Subject (High Speed
Description
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238 Pinout
CD54HC138, CD54HCT138, CD54HC238, CD54HCT238 (CERDIP) CD74HC138, CD74HCT138, CD74HCT238 (PDIP, SOIC) CD74HC238 (PDIP, SOIC, SOP) TOP VIEW
A0 1 A1 2 A2 3 E1 4 E2 5 E3 6 (Y7) Y7 7 GND 8 16 VCC 15 Y0 (Y0) 14 Y1 (Y1) 13 Y2 (Y2) 12 Y3 (Y3) 11 Y4 (Y4) 10 Y5 (Y5) 9 Y6 (Y6)
Functional Diagram
CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238
Absolute Maximum Ratings
Thermal Information
Operating Conditions
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238
DC Electrical Specifications
VCC (V)
5.5 5.5 4.5 to 5.5
HCT Input Loading Table
INPUT A0-A2 E1, E2 E3 UNIT LOADS 1.5 1.25 1
NOTE: Unit Load is ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC.
TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS
PARAMETER HC TYPES Propagation Delay Address to Output
SYMBOL
CD54 / 74HC138, CD54 / 74HCT138, CD54 / 74HC238, CD54 / 74HCT238
PARAMETER Enable to Output HC / HCT138
SYMBOL
TEST CONDITIONS
Test Circuits and Waveforms
INVERTING OUTPUT
FIGURE 7. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated